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ducalexducalex
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rg_system+rg_gui: Improved overclock support
It now skews the audio and UART timings (within reason) to try to keep them functional. More could definitely be done, so far the results are mixed depending on the app. Also there's an Overclock directly in the options menu (disabled in release build) for easier experimentation.
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+80
-52
lines changed

2 files changed

+80
-52
lines changed

‎components/retro-go/rg_gui.c‎

Lines changed: 37 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1534,11 +1534,39 @@ static rg_gui_event_t custom_zoom_cb(rg_gui_option_t *option, rg_gui_event_t eve
15341534

15351535
static rg_gui_event_t overclock_update_cb(rg_gui_option_t *option, rg_gui_event_t event)
15361536
{
1537-
if (event == RG_DIALOG_PREV)
1538-
rg_system_set_overclock(rg_system_get_overclock() - 1);
1539-
else if (event == RG_DIALOG_NEXT)
1540-
rg_system_set_overclock(rg_system_get_overclock() + 1);
1541-
sprintf(option->value, "%dMhz", 240 + (rg_system_get_overclock() * 40));
1537+
switch ((int)option->arg)
1538+
{
1539+
case 0:
1540+
#if CONFIG_IDF_TARGET_ESP32
1541+
if (event == RG_DIALOG_PREV)
1542+
rg_system_set_overclock(rg_system_get_overclock() - 1);
1543+
else if (event == RG_DIALOG_NEXT)
1544+
rg_system_set_overclock(rg_system_get_overclock() + 1);
1545+
sprintf(option->value, "%dMhz", 240 + (rg_system_get_overclock() * 40));
1546+
#endif
1547+
break;
1548+
case 1:
1549+
// sprintf(option->value, "%dMhz", RG_SCREEN_SPEED / 1000 / 1000);
1550+
break;
1551+
case 2:
1552+
// sprintf(option->value, "%dMhz", RG_STORAGE_SDSPI_SPEED / 1000 / 1000);
1553+
break;
1554+
}
1555+
return RG_DIALOG_VOID;
1556+
}
1557+
1558+
static rg_gui_event_t overclock_cb(rg_gui_option_t *option, rg_gui_event_t event)
1559+
{
1560+
if (event == RG_DIALOG_ENTER)
1561+
{
1562+
const rg_gui_option_t options[] = {
1563+
{0, _("CPU"), "-", RG_DIALOG_FLAG_NORMAL, &overclock_update_cb},
1564+
{1, _("LCD"), "-", RG_DIALOG_FLAG_DISABLED, &overclock_update_cb},
1565+
{2, _("SD"), "-", RG_DIALOG_FLAG_DISABLED, &overclock_update_cb},
1566+
RG_DIALOG_END,
1567+
};
1568+
rg_gui_dialog(option->label, options, 0);
1569+
}
15421570
return RG_DIALOG_VOID;
15431571
}
15441572

@@ -1999,6 +2027,9 @@ void rg_gui_options_menu(void)
19992027
{0, _("Border"), "-", RG_DIALOG_FLAG_NORMAL, &border_update_cb},
20002028
{0, _("Speed"), "-", RG_DIALOG_FLAG_NORMAL, &speedup_update_cb},
20012029
// {0, _("Misc options"), NULL, RG_DIALOG_FLAG_NORMAL, &misc_options_cb},
2030+
#if !RG_BUILD_RELEASE
2031+
{0, _("Overclock"), NULL, RG_DIALOG_FLAG_NORMAL, &overclock_cb},
2032+
#endif
20022033
{0, _("Emulator options"), NULL, RG_DIALOG_FLAG_NORMAL, &app_options_cb},
20032034
RG_DIALOG_END,
20042035
};
@@ -2090,7 +2121,7 @@ void rg_gui_debug_menu(void)
20902121
{0, "Battery ", battery_info, RG_DIALOG_FLAG_NORMAL, NULL},
20912122
{0, "Blit time ", frame_time, RG_DIALOG_FLAG_NORMAL, NULL},
20922123
RG_DIALOG_SEPARATOR,
2093-
{0, "Overclock", "-", RG_DIALOG_FLAG_NORMAL, &overclock_update_cb},
2124+
{0, "Overclock", NULL, RG_DIALOG_FLAG_NORMAL, &overclock_cb},
20942125
{1, "Reboot to firmware", NULL, RG_DIALOG_FLAG_NORMAL, NULL},
20952126
{2, "Clear cache ", NULL, RG_DIALOG_FLAG_NORMAL, NULL},
20962127
{3, "Save screenshot", NULL, RG_DIALOG_FLAG_NORMAL, NULL},

‎components/retro-go/rg_system.c‎

Lines changed: 43 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1092,35 +1092,24 @@ int rg_system_get_log_level(void)
10921092

10931093
void rg_system_set_overclock(int level)
10941094
{
1095-
#if defined(ESP_PLATFORM) && CONFIG_IDF_TARGET_ESP32
1096-
// None of this is documented by espressif but can be found in the file rtc_clk.c
1095+
#if CONFIG_IDF_TARGET_ESP32
1096+
// #include "driver/uart.h"
1097+
// None of this is documented by espressif but there are comments to be found in the file `rtc_clk.c`
10971098
#define I2C_BBPLL 0x66
1098-
#define I2C_BBPLL_ENDIV5 11
1099-
#define I2C_BBPLL_BBADC_DSMP 9
11001099
#define I2C_BBPLL_HOSTID 4
1101-
#define I2C_BBPLL_OC_LREF 2
1102-
#define I2C_BBPLL_OC_DIV_7_0 3
1103-
#define I2C_BBPLL_OC_DCUR 5
1104-
#define BBPLL_ENDIV5_VAL_320M 0x43
1105-
#define BBPLL_BBADC_DSMP_VAL_320M 0x84
1100+
#define I2C_BBPLL_ENDIV5 11 // This controls the BBPLL frequency. It should already be at 480Mhz
1101+
#define I2C_BBPLL_BBADC_DSMP 9 // This controls the BBPLL frequency. It should already be at 480Mhz
1102+
#define I2C_BBPLL_OC_LREF 2 // This is specific to the installed crystal (24/26/40), we don't care
1103+
#define I2C_BBPLL_OC_DIV_7_0 3 // This is the PLL divider to get the CPU clock (our main concern)
1104+
#define I2C_BBPLL_OC_DCUR 5 // This is specific to the installed crystal (24/26/40), we don't care
11061105
#define BBPLL_ENDIV5_VAL_480M 0xc3
11071106
#define BBPLL_BBADC_DSMP_VAL_480M 0x74
11081107
extern void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
11091108
extern uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
1109+
extern int uart_set_baudrate(int uart_num, uint32_t baud_rate);
11101110

1111-
uint8_t div_ref = 0;
1112-
uint8_t div7_0 = (level + 4) * 8;
1113-
uint8_t div10_8 = 0;
1114-
uint8_t lref = 0;
1115-
uint8_t dcur = 6;
1116-
uint8_t bw = 3;
1117-
uint8_t ENDIV5 = BBPLL_ENDIV5_VAL_480M;
1118-
uint8_t BBADC_DSMP = BBPLL_BBADC_DSMP_VAL_480M;
1119-
uint8_t BBADC_OC_LREF = (lref << 7) | (div10_8 << 4) | (div_ref);
1120-
uint8_t BBADC_OC_DIV_7_0 = div7_0;
1121-
uint8_t BBADC_OC_DCUR = (bw << 6) | dcur;
1122-
1123-
static uint8_t BASE_ENDIV5, BASE_BBADC_DSMP, BASE_BBADC_OC_LREF, BASE_BBADC_OC_DIV_7_0, BASE_BBADC_OC_DCUR, BASE_SAVED;
1111+
static uint8_t BASE_ENDIV5, BASE_BBADC_DSMP, BASE_BBADC_OC_LREF, BASE_BBADC_OC_DIV_7_0, BASE_BBADC_OC_DCUR;
1112+
static bool BASE_SAVED = false;
11241113
if (!BASE_SAVED)
11251114
{
11261115
BASE_ENDIV5 = rom_i2c_readReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_ENDIV5);
@@ -1131,48 +1120,56 @@ void rg_system_set_overclock(int level)
11311120
BASE_SAVED = true;
11321121
}
11331122

1134-
if (level == 0)
1135-
{
1136-
ENDIV5 = BASE_ENDIV5;
1137-
BBADC_DSMP = BASE_BBADC_DSMP;
1138-
BBADC_OC_LREF = BASE_BBADC_OC_LREF;
1139-
BBADC_OC_DIV_7_0 = BASE_BBADC_OC_DIV_7_0;
1140-
BBADC_OC_DCUR = BASE_BBADC_OC_DCUR;
1141-
}
1142-
else if (level < -4 || level > 3)
1123+
uint8_t ENDIV5 = BASE_ENDIV5;
1124+
uint8_t BBADC_DSMP = BASE_BBADC_DSMP;
1125+
uint8_t BBADC_OC_LREF = BASE_BBADC_OC_LREF;
1126+
uint8_t BBADC_OC_DIV_7_0 = BASE_BBADC_OC_DIV_7_0;
1127+
uint8_t BBADC_OC_DCUR = BASE_BBADC_OC_DCUR;
1128+
1129+
if (level < -4 || level > 3)
11431130
{
11441131
RG_LOGW("Invalid level %d, min:-4 max:3", level);
11451132
return;
11461133
}
1134+
else if (level != 0)
1135+
{
1136+
uint8_t div_ref = 0;
1137+
uint8_t div7_0 = (level + 4) * 8;
1138+
uint8_t div10_8 = 0;
1139+
uint8_t lref = 0;
1140+
uint8_t dcur = 6;
1141+
uint8_t bw = 3;
1142+
ENDIV5 = BBPLL_ENDIV5_VAL_480M;
1143+
BBADC_DSMP = BBPLL_BBADC_DSMP_VAL_480M;
1144+
BBADC_OC_LREF = (lref << 7) | (div10_8 << 4) | (div_ref);
1145+
BBADC_OC_DIV_7_0 = div7_0;
1146+
BBADC_OC_DCUR = (bw << 6) | dcur;
1147+
}
11471148

11481149
RG_LOGW(" ");
11491150
RG_LOGW("BASE: %d %d %d %d %d", BASE_ENDIV5, BASE_BBADC_DSMP, BASE_BBADC_OC_LREF, BASE_BBADC_OC_DIV_7_0, BASE_BBADC_OC_DCUR);
11501151
RG_LOGW("NEW : %d %d %d %d %d", ENDIV5, BBADC_DSMP, BBADC_OC_LREF, BBADC_OC_DIV_7_0, BBADC_OC_DCUR);
11511152
RG_LOGW(" ");
11521153

1154+
RG_LOGW("Preparing peripherals for the speed change...");
1155+
rg_task_delay(10); // Wait for the log to be sent
1156+
1157+
float overclock_ratio = (240 + (level * 40)) / 240.f;
1158+
rg_audio_set_sample_rate(app.sampleRate / overclock_ratio);
1159+
uart_set_baudrate(0, 115200 / overclock_ratio);
1160+
1161+
RG_LOGW("Updating clock registers!");
11531162
rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_ENDIV5, ENDIV5);
11541163
rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_BBADC_DSMP, BBADC_DSMP);
1155-
rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_OC_LREF, BBADC_OC_LREF);
1164+
// rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_OC_LREF, BBADC_OC_LREF);
11561165
rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_OC_DIV_7_0, BBADC_OC_DIV_7_0);
1157-
rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_OC_DCUR, BBADC_OC_DCUR);
1158-
1166+
// rom_i2c_writeReg(I2C_BBPLL, I2C_BBPLL_HOSTID, I2C_BBPLL_OC_DCUR, BBADC_OC_DCUR);
11591167
RG_LOGW("Overclock applied!");
1160-
#if 0
1161-
extern uint64_t esp_rtc_get_time_us(void);
1162-
uint64_t start = esp_rtc_get_time_us();
1163-
int64_t end = rg_system_timer() + 1000000;
1164-
while (rg_system_timer() < end)
1165-
continue;
1166-
overclock_ratio = 1000000.f / (esp_rtc_get_time_us() - start);
1167-
#endif
1168-
// overclock_ratio = (240 + (app.overclock * 40)) / 240.f;
11691168

1170-
// rg_audio_set_sample_rate(app.sampleRate / overclock_ratio);
1169+
app.overclock = level;
11711170
#else
11721171
RG_LOGE("Overclock not supported on this platform!");
11731172
#endif
1174-
1175-
app.overclock = level;
11761173
}
11771174

11781175
int rg_system_get_overclock(void)

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