Merge pull request #31 from codeplaysoftware/add-codasip-update-posts

Add Codasip Update Posts

Author: scottstraughan

_collections/_updates/2023-05-02-risc-v-customization-hw-sw-co-optimization-and-custom-compute.md

@@ -0,0 +1,18 @@
+---
+title: "RISC-V customization, HW/SW co-optimization, and custom compute"
+date: 2023-05-02
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - customization
+link: https://codasip.com/2023/05/02/riscv-customization-hardware-software-co-optimization-custom-compute/
+---
+
+Do we still need to introduce and define RISC-V? You know, the open-source instruction set architecture (ISA) that is
+gaining popularity thanks to its flexibility, scalability, and modularity. Okay, we just did, just to be sure we are all
+on the same page. One of the key benefits and the main “raison d’être” of RISC-V is the possibility to tailor both the
+instruction set (ISA) and the internal design (microarchitecture) of the processor to meet specific application
+requirements. This customization capability extends to custom compute solutions, enabling developers to create hardware
+optimized for their workloads. In this blog post, let’s explore the benefits of RISC-V customization and custom compute,
+and industry applications. 

_collections/_updates/2023-05-23-no-one-size-fits-all-approach-to-risc-v-processor-optimization.md

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+---
+title: "No one-size-fits-all approach to RISC-V processor optimization"
+date: 2023-05-23
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - optimization
+link: https://codasip.com/2023/05/23/no-one-size-fits-all-approach-to-processor-optimization/
+---
+
+As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their
+limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to
+enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each
+application will have their own requirements, there are actually different ways to optimize. You can modify a processor
+IP at different levels, each with its own benefits. In this blog post, let’s define and explore the different levels of
+processor optimization. From configuration to customization, let’s see how you can use them to create optimized
+processors that meet specific requirements.

_collections/_updates/2023-07-25-re-targetable-llvm-c-c-compiler-for-risc-v.md

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+---
+title: "Re-targetable LLVM C/C++ compiler for RISC-V"
+date: 2023-07-25
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - llvm
+link: https://codasip.com/2023/07/25/re-targetable-llvm-c-c-plus-plus-compiler-for-riscv/
+---
+
+RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and
+differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as
+integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the
+reasons for adding instructions are many: better performance, smaller memory footprint, lower power consumption, or
+anything in between.
+
+This means one important thing: the software (the final application(s)) is compiled for the particular RISC-V ISA. The
+software development kit (SDK) must know which ISA modules the RISC-V processor implements, so it can automatically
+leverage them. This includes both standard instructions and custom instructions.

_collections/_updates/2023-08-31-how-the-syclops-project-democratizes-ai-acceleration.md

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+---
+title: "How the SYCLOPS project democratizes AI acceleration"
+date: 2023-08-31
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - ai 
+  - ml
+link: https://codasip.com/2023/08/31/how-the-syclops-project-democratizes-ai-acceleration/
+---
+
+Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the
+rise of Artificial Intelligence (AI) and Machine Learning (ML), these areas have become a key focus for us. At the
+beginning of 2023, we joined the New Horizon Europe Project SYCLOPS (Scaling extreme analYtics with Cross-architecture
+acceLeration based on OPen Standards). This project aims to advance AI and data mining for extremely large and diverse
+data. The program brings together eight leading European organizations with the goal of achieving ground-breaking
+advances in the scalability of extreme data analytics via fully open AI acceleration. Codasip’s role is to develop
+domain-specific accelerators based on the RISC-V Vector extension (RVV). We will do this using the design automation
+tool Codasip Studio and the CodAL processor description language.

_collections/_updates/2023-10-17-codasip-700-risc-v-processor-family-bringing-the-world-of-custom-compute-to-everyone.md

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+---
+title: "Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone"
+date: 2023-10-17
+layout: update
+tags:
+  - codasip
+  - risc-v
+link: https://codasip.com/2023/10/17/codasip-700-riscv-processor-family-bringing-the-world-of-custom-compute-to-everyone/
+---
+
+Today, technology innovators must have new ways to create differentiated products. How are they supposed to meet the
+demand for more computational performance when semiconductor scaling laws are showing their limits? There is only one
+way: having a compute that is custom for specific needs. And what do we need for that? Several aspects: Architecture
+optimization, application profiling, hardware/software co-optimization, and domain-specific acceleration built on a
+strong design foundation. And this is great, but the design process must be as streamlined as possible to improve
+efficiency and reduce time to market while allowing companies to take ownership and remain flexible. 

_collections/_updates/2024-01-31-effectively-hiding-sensitive-data-with-risc-v-zk-and-custom-instructions.md

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+---
+title: "Effectively hiding sensitive data with RISC-V Zk and custom instructions"
+date: 2024-01-31
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - cryptographic
+link: https://codasip.com/2024/01/31/effectively-hiding-sensitive-data-with-risc-v-zk-and-custom-instructions/
+---
+
+Cryptographic hash functions play a critical role in computer security providing a one-way transformation of sensitive
+data. Many information-security applications benefit from using hash functions, specifically digital signatures, message
+authentication codes, and other forms of authentication. The calculation of hash functions such as SHA512, SHA256, MD5
+etc is a potential playground for Custom Compute. This is where the ISA flexibility enabled by RISC-V and empowered by
+the Zk extension, as well as the ability to merge inherently sequential bit manipulations in custom instructions help to
+improve the performance.   

_collections/_updates/2024-03-20-a-custom-risc-v-vector-instruction-to-accelerate-structured-sparse-matrix-multiplications.md

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+---
+title: "A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications"
+date: 2024-03-20
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - ai
+  - matrix
+link: https://codasip.com/2024/03/20/a-custom-risc-v-vector-instruction/
+---
+
+A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models,
+particularly focusing on structured sparsity. Structured sparsity involves a predefined pattern of zero values in the
+matrix, unlike unstructured sparsity where zeros can occur anywhere. The research was conducted by Democritus University
+of Thrace (DUTH) in Greece and was sponsored by Codasip University Program.
+
+Structured sparsity has emerged as a promising approach to streamline the complexity of modern Machine Learning (ML)
+applications and facilitate the handling of sparse data in hardware. Accelerating ML models, whether for training or
+inference, heavily relies on efficient execution of equivalent matrix multiplications, which are often performed on
+vector processors or custom matrix engines.

_collections/_updates/2024-04-04-custom-compute-for-edge-ai-accelerating-innovation-with-lund-university-and-codasip-university-program.md

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+---
+title: "Custom Compute for Edge AI: Accelerating innovation with Lund University and Codasip University Program"
+date: 2024-04-04
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - edge
+  - hpc
+  - ai
+link: https://codasip.com/2024/04/04/custom-compute-for-edge-ai/
+---
+
+In recent years, the rapid advancement and adoption of Artificial Intelligence (AI) on the edge has brought about a
+surge in development. As AI models like ChatGPT become more prevalent and accurate, the computational requirements for
+inference also escalate. This necessitates architectural innovations aimed at reducing both power consumption and
+latency.

_collections/_updates/2024-06-28-sunny-skies-and-electric-energy-risc-v-summit-europe-2024-shines-in-munich.md

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+---
+title: "Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich"
+date: 2024-06-28
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - energy
+link: https://codasip.com/2024/06/28/sunny-skies-and-electric-energy-risc-v-summit-europe-2024-shines-in-munich/
+---
+
+As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year
+was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall,
+while I was heading to San Francisco with a bunch of other Codasippers some of the Codasip team was headed for the
+RISC-V Summit in Munich.
+
+The event is nowhere on the scale that it used to be. In fact, the entire exhibit could probably now fill one floor of
+the Moscone. But the level of foot traffic remained high throughout the show and the team and I spoke to a fair number
+of people over the 3 days of exhibits. I was impressed with the number of fresh faces and new startups. There was
+something interesting to see in all corners of the tradeshow floor. And… incredibly the weather was, well, incredible.

_collections/_updates/2024-07-16-dac-2024-showcasing-the-future-of-risc-v-through-eda.md

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+---
+title: "DAC 2024 – Showcasing the future of RISC-V through EDA"
+date: 2024-07-16
+layout: update
+tags:
+  - codasip
+  - risc-v
+  - conference
+  - summit
+link: https://codasip.com/2024/07/16/dac-2024-showcasing-the-future-of-risc-v-through-eda/
+---
+
+This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last
+year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a
+sunny, hot week, only interrupted by a thunderstorm that shook up some conference attendees (including me!) on the
+Wednesday afternoon. However, thunderbolts and lightning were also present in a less literal form as massive applause
+following the many talks, and an abundance of photos and selfies taken in the expo hall and at the social events.
+
+![Thumbnail](https://codasip.com/wp-content/uploads/2024/06/Picture1.png)

_layouts/update.html

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