7474-include_lib (" jit.hrl" ).
7575
7676-include (" primitives.hrl" ).
77+ -include (" term.hrl" ).
7778
7879-define (ASSERT (Expr ), true = Expr ).
7980
@@ -1301,7 +1302,7 @@ if_block_cond(
13011302 I1 = jit_armv6m_asm :mov (Temp , Reg ),
13021303 Stream1 = StreamModule :append (Stream0 , I1 ),
13031304 State1 = State0 # state {stream = Stream1 },
1304- State2 = and_ (State1 # state {available_regs = AT }, Temp , Mask ),
1305+ { State2 , Temp } = and_ (State1 # state {available_regs = AT }, { free , Temp } , Mask ),
13051306 Stream2 = State2 # state .stream ,
13061307 % Compare with value
13071308 I2 = jit_armv6m_asm :cmp (Temp , Val ),
@@ -1320,7 +1321,7 @@ if_block_cond(
13201321) when ? IS_GPR (Reg ) ->
13211322 % AND with mask
13221323 OffsetBefore = StreamModule :offset (Stream0 ),
1323- State1 = and_ (State0 , Reg , Mask ),
1324+ { State1 , Reg } = and_ (State0 , RegTuple , Mask ),
13241325 Stream1 = State1 # state .stream ,
13251326 % Compare with value
13261327 I2 = jit_armv6m_asm :cmp (Reg , Val ),
@@ -2508,34 +2509,34 @@ get_module_index(
25082509% % JIT currentl calls this with two values: ?TERM_PRIMARY_CLEAR_MASK (-4) to
25092510% % clear bits and ?TERM_BOXED_TAG_MASK (0x3F). We can avoid any literal pool
25102511% % by using BICS for -4.
2511- and_ (# state {stream_module = StreamModule , stream = Stream0 } = State0 , Reg , 16#FFFFFF ) ->
2512+ and_ (# state {stream_module = StreamModule , stream = Stream0 } = State0 , { free , Reg } , 16#FFFFFF ) ->
25122513 I1 = jit_armv6m_asm :lsls (Reg , Reg , 8 ),
25132514 I2 = jit_armv6m_asm :lsrs (Reg , Reg , 8 ),
25142515 Stream1 = StreamModule :append (Stream0 , <<I1 /binary , I2 /binary >>),
2515- State0 # state {stream = Stream1 };
2516+ { State0 # state {stream = Stream1 }, Reg };
25162517and_ (
25172518 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
2518- Reg ,
2519+ { free , Reg } ,
25192520 Val
25202521) when Val < 0 andalso Val >= - 256 ->
25212522 State1 = mov_immediate (State0 # state {available_regs = AT }, Temp , bnot (Val )),
25222523 Stream1 = State1 # state .stream ,
25232524 I = jit_armv6m_asm :bics (Reg , Temp ),
25242525 Stream2 = StreamModule :append (Stream1 , I ),
2525- State1 # state {available_regs = [Temp | AT ], stream = Stream2 };
2526+ { State1 # state {available_regs = [Temp | AT ], stream = Stream2 }, Reg };
25262527and_ (
25272528 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
2528- Reg ,
2529+ { free , Reg } ,
25292530 Val
25302531) ->
25312532 State1 = mov_immediate (State0 # state {available_regs = AT }, Temp , Val ),
25322533 Stream1 = State1 # state .stream ,
25332534 I = jit_armv6m_asm :ands (Reg , Temp ),
25342535 Stream2 = StreamModule :append (Stream1 , I ),
2535- State1 # state {available_regs = [Temp | AT ], stream = Stream2 };
2536+ { State1 # state {available_regs = [Temp | AT ], stream = Stream2 }, Reg };
25362537and_ (
25372538 # state {stream_module = StreamModule , available_regs = []} = State0 ,
2538- Reg ,
2539+ { free , Reg } ,
25392540 Val
25402541) when Val < 0 andalso Val >= - 256 ->
25412542 % No available registers, use r0 as temp and save it to r12
@@ -2552,10 +2553,10 @@ and_(
25522553 % Restore r0 from r12
25532554 Restore = jit_armv6m_asm :mov (r0 , ? IP_REG ),
25542555 Stream4 = StreamModule :append (Stream3 , Restore ),
2555- State0 # state {stream = Stream4 };
2556+ { State0 # state {stream = Stream4 }, Reg };
25562557and_ (
25572558 # state {stream_module = StreamModule , available_regs = []} = State0 ,
2558- Reg ,
2559+ { free , Reg } ,
25592560 Val
25602561) ->
25612562 % No available registers, use r0 as temp and save it to r12
@@ -2572,7 +2573,17 @@ and_(
25722573 % Restore r0 from r12
25732574 Restore = jit_armv6m_asm :mov (r0 , ? IP_REG ),
25742575 Stream4 = StreamModule :append (Stream3 , Restore ),
2575- State0 # state {stream = Stream4 }.
2576+ {State0 # state {stream = Stream4 }, Reg };
2577+ and_ (
2578+ # state {stream_module = StreamModule , available_regs = [ResultReg | AT ], used_regs = UR } =
2579+ State0 ,
2580+ Reg ,
2581+ ? TERM_PRIMARY_CLEAR_MASK
2582+ ) ->
2583+ I1 = jit_armv6m_asm :lsrs (ResultReg , Reg , 2 ),
2584+ I2 = jit_armv6m_asm :lsls (ResultReg , ResultReg , 2 ),
2585+ Stream1 = StreamModule :append (State0 # state .stream , <<I1 /binary , I2 /binary >>),
2586+ {State0 # state {stream = Stream1 , available_regs = AT , used_regs = [ResultReg | UR ]}, ResultReg }.
25762587
25772588or_ (
25782589 # state {stream_module = StreamModule , available_regs = [Temp | AT ]} = State0 ,
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