# Release Notes for **GHRD for Agilex 3 FPGA C-Series 25.3** (#2)

## Release Information:
Quartus Version: 25.3 Build 109 09/24/2025 SC Pro Edition
Tag: QPDS25.3_REL_GSRD_PR
Build: socfpga_ghrd_lth_base/25.3/390

## New Features and Enhancements
none

## Issues Resolved
- Fixed incorrect weak pull up assignment. Applicable for HPS IO pin will be assigned with 20kOhm pullup resistor.
- Disable EMIF REQ and WEQ calibration in EMIF IP to reduce boot time.

## Latest Known Issues
None

Author: gohshunjing

README.md

@@ -2,7 +2,7 @@
 
 This repository contains Golden Hardware Reference Design (GHRD) for Agilex 3 C-Series System On Chip (SoC) FPGA.
 The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.
-Refer to the [Altera FPGA Developer Site](https://altera-fpga.github.io/latest/ed-demo-list/ed-list/) for information about GSRD.
+Refer to the [HPS GSRD User Guide for the Agilex 3 C-Series Development Kit](https://altera-fpga.github.io/latest/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/) for information about GSRD.
 
 The [designs](#designs) are stored in individual folders. Each design can be opened, modified and compiled by using Quartus Prime software.
 GHRD releases are created for each version of Quartus Prime Software. It is recommended to use the release for your version of Quartus Prime.
@@ -27,25 +27,26 @@ This is applicable to all designs.
 3. modify and compile the [designs](#designs) with Quartus Prime.
 
 ## Dependency
-* Altera Quartus Prime 25.1.1
+* Altera Quartus Prime 25.3
 * Supported Board
   - Agilex 3 FPGA and SoC C-Series Development Kit: [Devkit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/851698/current)
   ![Agilex 3 FPGA and SoC C-Series Development Kit](images/agilex3_soc_devkit.png)
 
 ## Tested Platform for the GHRD Build Flow
 * SUSE Linux Enterprise Server 15 SP4
 
+
 ## Setup
 
 Several tools are required to be in the path.
 
-* Altera Quartus Prime 25.1.1
+* Altera Quartus Prime 25.3
 * Python 3.11.5 (only required when using command line to build)
 
 ### Example Setup for Altera Quartus Prime tools
 This is recommended, when using command line to build.
 ```bash
-export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1.1/quartus
+export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.3/quartus
 ```
 Note: Adapt the path above to where Quartus Prime is installed.
 

a3cw135-devkit-oobe/legacy-baseline/Makefile

@@ -81,7 +81,9 @@ $(strip $(1))-qsys-ip-file-upgrade: pre-prep
 	quartus_sh --ip_upgrade $(PROJECT_NAME) -revision $(strip $(1)) -mode all
 
 $(strip $(1))-ip-upgrade: pre-prep | output_files
+	chmod a-w $(strip $(1)).qsf
 	flock --verbose output_files/ipupgrade.lock $(MAKE) $(strip $(1))-qsys-ip-file-upgrade
+	chmod +w $(strip $(1)).qsf
 
 $(strip $(1))-generate-design :
 
@@ -108,7 +110,7 @@ output_files $(INSTALL_ROOT):
 
 output_files/pre-prep.done: | output_files
  	# Write protect QPF so it doesn't get modified when switching revisions
-	chmod a-w $(PROJECT_NAME).qpf 
+	chmod a-w $(PROJECT_NAME).qpf
 	touch $@
 
 output_files/prep-%.done: output_files/pre-prep.done | output_files
@@ -144,7 +146,7 @@ output_files/%.sof: output_files/prep-%.done
 	quartus_sta top -c $* --mode=finalize
 	quartus_asm top -c $*
 	quartus_pow top -c $*
-	mv $*.qptc output_files/$*.qptc
+	mv $*.qpta output_files/$*.qpta
 
 # Clean all files
 .PHONY: clean

a3cw135-devkit-oobe/legacy-baseline/README.md

@@ -1,13 +1,13 @@
-# a3cw135-devkit-oobe-legacy-baseline
+# HPS Baseline System Example Design for Agilex 3 FPGA and SoC C-Series Development Kit
 
 This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 3 FPGA and SoC C-Series Development Kit.
 
 ## Description
 
-Agilex 3 GHRD is a reference design for Intel Agilex 3 System On Chip (SoC) FPGA.
+Agilex 3 GHRD is a reference design for Altera Agilex 3 System On Chip (SoC) FPGA.
 
 The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.
-Refer to the [Altera FPGA Developer Site](https://altera-fpga.github.io/latest/ed-demo-list/ed-list/) for information about GSRD.
+Refer to the [HPS GSRD User Guide for the Agilex 3 C-Series Development Kit](https://altera-fpga.github.io/latest/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/) for information about GSRD.
 
 The design uses HPS First configuration mode.
 
@@ -27,20 +27,27 @@ This reference design demonstrates the following system integration between Hard
 ## Project Details
 
 - **Family**: Agilex 3
-- **Quartus Version**: 25.1.1
+- **Quartus Version**: 25.3
 - **Development Kit**: Agilex 3 FPGA and SoC C-Series Development Kit DK-A3W135BM16AEA
 - **Device Part**: A3CW135BM16AE6S
-- **Category**: Golden Hardware Reference Design (GHRD)
+- **Category**: HPS
 - **Source**: Quartus Prime Pro
 - **URL**: https://www.github.com/altera-fpga/agilex3c-ed-gsrd
 - **Design Package**: a3cw135-devkit-oobe-legacy-baseline.zip
-- **Documentations**: Link TBD - Refer to this README.
+
+## Documentations
+
+- **Title**: HPS GSRD User Guide for the Agilex 3 C-Series Development Kit
+**URL**: https://altera-fpga.github.io/latest/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/
+- **Title**: GHRD README for the Agilex 3 FPGA and SoC C-Series Development Kit
+**URL**: https://github.com/altera-fpga/agilex3c-ed-gsrd/blob/main/a3cw135-devkit-oobe/legacy-baseline/README.md
+
 ## GHRD Overview
 ![GHRD_overview](/images/agilex3_ghrd_overview.svg)
 
 ## Hard Processor System (HPS)
 The GHRD HPS configuration matches the board schematic.
-Refer to [Hard Processor System Technical Reference Manual: Agilex 3 SoCs](https://www.intel.com/content/www/us/en/docs/programmable/848530/current) and [Hard Processor System Component Reference Manual: Agilex 3 SoCs](https://www.intel.com/content/www/us/en/docs/programmable/851703/current) for more information on HPS configuration.
+Refer to [Hard Processor System Technical Reference Manual: Agilex 3 SoCs](https://www.intel.com/content/www/us/en/docs/programmable/848530/current/hard-processor-system-technical-reference.html) and [Hard Processor System Component Reference Manual: Agilex 3 SoCs](https://www.intel.com/content/www/us/en/docs/programmable/851703/current) for more information on HPS configuration.
 
 ## HPS External Memory Interfaces (EMIF)
 The GHRD HPS EMIF configuration matches the board schematic.
@@ -50,7 +57,8 @@ Refer to [External Memory Interfaces (EMIF) IP User Guide: Agilex 3 FPGAs and So
 Bridges are used to move data between FPGA fabric and HPS logic.
 Refer to [HPS Bridges](https://www.intel.com/content/www/us/en/docs/programmable/851703/current/hps-fpga-bridges.html)
 
-The HPS address map and the FPGA address map are the same for Agilex 3. Refer to [Total Address Map Graphical](https://www.intel.com/content/www/us/en/docs/programmable/848530/current/total-address-map-graphical.html) for more information.
+The HPS address map and the FPGA address map are the same for Agilex 3.
+Refer to [Total Address Map Graphical](https://www.intel.com/content/www/us/en/docs/programmable/848530/current/total-address-map-graphical.html) for more information.
 
 Therefore, when accessing HPS logic in uboot or linux, the base address would be the same as, when using [Debug Subsystem](#Debug-Subsystem) from FPGA fabric.