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alexforencichalexforencich
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Add ZCU106 example design
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‎example/ZCU106/fpga/Makefile

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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

‎example/ZCU106/fpga/README.md

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# Verilog Ethernet ZCU106 Example Design
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## Introduction
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This example design targets the Xilinx ZCU106 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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FPGA: xczu7ev-ffvc1156-2-e
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PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the ZCU106 board with Vivado. Then run
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netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
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entered into netcat will be echoed back after pressing enter.
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‎example/ZCU106/fpga/common/vivado.mk

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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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vivado: $(FPGA_TOP).xpr
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vivado $(FPGA_TOP).xpr
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -nojournal -nolog -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";

‎example/ZCU106/fpga/fpga.xdc

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# XDC constraints for the Xilinx ZCU106 board
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# part: xczu7ev-ffvc1156-2-e
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# General configuration
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# System clocks
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# 125 MHz
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set_property -dict {LOC H9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC G9 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# LEDs
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set_property -dict {LOC AL11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AL13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC AK13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC AE15 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_property -dict {LOC AM8 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
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set_property -dict {LOC AM9 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
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set_property -dict {LOC AM10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
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set_property -dict {LOC AM11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
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# Reset button
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set_property -dict {LOC G13 IOSTANDARD LVCMOS12} [get_ports reset]
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# Push buttons
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set_property -dict {LOC AG13 IOSTANDARD LVCMOS12} [get_ports btnu]
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set_property -dict {LOC AK12 IOSTANDARD LVCMOS12} [get_ports btnl]
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set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports btnd]
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set_property -dict {LOC AC14 IOSTANDARD LVCMOS12} [get_ports btnr]
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set_property -dict {LOC AL10 IOSTANDARD LVCMOS12} [get_ports btnc]
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# DIP switches
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set_property -dict {LOC A17 IOSTANDARD LVCMOS18} [get_ports {sw[0]}]
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set_property -dict {LOC A16 IOSTANDARD LVCMOS18} [get_ports {sw[1]}]
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set_property -dict {LOC B16 IOSTANDARD LVCMOS18} [get_ports {sw[2]}]
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set_property -dict {LOC B15 IOSTANDARD LVCMOS18} [get_ports {sw[3]}]
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set_property -dict {LOC A15 IOSTANDARD LVCMOS18} [get_ports {sw[4]}]
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set_property -dict {LOC A14 IOSTANDARD LVCMOS18} [get_ports {sw[5]}]
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set_property -dict {LOC B14 IOSTANDARD LVCMOS18} [get_ports {sw[6]}]
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set_property -dict {LOC B13 IOSTANDARD LVCMOS18} [get_ports {sw[7]}]
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# UART
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set_property -dict {LOC AL17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
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set_property -dict {LOC AH17 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
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set_property -dict {LOC AM15 IOSTANDARD LVCMOS12} [get_ports uart_rts]
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set_property -dict {LOC AP17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_cts]
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# SFP+ Interface
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set_property -dict {LOC AA2 } [get_ports sfp0_rx_p] ;# MGTYRXP2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
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#set_property -dict {LOC AA1 } [get_ports sfp0_rx_n] ;# MGTYRXN2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
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set_property -dict {LOC Y4 } [get_ports sfp0_tx_p] ;# MGTYTXP2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
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#set_property -dict {LOC Y3 } [get_ports sfp0_tx_n] ;# MGTYTXN2_225 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y2
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set_property -dict {LOC W2 } [get_ports sfp1_rx_p] ;# MGTYRXP3_225 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
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#set_property -dict {LOC W1 } [get_ports sfp1_rx_n] ;# MGTYRXN3_225 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
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set_property -dict {LOC W6 } [get_ports sfp1_tx_p] ;# MGTYTXP3_225 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
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#set_property -dict {LOC W5 } [get_ports sfp1_tx_n] ;# MGTYTXN3_225 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y2
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set_property -dict {LOC U10 } [get_ports sfp_mgt_refclk_0_p] ;# MGTREFCLK1P_226 from U56 SI570 via U51 SI53340
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#set_property -dict {LOC U9 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK1N_226 from U56 SI570 via U51 SI53340
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#set_property -dict {LOC W10 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_225 from U20 CKOUT2 SI5328
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#set_property -dict {LOC W9 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_225 from U20 CKOUT2 SI5328
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#set_property -dict {LOC H11 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U20 CKIN1 SI5328
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#set_property -dict {LOC G11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U20 CKIN1 SI5328
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set_property -dict {LOC AE22 IOSTANDARD LVCMOS12} [get_ports sfp0_tx_disable_b]
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set_property -dict {LOC AF20 IOSTANDARD LVCMOS12} [get_ports sfp1_tx_disable_b]
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# 156.25 MHz MGT reference clock
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create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]
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# PCIe Interface
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#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AD4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AD3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AE6 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AE5 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1
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#set_property -dict {LOC AB8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_224
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#set_property -dict {LOC AB7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_224
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#set_property -dict {LOC L8 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_reset_n]
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# 100 MHz MGT reference clock
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#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
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‎example/ZCU106/fpga/fpga/Makefile

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# FPGA settings
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FPGA_PART = xczu7ev-ffvc1156-2-e
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FPGA_TOP = fpga
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FPGA_ARCH = zynquplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES += lib/eth/syn/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl
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# IP
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IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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‎example/ZCU106/fpga/ip/gtwizard_ultrascale_0.tcl

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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0
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set_property -dict [list CONFIG.preset {GTH-10GBASE-R}] [get_ips gtwizard_ultrascale_0]
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set_property -dict [list \
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CONFIG.CHANNEL_ENABLE {X0Y11 X0Y10} \
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CONFIG.TX_MASTER_CHANNEL {X0Y10} \
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CONFIG.RX_MASTER_CHANNEL {X0Y10} \
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CONFIG.TX_LINE_RATE {10.3125} \
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CONFIG.TX_REFCLK_FREQUENCY {156.25} \
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CONFIG.TX_USER_DATA_WIDTH {64} \
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CONFIG.TX_INT_DATA_WIDTH {32} \
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CONFIG.RX_LINE_RATE {10.3125} \
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CONFIG.RX_REFCLK_FREQUENCY {156.25} \
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CONFIG.RX_USER_DATA_WIDTH {64} \
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CONFIG.RX_INT_DATA_WIDTH {32} \
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CONFIG.RX_REFCLK_SOURCE {X0Y11 clk1+1 X0Y10 clk1+1} \
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CONFIG.TX_REFCLK_SOURCE {X0Y11 clk1+1 X0Y10 clk1+1} \
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CONFIG.FREERUN_FREQUENCY {125} \
21+
] [get_ips gtwizard_ultrascale_0]

‎example/ZCU106/fpga/lib/eth

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../../../../

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