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alexforencichalexforencich
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Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters
Signed-off-by: Alex Forencich <[email protected]>
1 parent 839fe8c commit baac5f8

18 files changed

+181
-226
lines changed

‎rtl/axis_baser_rx_64.v

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,6 @@ module axis_baser_rx_64 #
3636
parameter DATA_WIDTH = 64,
3737
parameter KEEP_WIDTH = (DATA_WIDTH/8),
3838
parameter HDR_WIDTH = 2,
39-
parameter PTP_PERIOD_NS = 4'h6,
40-
parameter PTP_PERIOD_FNS = 16'h6666,
4139
parameter PTP_TS_ENABLE = 0,
4240
parameter PTP_TS_FMT_TOD = 1,
4341
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
@@ -215,6 +213,9 @@ assign crc_valid[2] = crc_next == ~32'he60914ae;
215213
assign crc_valid[1] = crc_next == ~32'he38a6876;
216214
assign crc_valid[0] = crc_next == ~32'h6b87b1ec;
217215

216+
reg [4+16-1:0] last_ts_reg = 0;
217+
reg [4+16-1:0] ts_inc_reg = 0;
218+
218219
assign m_axis_tdata = m_axis_tdata_reg;
219220
assign m_axis_tkeep = m_axis_tkeep_reg;
220221
assign m_axis_tvalid = m_axis_tvalid_reg;
@@ -287,10 +288,6 @@ always @* begin
287288
// idle state - wait for packet
288289
reset_crc = 1'b1;
289290

290-
if (PTP_TS_ENABLE) begin
291-
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
292-
end
293-
294291
if (input_type_d1 == INPUT_TYPE_START_0 && cfg_rx_enable) begin
295292
// start condition
296293
reset_crc = 1'b0;
@@ -312,6 +309,10 @@ always @* begin
312309
reset_crc = 1'b1;
313310
end
314311

312+
if (PTP_TS_ENABLE) begin
313+
m_axis_tuser_next[1 +: PTP_TS_WIDTH] = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
314+
end
315+
315316
if (input_type_d0 == INPUT_TYPE_DATA) begin
316317
state_next = STATE_PAYLOAD;
317318
end else if (input_type_d0[3]) begin
@@ -410,19 +411,10 @@ always @(posedge clk) begin
410411

411412
if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
412413
lanes_swapped <= 1'b0;
413-
start_packet_reg <= 2'b01;
414414
input_type_d0 <= INPUT_TYPE_START_0;
415415
input_data_d0 <= encoded_rx_data_masked;
416-
417-
if (PTP_TS_FMT_TOD) begin
418-
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
419-
ptp_ts_reg[95:48] <= ptp_ts[95:48];
420-
end else begin
421-
ptp_ts_reg <= ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
422-
end
423416
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
424417
lanes_swapped <= 1'b1;
425-
start_packet_reg <= 2'b10;
426418
delay_type_valid <= 1'b1;
427419

428420
if (delay_type_valid) begin
@@ -431,13 +423,6 @@ always @(posedge clk) begin
431423
input_type_d0 <= INPUT_TYPE_IDLE;
432424
end
433425
input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data};
434-
435-
if (PTP_TS_FMT_TOD) begin
436-
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
437-
ptp_ts_reg[95:48] <= ptp_ts[95:48];
438-
end else begin
439-
ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
440-
end
441426
end else if (lanes_swapped) begin
442427
if (delay_type_valid) begin
443428
input_type_d0 <= delay_type;
@@ -519,6 +504,23 @@ always @(posedge clk) begin
519504
delay_type <= INPUT_TYPE_ERROR;
520505
end
521506

507+
if (delay_type == INPUT_TYPE_START_0 && delay_type_valid) begin
508+
start_packet_reg <= 2'b10;
509+
if (PTP_TS_FMT_TOD) begin
510+
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
511+
ptp_ts_reg[95:48] <= ptp_ts[95:48];
512+
end else begin
513+
ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
514+
end
515+
end
516+
517+
if (input_type_d0 == INPUT_TYPE_START_0) begin
518+
if (!lanes_swapped) begin
519+
start_packet_reg <= 2'b01;
520+
ptp_ts_reg <= ptp_ts;
521+
end
522+
end
523+
522524
input_type_d1 <= input_type_d0;
523525
input_data_d1 <= input_data_d0;
524526

@@ -530,6 +532,9 @@ always @(posedge clk) begin
530532

531533
crc_valid_save <= crc_valid;
532534

535+
last_ts_reg <= ptp_ts;
536+
ts_inc_reg <= ptp_ts - last_ts_reg;
537+
533538
if (rst) begin
534539
state_reg <= STATE_IDLE;
535540

‎rtl/axis_baser_tx_64.v

Lines changed: 66 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,6 @@ module axis_baser_tx_64 #
3939
parameter ENABLE_PADDING = 1,
4040
parameter ENABLE_DIC = 1,
4141
parameter MIN_FRAME_LENGTH = 64,
42-
parameter PTP_PERIOD_NS = 4'h6,
43-
parameter PTP_PERIOD_FNS = 16'h6666,
4442
parameter PTP_TS_ENABLE = 0,
4543
parameter PTP_TS_FMT_TOD = 1,
4644
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
@@ -199,6 +197,7 @@ reg [3:0] fcs_output_type_1;
199197

200198
reg [7:0] ifg_offset;
201199

200+
reg frame_start_reg = 1'b0, frame_start_next;
202201
reg frame_reg = 1'b0, frame_next;
203202
reg frame_error_reg = 1'b0, frame_error_next;
204203
reg [MIN_LEN_WIDTH-1:0] frame_min_count_reg = 0, frame_min_count_next;
@@ -208,12 +207,12 @@ reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
208207

209208
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
210209

211-
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
212-
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0, m_axis_ptp_ts_adj_next;
213-
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
214-
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
215-
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
216-
reg m_axis_ptp_ts_borrow_reg = 1'b0, m_axis_ptp_ts_borrow_next;
210+
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0;
211+
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_adj_reg = 0;
212+
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0;
213+
reg m_axis_ptp_ts_valid_reg = 1'b0;
214+
reg m_axis_ptp_ts_valid_int_reg = 1'b0;
215+
reg m_axis_ptp_ts_borrow_reg = 1'b0;
217216

218217
reg [31:0] crc_state_reg[7:0];
219218
wire [31:0] crc_state_next[7:0];
@@ -224,9 +223,12 @@ reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
224223
reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next;
225224
reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
226225

227-
reg [1:0] start_packet_reg = 2'b00, start_packet_next;
226+
reg [1:0] start_packet_reg = 2'b00;
228227
reg error_underflow_reg = 1'b0, error_underflow_next;
229228

229+
reg [4+16-1:0] last_ts_reg = 0;
230+
reg [4+16-1:0] ts_inc_reg = 0;
231+
230232
assign s_axis_tready = s_axis_tready_reg;
231233

232234
assign encoded_tx_data = encoded_tx_data_reg;
@@ -356,6 +358,7 @@ always @* begin
356358

357359
swap_lanes_next = swap_lanes_reg;
358360

361+
frame_start_next = 1'b0;
359362
frame_next = frame_reg;
360363
frame_error_next = frame_error_reg;
361364
frame_min_count_next = frame_min_count_reg;
@@ -368,31 +371,15 @@ always @* begin
368371
s_tdata_next = s_tdata_reg;
369372
s_empty_next = s_empty_reg;
370373

371-
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
372-
m_axis_ptp_ts_adj_next = m_axis_ptp_ts_adj_reg;
373-
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
374-
m_axis_ptp_ts_valid_next = 1'b0;
375-
m_axis_ptp_ts_valid_int_next = 1'b0;
376-
m_axis_ptp_ts_borrow_next = m_axis_ptp_ts_borrow_reg;
377-
378374
output_data_next = s_tdata_reg;
379375
output_type_next = OUTPUT_TYPE_IDLE;
380376

381-
start_packet_next = 2'b00;
382377
error_underflow_next = 1'b0;
383378

384379
if (s_axis_tvalid && s_axis_tready) begin
385380
frame_next = !s_axis_tlast;
386381
end
387382

388-
if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
389-
m_axis_ptp_ts_valid_next = m_axis_ptp_ts_valid_int_reg;
390-
m_axis_ptp_ts_adj_next[15:0] = m_axis_ptp_ts_reg[15:0];
391-
{m_axis_ptp_ts_borrow_next, m_axis_ptp_ts_adj_next[45:16]} = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
392-
m_axis_ptp_ts_adj_next[47:46] = 0;
393-
m_axis_ptp_ts_adj_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
394-
end
395-
396383
case (state_reg)
397384
STATE_IDLE: begin
398385
// idle state - wait for data
@@ -408,49 +395,10 @@ always @* begin
408395
s_empty_next = keep2empty(s_axis_tkeep);
409396

410397
if (s_axis_tvalid && cfg_tx_enable) begin
411-
// XGMII start and preamble
412-
if (swap_lanes_reg) begin
413-
// lanes swapped
414-
if (PTP_TS_ENABLE) begin
415-
if (PTP_TS_FMT_TOD) begin
416-
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
417-
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
418-
end else begin
419-
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
420-
end
421-
end
422-
start_packet_next = 2'b10;
423-
end else begin
424-
// lanes not swapped
425-
if (PTP_TS_ENABLE) begin
426-
if (PTP_TS_FMT_TOD) begin
427-
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
428-
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
429-
end else begin
430-
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
431-
end
432-
end
433-
start_packet_next = 2'b01;
434-
end
435-
if (PTP_TS_ENABLE) begin
436-
if (PTP_TS_CTRL_IN_TUSER) begin
437-
m_axis_ptp_ts_tag_next = s_axis_tuser >> 2;
438-
if (PTP_TS_FMT_TOD) begin
439-
m_axis_ptp_ts_valid_int_next = s_axis_tuser[1];
440-
end else begin
441-
m_axis_ptp_ts_valid_next = s_axis_tuser[1];
442-
end
443-
end else begin
444-
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
445-
if (PTP_TS_FMT_TOD) begin
446-
m_axis_ptp_ts_valid_int_next = 1'b1;
447-
end else begin
448-
m_axis_ptp_ts_valid_next = 1'b1;
449-
end
450-
end
451-
end
398+
// Preamble and SFD
452399
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
453400
output_type_next = OUTPUT_TYPE_START_0;
401+
frame_start_next = 1'b1;
454402
s_axis_tready_next = 1'b1;
455403
state_next = STATE_PAYLOAD;
456404
end else begin
@@ -641,6 +589,7 @@ always @(posedge clk) begin
641589

642590
swap_lanes_reg <= swap_lanes_next;
643591

592+
frame_start_reg <= frame_start_next;
644593
frame_reg <= frame_next;
645594
frame_error_reg <= frame_error_next;
646595
frame_min_count_reg <= frame_min_count_next;
@@ -653,14 +602,10 @@ always @(posedge clk) begin
653602

654603
s_axis_tready_reg <= s_axis_tready_next;
655604

656-
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
657-
m_axis_ptp_ts_adj_reg <= m_axis_ptp_ts_adj_next;
658-
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
659-
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
660-
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
661-
m_axis_ptp_ts_borrow_reg <= m_axis_ptp_ts_borrow_next;
605+
m_axis_ptp_ts_valid_reg <= 1'b0;
606+
m_axis_ptp_ts_valid_int_reg <= 1'b0;
662607

663-
start_packet_reg <= start_packet_next;
608+
start_packet_reg <= 2'b00;
664609
error_underflow_reg <= error_underflow_next;
665610

666611
delay_type_valid <= 1'b0;
@@ -690,6 +635,50 @@ always @(posedge clk) begin
690635
output_type_reg <= output_type_next;
691636
end
692637

638+
if (PTP_TS_ENABLE && PTP_TS_FMT_TOD) begin
639+
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_int_reg;
640+
m_axis_ptp_ts_adj_reg[15:0] <= m_axis_ptp_ts_reg[15:0];
641+
{m_axis_ptp_ts_borrow_reg, m_axis_ptp_ts_adj_reg[45:16]} <= $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
642+
m_axis_ptp_ts_adj_reg[47:46] <= 0;
643+
m_axis_ptp_ts_adj_reg[95:48] <= m_axis_ptp_ts_reg[95:48] + 1;
644+
end
645+
646+
if (frame_start_reg) begin
647+
if (swap_lanes_reg) begin
648+
if (PTP_TS_ENABLE) begin
649+
if (PTP_TS_FMT_TOD) begin
650+
m_axis_ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
651+
m_axis_ptp_ts_reg[95:48] <= ptp_ts[95:48];
652+
end else begin
653+
m_axis_ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
654+
end
655+
end
656+
start_packet_reg <= 2'b10;
657+
end else begin
658+
if (PTP_TS_ENABLE) begin
659+
m_axis_ptp_ts_reg <= ptp_ts;
660+
end
661+
start_packet_reg <= 2'b01;
662+
end
663+
if (PTP_TS_ENABLE) begin
664+
if (PTP_TS_CTRL_IN_TUSER) begin
665+
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 2;
666+
if (PTP_TS_FMT_TOD) begin
667+
m_axis_ptp_ts_valid_int_reg <= s_axis_tuser[1];
668+
end else begin
669+
m_axis_ptp_ts_valid_reg <= s_axis_tuser[1];
670+
end
671+
end else begin
672+
m_axis_ptp_ts_tag_reg <= s_axis_tuser >> 1;
673+
if (PTP_TS_FMT_TOD) begin
674+
m_axis_ptp_ts_valid_int_reg <= 1'b1;
675+
end else begin
676+
m_axis_ptp_ts_valid_reg <= 1'b1;
677+
end
678+
end
679+
end
680+
end
681+
693682
case (output_type_reg)
694683
OUTPUT_TYPE_IDLE: begin
695684
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
@@ -765,9 +754,13 @@ always @(posedge clk) begin
765754
crc_state_reg[7] <= 32'hFFFFFFFF;
766755
end
767756

757+
last_ts_reg <= ptp_ts;
758+
ts_inc_reg <= ptp_ts - last_ts_reg;
759+
768760
if (rst) begin
769761
state_reg <= STATE_IDLE;
770762

763+
frame_start_reg <= 1'b0;
771764
frame_reg <= 1'b0;
772765

773766
swap_lanes_reg <= 1'b0;

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