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alexforencichalexforencich
committed
Pack start packet strobes into the same signal
1 parent 2efcfdb commit 659aa67

22 files changed

+96
-180
lines changed

‎rtl/axis_baser_rx_64.v

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,7 @@ module axis_baser_rx_64 #
5757
/*
5858
* Status
5959
*/
60-
output wire start_packet_0,
61-
output wire start_packet_4,
60+
output wire [1:0] start_packet,
6261
output wire error_bad_frame,
6362
output wire error_bad_fcs,
6463
output wire rx_bad_block
@@ -173,8 +172,7 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
173172
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
174173
reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
175174

176-
reg start_packet_0_reg = 1'b0;
177-
reg start_packet_4_reg = 1'b0;
175+
reg [1:0] start_packet_reg = 2'b00;
178176
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
179177
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
180178
reg rx_bad_block_reg = 1'b0;
@@ -202,8 +200,7 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
202200
assign m_axis_tlast = m_axis_tlast_reg;
203201
assign m_axis_tuser = m_axis_tuser_reg;
204202

205-
assign start_packet_0 = start_packet_0_reg;
206-
assign start_packet_4 = start_packet_4_reg;
203+
assign start_packet = start_packet_reg;
207204
assign error_bad_frame = error_bad_frame_reg;
208205
assign error_bad_fcs = error_bad_fcs_reg;
209206
assign rx_bad_block = rx_bad_block_reg;
@@ -406,8 +403,7 @@ always @(posedge clk) begin
406403

407404
m_axis_tvalid_reg <= 1'b0;
408405

409-
start_packet_0_reg <= 1'b0;
410-
start_packet_4_reg <= 1'b0;
406+
start_packet_reg <= 2'b00;
411407
error_bad_frame_reg <= 1'b0;
412408
error_bad_fcs_reg <= 1'b0;
413409
rx_bad_block_reg <= 1'b0;
@@ -428,8 +424,7 @@ always @(posedge clk) begin
428424

429425
m_axis_tvalid_reg <= m_axis_tvalid_next;
430426

431-
start_packet_0_reg <= 1'b0;
432-
start_packet_4_reg <= 1'b0;
427+
start_packet_reg <= 2'b00;
433428
error_bad_frame_reg <= error_bad_frame_next;
434429
error_bad_fcs_reg <= error_bad_fcs_next;
435430
rx_bad_block_reg <= 1'b0;
@@ -438,11 +433,11 @@ always @(posedge clk) begin
438433

439434
if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
440435
lanes_swapped <= 1'b0;
441-
start_packet_0_reg <= 1'b1;
436+
start_packet_reg <= 2'b01;
442437
input_type_d0 <= INPUT_TYPE_START_0;
443438
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
444439
lanes_swapped <= 1'b1;
445-
start_packet_4_reg <= 1'b1;
440+
start_packet_reg <= 2'b10;
446441
delay_type_valid <= 1'b1;
447442
if (delay_type_valid) begin
448443
input_type_d0 <= delay_type;

‎rtl/axis_baser_tx_64.v

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,7 @@ module axis_baser_tx_64 #
6666
/*
6767
* Status
6868
*/
69-
output wire start_packet_0,
70-
output wire start_packet_4,
69+
output wire [1:0] start_packet,
7170
output wire error_underflow
7271
);
7372

@@ -210,17 +209,15 @@ reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
210209
reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next;
211210
reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
212211

213-
reg start_packet_0_reg = 1'b0, start_packet_0_next;
214-
reg start_packet_4_reg = 1'b0, start_packet_4_next;
212+
reg [1:0] start_packet_reg = 2'b00, start_packet_next;
215213
reg error_underflow_reg = 1'b0, error_underflow_next;
216214

217215
assign s_axis_tready = s_axis_tready_reg;
218216

219217
assign encoded_tx_data = encoded_tx_data_reg;
220218
assign encoded_tx_hdr = encoded_tx_hdr_reg;
221219

222-
assign start_packet_0 = start_packet_0_reg;
223-
assign start_packet_4 = start_packet_4_reg;
220+
assign start_packet = start_packet_reg;
224221
assign error_underflow = error_underflow_reg;
225222

226223
lfsr #(
@@ -475,8 +472,7 @@ always @* begin
475472
output_data_next = s_tdata_reg;
476473
output_type_next = OUTPUT_TYPE_IDLE;
477474

478-
start_packet_0_next = 1'b0;
479-
start_packet_4_next = 1'b0;
475+
start_packet_next = 2'b00;
480476
error_underflow_next = 1'b0;
481477

482478
case (state_reg)
@@ -497,11 +493,11 @@ always @* begin
497493
if (ifg_count_reg > 8'd0) begin
498494
// need to send more idles - swap lanes
499495
swap_lanes = 1'b1;
500-
start_packet_4_next = 1'b1;
496+
start_packet_next = 2'b10;
501497
end else begin
502498
// no more idles - unswap
503499
unswap_lanes = 1'b1;
504-
start_packet_0_next = 1'b1;
500+
start_packet_next = 2'b01;
505501
end
506502
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
507503
output_type_next = OUTPUT_TYPE_START_0;
@@ -731,8 +727,7 @@ always @(posedge clk) begin
731727
output_data_reg <= {DATA_WIDTH{1'b0}};
732728
output_type_reg <= OUTPUT_TYPE_IDLE;
733729

734-
start_packet_0_reg <= 1'b0;
735-
start_packet_4_reg <= 1'b0;
730+
start_packet_reg <= 2'b00;
736731
error_underflow_reg <= 1'b0;
737732

738733
crc_state <= 32'hFFFFFFFF;
@@ -751,8 +746,7 @@ always @(posedge clk) begin
751746

752747
s_axis_tready_reg <= s_axis_tready_next;
753748

754-
start_packet_0_reg <= start_packet_0_next;
755-
start_packet_4_reg <= start_packet_4_next;
749+
start_packet_reg <= start_packet_next;
756750
error_underflow_reg <= error_underflow_next;
757751

758752
delay_type_valid <= 1'b0;

‎rtl/axis_xgmii_rx_64.v

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,7 @@ module axis_xgmii_rx_64
5252
/*
5353
* Status
5454
*/
55-
output wire start_packet_0,
56-
output wire start_packet_4,
55+
output wire [1:0] start_packet,
5756
output wire error_bad_frame,
5857
output wire error_bad_fcs
5958
);
@@ -98,8 +97,7 @@ reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
9897
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
9998
reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
10099

101-
reg start_packet_0_reg = 1'b0;
102-
reg start_packet_4_reg = 1'b0;
100+
reg [1:0] start_packet_reg = 2'b00;
103101
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
104102
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
105103

@@ -126,8 +124,7 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
126124
assign m_axis_tlast = m_axis_tlast_reg;
127125
assign m_axis_tuser = m_axis_tuser_reg;
128126

129-
assign start_packet_0 = start_packet_0_reg;
130-
assign start_packet_4 = start_packet_4_reg;
127+
assign start_packet = start_packet_reg;
131128
assign error_bad_frame = error_bad_frame_reg;
132129
assign error_bad_fcs = error_bad_fcs_reg;
133130

@@ -425,8 +422,7 @@ always @(posedge clk) begin
425422

426423
m_axis_tvalid_reg <= 1'b0;
427424

428-
start_packet_0_reg <= 1'b0;
429-
start_packet_4_reg <= 1'b0;
425+
start_packet_reg <= 2'b00;
430426
error_bad_frame_reg <= 1'b0;
431427
error_bad_fcs_reg <= 1'b0;
432428

@@ -443,18 +439,17 @@ always @(posedge clk) begin
443439

444440
m_axis_tvalid_reg <= m_axis_tvalid_next;
445441

446-
start_packet_0_reg <= 1'b0;
447-
start_packet_4_reg <= 1'b0;
442+
start_packet_reg <= 2'b00;
448443
error_bad_frame_reg <= error_bad_frame_next;
449444
error_bad_fcs_reg <= error_bad_fcs_next;
450445

451446
if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
452447
lanes_swapped <= 1'b0;
453-
start_packet_0_reg <= 1'b1;
448+
start_packet_reg <= 2'b01;
454449
xgmii_rxc_d0 <= xgmii_rxc;
455450
end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
456451
lanes_swapped <= 1'b1;
457-
start_packet_4_reg <= 1'b1;
452+
start_packet_reg <= 2'b10;
458453
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
459454
end else if (lanes_swapped) begin
460455
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};

‎rtl/axis_xgmii_tx_64.v

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@ module axis_xgmii_tx_64 #
6363
/*
6464
* Status
6565
*/
66-
output wire start_packet_0,
67-
output wire start_packet_4,
66+
output wire [1:0] start_packet,
6867
output wire error_underflow
6968
);
7069

@@ -139,17 +138,15 @@ wire [31:0] crc_next7;
139138
reg [63:0] xgmii_txd_reg = {8{XGMII_IDLE}}, xgmii_txd_next;
140139
reg [7:0] xgmii_txc_reg = 8'b11111111, xgmii_txc_next;
141140

142-
reg start_packet_0_reg = 1'b0, start_packet_0_next;
143-
reg start_packet_4_reg = 1'b0, start_packet_4_next;
141+
reg start_packet_reg = 2'b00, start_packet_next;
144142
reg error_underflow_reg = 1'b0, error_underflow_next;
145143

146144
assign s_axis_tready = s_axis_tready_reg;
147145

148146
assign xgmii_txd = xgmii_txd_reg;
149147
assign xgmii_txc = xgmii_txc_reg;
150148

151-
assign start_packet_0 = start_packet_0_reg;
152-
assign start_packet_4 = start_packet_4_reg;
149+
assign start_packet = start_packet_reg;
153150
assign error_underflow = error_underflow_reg;
154151

155152
lfsr #(
@@ -405,8 +402,7 @@ always @* begin
405402
xgmii_txd_next = {8{XGMII_IDLE}};
406403
xgmii_txc_next = 8'b11111111;
407404

408-
start_packet_0_next = 1'b0;
409-
start_packet_4_next = 1'b0;
405+
start_packet_next = 2'b00;
410406
error_underflow_next = 1'b0;
411407

412408
case (state_reg)
@@ -428,11 +424,11 @@ always @* begin
428424
if (ifg_count_reg > 8'd0) begin
429425
// need to send more idles - swap lanes
430426
swap_lanes = 1'b1;
431-
start_packet_4_next = 1'b1;
427+
start_packet_next = 2'b10;
432428
end else begin
433429
// no more idles - unswap
434430
unswap_lanes = 1'b1;
435-
start_packet_0_next = 1'b1;
431+
start_packet_next = 2'b01;
436432
end
437433
xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
438434
xgmii_txc_next = 8'b00000001;
@@ -661,8 +657,7 @@ always @(posedge clk) begin
661657
xgmii_txd_reg <= {8{XGMII_IDLE}};
662658
xgmii_txc_reg <= 8'b11111111;
663659

664-
start_packet_0_reg <= 1'b0;
665-
start_packet_4_reg <= 1'b0;
660+
start_packet_reg <= 2'b00;
666661
error_underflow_reg <= 1'b0;
667662

668663
crc_state <= 32'hFFFFFFFF;
@@ -678,8 +673,7 @@ always @(posedge clk) begin
678673

679674
s_axis_tready_reg <= s_axis_tready_next;
680675

681-
start_packet_0_reg <= start_packet_0_next;
682-
start_packet_4_reg <= start_packet_4_next;
676+
start_packet_reg <= start_packet_next;
683677
error_underflow_reg <= error_underflow_next;
684678

685679
if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin

‎rtl/eth_mac_10g.v

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -74,11 +74,9 @@ module eth_mac_10g #
7474
/*
7575
* Status
7676
*/
77-
output wire tx_start_packet_0,
78-
output wire tx_start_packet_4,
77+
output wire [1:0] tx_start_packet,
7978
output wire tx_error_underflow,
80-
output wire rx_start_packet_0,
81-
output wire rx_start_packet_4,
79+
output wire [1:0] rx_start_packet,
8280
output wire rx_error_bad_frame,
8381
output wire rx_error_bad_fcs,
8482

@@ -116,8 +114,7 @@ axis_xgmii_rx_inst (
116114
.m_axis_tvalid(rx_axis_tvalid),
117115
.m_axis_tlast(rx_axis_tlast),
118116
.m_axis_tuser(rx_axis_tuser),
119-
.start_packet_0(rx_start_packet_0),
120-
.start_packet_4(rx_start_packet_4),
117+
.start_packet(rx_start_packet),
121118
.error_bad_frame(rx_error_bad_frame),
122119
.error_bad_fcs(rx_error_bad_fcs)
123120
);
@@ -139,8 +136,7 @@ axis_xgmii_tx_inst (
139136
.xgmii_txd(xgmii_txd),
140137
.xgmii_txc(xgmii_txc),
141138
.ifg_delay(ifg_delay),
142-
.start_packet_0(tx_start_packet_0),
143-
.start_packet_4(tx_start_packet_4),
139+
.start_packet(tx_start_packet),
144140
.error_underflow(tx_error_underflow)
145141
);
146142

@@ -157,12 +153,12 @@ axis_xgmii_rx_inst (
157153
.m_axis_tvalid(rx_axis_tvalid),
158154
.m_axis_tlast(rx_axis_tlast),
159155
.m_axis_tuser(rx_axis_tuser),
160-
.start_packet(rx_start_packet_0),
156+
.start_packet(rx_start_packet),
161157
.error_bad_frame(rx_error_bad_frame),
162158
.error_bad_fcs(rx_error_bad_fcs)
163159
);
164160

165-
assign tx_start_packet_4 = 1'b0;
161+
assign rx_start_packet[1] = 1'b0;
166162

167163
axis_xgmii_tx_32 #(
168164
.ENABLE_PADDING(ENABLE_PADDING),
@@ -181,10 +177,10 @@ axis_xgmii_tx_inst (
181177
.xgmii_txd(xgmii_txd),
182178
.xgmii_txc(xgmii_txc),
183179
.ifg_delay(ifg_delay),
184-
.start_packet(tx_start_packet_0)
180+
.start_packet(tx_start_packet)
185181
);
186182

187-
assign rx_start_packet_4 = 1'b0;
183+
assign tx_start_packet[1] = 1'b0;
188184

189185
end
190186

‎rtl/eth_mac_phy_10g.v

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -81,11 +81,9 @@ module eth_mac_phy_10g #
8181
/*
8282
* Status
8383
*/
84-
output wire tx_start_packet_0,
85-
output wire tx_start_packet_4,
84+
output wire [1:0] tx_start_packet,
8685
output wire tx_error_underflow,
87-
output wire rx_start_packet_0,
88-
output wire rx_start_packet_4,
86+
output wire [1:0] rx_start_packet,
8987
output wire [6:0] rx_error_count,
9088
output wire rx_error_bad_frame,
9189
output wire rx_error_bad_fcs,
@@ -123,8 +121,7 @@ eth_mac_phy_10g_rx_inst (
123121
.serdes_rx_data(serdes_rx_data),
124122
.serdes_rx_hdr(serdes_rx_hdr),
125123
.serdes_rx_bitslip(serdes_rx_bitslip),
126-
.rx_start_packet_0(rx_start_packet_0),
127-
.rx_start_packet_4(rx_start_packet_4),
124+
.rx_start_packet(rx_start_packet),
128125
.rx_error_count(rx_error_count),
129126
.rx_error_bad_frame(rx_error_bad_frame),
130127
.rx_error_bad_fcs(rx_error_bad_fcs),
@@ -157,8 +154,7 @@ eth_mac_phy_10g_tx_inst (
157154
.s_axis_tuser(tx_axis_tuser),
158155
.serdes_tx_data(serdes_tx_data),
159156
.serdes_tx_hdr(serdes_tx_hdr),
160-
.tx_start_packet_0(tx_start_packet_0),
161-
.tx_start_packet_4(tx_start_packet_4),
157+
.tx_start_packet(tx_start_packet),
162158
.tx_error_underflow(tx_error_underflow),
163159
.ifg_delay(ifg_delay),
164160
.tx_prbs31_enable(tx_prbs31_enable)

‎rtl/eth_mac_phy_10g_rx.v

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,7 @@ module eth_mac_phy_10g_rx #
6464
/*
6565
* Status
6666
*/
67-
output wire rx_start_packet_0,
68-
output wire rx_start_packet_4,
67+
output wire [1:0] rx_start_packet,
6968
output wire [6:0] rx_error_count,
7069
output wire rx_error_bad_frame,
7170
output wire rx_error_bad_fcs,
@@ -139,8 +138,7 @@ axis_baser_rx_inst (
139138
.m_axis_tvalid(m_axis_tvalid),
140139
.m_axis_tlast(m_axis_tlast),
141140
.m_axis_tuser(m_axis_tuser),
142-
.start_packet_0(rx_start_packet_0),
143-
.start_packet_4(rx_start_packet_4),
141+
.start_packet(rx_start_packet),
144142
.error_bad_frame(rx_error_bad_frame),
145143
.error_bad_fcs(rx_error_bad_fcs),
146144
.rx_bad_block(rx_bad_block)

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