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Fix corner case with back-to-back single-cycle transfers
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-12
lines changed

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+7
-12
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rtl/axis_frame_len.v

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,6 @@ module axis_frame_len #
6262

6363
reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next;
6464
reg frame_len_valid_reg = 1'b0, frame_len_valid_next;
65-
reg frame_reg = 1'b0, frame_next;
6665

6766
assign frame_len = frame_len_reg;
6867
assign frame_len_valid = frame_len_valid_reg;
@@ -72,19 +71,17 @@ integer offset, i, bit_cnt;
7271
always @* begin
7372
frame_len_next = frame_len_reg;
7473
frame_len_valid_next = 1'b0;
75-
frame_next = frame_reg;
74+
75+
if (frame_len_valid_reg) begin
76+
frame_len_next = 0;
77+
end
7678

7779
if (monitor_axis_tready && monitor_axis_tvalid) begin
7880
// valid transfer cycle
7981

8082
if (monitor_axis_tlast) begin
8183
// end of frame
8284
frame_len_valid_next = 1'b1;
83-
frame_next = 1'b0;
84-
end else if (!frame_reg) begin
85-
// first word after end of frame
86-
frame_len_next = 0;
87-
frame_next = 1'b1;
8885
end
8986

9087
// increment frame length by number of words transferred
@@ -101,14 +98,12 @@ always @* begin
10198
end
10299

103100
always @(posedge clk) begin
101+
frame_len_reg <= frame_len_next;
102+
frame_len_valid_reg <= frame_len_valid_next;
103+
104104
if (rst) begin
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frame_len_reg <= 0;
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frame_len_valid_reg <= 0;
107-
frame_reg <= 1'b0;
108-
end else begin
109-
frame_len_reg <= frame_len_next;
110-
frame_len_valid_reg <= frame_len_valid_next;
111-
frame_reg <= frame_next;
112107
end
113108
end
114109

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