diff --git a/rtl/arbiter.v b/rtl/arbiter.v
index 7629077..a94f926 100644
--- a/rtl/arbiter.v
+++ b/rtl/arbiter.v
@@ -31,7 +31,7 @@ THE SOFTWARE.
 /*
  * Arbiter module
  */
-module arbiter #
+module verilog_axis_arbiter #
 (
     parameter PORTS = 4,
     // select round robin arbitration
diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 4cf0690..920dfe0 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -151,7 +151,7 @@ wire [DEST_WIDTH-1:0] current_s_tdest  = s_axis_tdest_reg[grant_encoded*DEST_WID
 wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser_reg[grant_encoded*USER_WIDTH +: USER_WIDTH];
 
 // arbiter instance
-arbiter #(
+verilog_axis_arbiter #(
     .PORTS(S_COUNT),
     .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
     .ARB_BLOCK(1),
diff --git a/rtl/axis_ram_switch.v b/rtl/axis_ram_switch.v
index ac31dcc..cc1b257 100644
--- a/rtl/axis_ram_switch.v
+++ b/rtl/axis_ram_switch.v
@@ -284,7 +284,7 @@ generate
 
 if (S_COUNT > 1) begin
 
-    arbiter #(
+    verilog_axis_arbiter #(
         .PORTS(S_COUNT),
         .ARB_TYPE_ROUND_ROBIN(1),
         .ARB_BLOCK(0),
@@ -320,7 +320,7 @@ generate
 
 if (M_COUNT > 1) begin
 
-    arbiter #(
+    verilog_axis_arbiter #(
         .PORTS(M_COUNT),
         .ARB_TYPE_ROUND_ROBIN(1),
         .ARB_BLOCK(0),
@@ -504,7 +504,7 @@ generate
         wire grant_valid;
         wire [CL_M_COUNT-1:0] grant_encoded;
 
-        arbiter #(
+        verilog_axis_arbiter #(
             .PORTS(M_COUNT),
             .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
             .ARB_BLOCK(1),
@@ -824,7 +824,7 @@ generate
         wire grant_valid;
         wire [CL_S_COUNT-1:0] grant_encoded;
 
-        arbiter #(
+        verilog_axis_arbiter #(
             .PORTS(S_COUNT),
             .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
             .ARB_BLOCK(1),
diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v
index fae45fb..8d3c858 100644
--- a/rtl/axis_switch.v
+++ b/rtl/axis_switch.v
@@ -318,7 +318,7 @@ generate
         wire grant_valid;
         wire [CL_S_COUNT-1:0] grant_encoded;
 
-        arbiter #(
+        verilog_axis_arbiter #(
             .PORTS(S_COUNT),
             .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
             .ARB_BLOCK(1),
diff --git a/tb/test_arbiter.v b/tb/test_arbiter.v
index 06663fb..4b032fd 100644
--- a/tb/test_arbiter.v
+++ b/tb/test_arbiter.v
@@ -71,7 +71,7 @@ initial begin
     $dumpvars(0, test_arbiter);
 end
 
-arbiter #(
+verilog_axis_arbiter #(
     .PORTS(PORTS),
     .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
     .ARB_BLOCK(ARB_BLOCK),
diff --git a/tb/test_arbiter_rr.v b/tb/test_arbiter_rr.v
index 3d946e8..98ab558 100644
--- a/tb/test_arbiter_rr.v
+++ b/tb/test_arbiter_rr.v
@@ -71,7 +71,7 @@ initial begin
     $dumpvars(0, test_arbiter_rr);
 end
 
-arbiter #(
+verilog_axis_arbiter #(
     .PORTS(PORTS),
     .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
     .ARB_BLOCK(ARB_BLOCK),