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Rewrite early ready condition
Signed-off-by: Alex Forencich <[email protected]>
1 parent 268d0c6 commit f1b7079

13 files changed

+26
-26
lines changed

rtl/axis_adapter.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -484,8 +484,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
484484
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
485485
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
486486

487-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
488-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
487+
// enable ready input next cycle if temp register is empty and output register will be available
488+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
489489

490490
always @* begin
491491
// transfer sink ready state to source

rtl/axis_arb_mux.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,8 +206,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_ID_WIDTH{1'b0}};
206206
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
207207
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
208208

209-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
210-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
209+
// enable ready input next cycle if temp register is empty and output register will be available
210+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
211211

212212
always @* begin
213213
// transfer sink ready state to source

rtl/axis_broadcast.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W
121121
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
122122
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
123123

124-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
125-
wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
124+
// enable ready input next cycle if temp register is empty and output register will be available
125+
wire s_axis_tready_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid || ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid));
126126

127127
always @* begin
128128
// transfer sink ready state to source

rtl/axis_cobs_decode.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -268,8 +268,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
268268
assign m_axis_tlast = m_axis_tlast_reg;
269269
assign m_axis_tuser = m_axis_tuser_reg;
270270

271-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
272-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
271+
// enable ready input next cycle if temp register is empty and output register will be available
272+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
273273

274274
always @* begin
275275
// transfer sink ready state to source

rtl/axis_cobs_encode.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -445,8 +445,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
445445
assign m_axis_tlast = m_axis_tlast_reg;
446446
assign m_axis_tuser = m_axis_tuser_reg;
447447

448-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
449-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
448+
// enable ready input next cycle if temp register is empty and output register will be available
449+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
450450

451451
always @* begin
452452
// transfer sink ready state to source

rtl/axis_demux.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -227,8 +227,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W
227227
assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH_INT{1'b0}};
228228
assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
229229

230-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
231-
assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !m_axis_tvalid_int));
230+
// enable ready input next cycle if temp register is empty and output register will be available
231+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || (m_axis_tready & m_axis_tvalid));
232232

233233
always @* begin
234234
// transfer sink ready state to source

rtl/axis_frame_join.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -266,8 +266,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
266266
assign m_axis_tlast = m_axis_tlast_reg;
267267
assign m_axis_tuser = m_axis_tuser_reg;
268268

269-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
270-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
269+
// enable ready input next cycle if temp register is empty and output register will be available
270+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
271271

272272
always @* begin
273273
// transfer sink ready state to source

rtl/axis_frame_length_adjust.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -543,8 +543,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
543543
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
544544
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
545545

546-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
547-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
546+
// enable ready input next cycle if temp register is empty and output register will be available
547+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
548548

549549
always @* begin
550550
// transfer sink ready state to source

rtl/axis_mux.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -193,8 +193,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
193193
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
194194
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
195195

196-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
197-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
196+
// enable ready input next cycle if temp register is empty and output register will be available
197+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
198198

199199
always @* begin
200200
// transfer sink ready state to source

rtl/axis_rate_limit.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
186186
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
187187
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
188188

189-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
190-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
189+
// enable ready input next cycle if temp register is empty and output register will be available
190+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
191191

192192
always @* begin
193193
// transfer sink ready state to source

rtl/axis_register.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -125,8 +125,8 @@ if (REG_TYPE > 1) begin
125125
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
126126
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
127127

128-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
129-
wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
128+
// enable ready input next cycle if temp register is empty and output register will be available
129+
wire s_axis_tready_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
130130

131131
always @* begin
132132
// transfer sink ready state to source

rtl/axis_stat_counter.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -305,8 +305,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
305305
assign m_axis_tlast = m_axis_tlast_reg;
306306
assign m_axis_tuser = m_axis_tuser_reg;
307307

308-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
309-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
308+
// enable ready input next cycle if temp register is empty and output register will be available
309+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
310310

311311
always @* begin
312312
// transfer sink ready state to source

rtl/axis_tap.v

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,8 +258,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
258258
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
259259
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
260260

261-
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
262-
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
261+
// enable ready input next cycle if temp register is empty and output register will be available
262+
assign m_axis_tready_int_early = !temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || m_axis_tready);
263263

264264
always @* begin
265265
// transfer sink ready state to source

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