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-26
lines changed
13 files changed +26
-26
lines changed Original file line number Diff line number Diff line change @@ -484,8 +484,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -206,8 +206,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -121,8 +121,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W
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assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT* DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT* USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (! temp_m_axis_tvalid_reg && ( ! m_axis_tvalid || ! s_axis_tvalid ));
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ wire s_axis_tready_early = ! temp_m_axis_tvalid_reg && ( ! m_axis_tvalid || ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid ));
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -268,8 +268,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -445,8 +445,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -227,8 +227,8 @@ assign m_axis_tid = ID_ENABLE ? {M_COUNT{m_axis_tid_reg}} : {M_COUNT*ID_W
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assign m_axis_tdest = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT* M_DEST_WIDTH_INT{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT* USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid || ! m_axis_tvalid_int ));
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || (m_axis_tready & m_axis_tvalid ));
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -266,8 +266,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -543,8 +543,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -193,8 +193,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -186,8 +186,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -125,8 +125,8 @@ if (REG_TYPE > 1) begin
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- wire s_axis_tready_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! s_axis_tvalid) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ wire s_axis_tready_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -305,8 +305,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
Original file line number Diff line number Diff line change @@ -258,8 +258,8 @@ assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
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assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0 }};
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assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0 }};
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- // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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- assign m_axis_tready_int_early = m_axis_tready || ( ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || ! m_axis_tvalid_int) );
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+ // enable ready input next cycle if temp register is empty and output register will be available
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+ assign m_axis_tready_int_early = ! temp_m_axis_tvalid_reg && (! m_axis_tvalid_reg || m_axis_tready );
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always @* begin
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// transfer sink ready state to source
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