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alexforencichalexforencich
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Reorganize FIFO write logic
Signed-off-by: Alex Forencich <[email protected]>
1 parent c3cd676 commit 6020d09

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2 files changed

+116
-104
lines changed

2 files changed

+116
-104
lines changed

‎rtl/axis_async_fifo.v

Lines changed: 74 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -395,10 +395,80 @@ always @(posedge s_clk) begin
395395
end
396396
end
397397

398-
if (s_axis_tready && s_axis_tvalid) begin
399-
// transfer in
400-
if (!FRAME_FIFO) begin
401-
// normal FIFO mode
398+
if (FRAME_FIFO) begin
399+
// frame FIFO mode
400+
if (s_axis_tready && s_axis_tvalid) begin
401+
// transfer in
402+
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
403+
// full, packet overflow, or currently dropping frame
404+
// drop frame
405+
drop_frame_reg <= 1'b1;
406+
if (s_axis_tlast) begin
407+
// end of frame, reset write pointer
408+
wr_ptr_temp = wr_ptr_commit_reg;
409+
wr_ptr_reg <= wr_ptr_temp;
410+
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
411+
drop_frame_reg <= 1'b0;
412+
overflow_reg <= 1'b1;
413+
end
414+
end else begin
415+
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
416+
wr_ptr_temp = wr_ptr_reg + 1;
417+
wr_ptr_reg <= wr_ptr_temp;
418+
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
419+
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
420+
// end of frame or send frame
421+
send_frame_reg <= !s_axis_tlast;
422+
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
423+
// bad packet, reset write pointer
424+
wr_ptr_temp = wr_ptr_commit_reg;
425+
wr_ptr_reg <= wr_ptr_temp;
426+
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
427+
bad_frame_reg <= 1'b1;
428+
end else begin
429+
// good packet or packet overflow, update write pointer
430+
wr_ptr_temp = wr_ptr_reg + 1;
431+
wr_ptr_reg <= wr_ptr_temp;
432+
wr_ptr_commit_reg <= wr_ptr_temp;
433+
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
434+
435+
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
436+
// no sync in progress; sync update
437+
wr_ptr_update_valid_reg <= 1'b0;
438+
wr_ptr_sync_commit_reg <= wr_ptr_temp;
439+
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
440+
end else begin
441+
// sync in progress; flag it for later
442+
wr_ptr_update_valid_reg <= 1'b1;
443+
end
444+
445+
good_frame_reg <= s_axis_tlast;
446+
end
447+
end
448+
end
449+
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
450+
// data valid with packet overflow
451+
// update write pointer
452+
send_frame_reg <= 1'b1;
453+
wr_ptr_temp = wr_ptr_reg;
454+
wr_ptr_reg <= wr_ptr_temp;
455+
wr_ptr_commit_reg <= wr_ptr_temp;
456+
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
457+
458+
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
459+
// no sync in progress; sync update
460+
wr_ptr_update_valid_reg <= 1'b0;
461+
wr_ptr_sync_commit_reg <= wr_ptr_temp;
462+
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
463+
end else begin
464+
// sync in progress; flag it for later
465+
wr_ptr_update_valid_reg <= 1'b1;
466+
end
467+
end
468+
end else begin
469+
// normal FIFO mode
470+
if (s_axis_tready && s_axis_tvalid) begin
471+
// transfer in
402472
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
403473
if (drop_frame_reg && LAST_ENABLE) begin
404474
// currently dropping frame
@@ -414,70 +484,6 @@ always @(posedge s_clk) begin
414484
wr_ptr_commit_reg <= wr_ptr_temp;
415485
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
416486
end
417-
end else if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
418-
// full, packet overflow, or currently dropping frame
419-
// drop frame
420-
drop_frame_reg <= 1'b1;
421-
if (s_axis_tlast) begin
422-
// end of frame, reset write pointer
423-
wr_ptr_temp = wr_ptr_commit_reg;
424-
wr_ptr_reg <= wr_ptr_temp;
425-
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
426-
drop_frame_reg <= 1'b0;
427-
overflow_reg <= 1'b1;
428-
end
429-
end else begin
430-
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
431-
wr_ptr_temp = wr_ptr_reg + 1;
432-
wr_ptr_reg <= wr_ptr_temp;
433-
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
434-
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
435-
// end of frame or send frame
436-
send_frame_reg <= !s_axis_tlast;
437-
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
438-
// bad packet, reset write pointer
439-
wr_ptr_temp = wr_ptr_commit_reg;
440-
wr_ptr_reg <= wr_ptr_temp;
441-
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
442-
bad_frame_reg <= 1'b1;
443-
end else begin
444-
// good packet or packet overflow, update write pointer
445-
wr_ptr_temp = wr_ptr_reg + 1;
446-
wr_ptr_reg <= wr_ptr_temp;
447-
wr_ptr_commit_reg <= wr_ptr_temp;
448-
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
449-
450-
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
451-
// no sync in progress; sync update
452-
wr_ptr_update_valid_reg <= 1'b0;
453-
wr_ptr_sync_commit_reg <= wr_ptr_temp;
454-
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
455-
end else begin
456-
// sync in progress; flag it for later
457-
wr_ptr_update_valid_reg <= 1'b1;
458-
end
459-
460-
good_frame_reg <= s_axis_tlast;
461-
end
462-
end
463-
end
464-
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
465-
// data valid with packet overflow
466-
// update write pointer
467-
send_frame_reg <= 1'b1;
468-
wr_ptr_temp = wr_ptr_reg;
469-
wr_ptr_reg <= wr_ptr_temp;
470-
wr_ptr_commit_reg <= wr_ptr_temp;
471-
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
472-
473-
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
474-
// no sync in progress; sync update
475-
wr_ptr_update_valid_reg <= 1'b0;
476-
wr_ptr_sync_commit_reg <= wr_ptr_temp;
477-
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
478-
end else begin
479-
// sync in progress; flag it for later
480-
wr_ptr_update_valid_reg <= 1'b1;
481487
end
482488
end
483489

‎rtl/axis_fifo.v

Lines changed: 42 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -245,46 +245,52 @@ always @(posedge clk) begin
245245
bad_frame_reg <= 1'b0;
246246
good_frame_reg <= 1'b0;
247247

248-
if (s_axis_tready && s_axis_tvalid) begin
249-
// transfer in
250-
if (!FRAME_FIFO) begin
251-
// normal FIFO mode
252-
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
253-
wr_ptr_reg <= wr_ptr_reg + 1;
254-
wr_ptr_commit_reg <= wr_ptr_reg + 1;
255-
end else if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
256-
// full, packet overflow, or currently dropping frame
257-
// drop frame
258-
drop_frame_reg <= 1'b1;
259-
if (s_axis_tlast) begin
260-
// end of frame, reset write pointer
261-
wr_ptr_reg <= wr_ptr_commit_reg;
262-
drop_frame_reg <= 1'b0;
263-
overflow_reg <= 1'b1;
264-
end
265-
end else begin
266-
// store it
267-
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
268-
wr_ptr_reg <= wr_ptr_reg + 1;
269-
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
270-
// end of frame or send frame
271-
send_frame_reg <= !s_axis_tlast;
272-
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
273-
// bad packet, reset write pointer
248+
if (FRAME_FIFO) begin
249+
// frame FIFO mode
250+
if (s_axis_tready && s_axis_tvalid) begin
251+
// transfer in
252+
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
253+
// full, packet overflow, or currently dropping frame
254+
// drop frame
255+
drop_frame_reg <= 1'b1;
256+
if (s_axis_tlast) begin
257+
// end of frame, reset write pointer
274258
wr_ptr_reg <= wr_ptr_commit_reg;
275-
bad_frame_reg <= 1'b1;
276-
end else begin
277-
// good packet or packet overflow, update write pointer
278-
wr_ptr_commit_reg <= wr_ptr_reg + 1;
279-
good_frame_reg <= s_axis_tlast;
259+
drop_frame_reg <= 1'b0;
260+
overflow_reg <= 1'b1;
261+
end
262+
end else begin
263+
// store it
264+
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
265+
wr_ptr_reg <= wr_ptr_reg + 1;
266+
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
267+
// end of frame or send frame
268+
send_frame_reg <= !s_axis_tlast;
269+
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
270+
// bad packet, reset write pointer
271+
wr_ptr_reg <= wr_ptr_commit_reg;
272+
bad_frame_reg <= 1'b1;
273+
end else begin
274+
// good packet or packet overflow, update write pointer
275+
wr_ptr_commit_reg <= wr_ptr_reg + 1;
276+
good_frame_reg <= s_axis_tlast;
277+
end
280278
end
281279
end
280+
end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
281+
// data valid with packet overflow
282+
// update write pointer
283+
send_frame_reg <= 1'b1;
284+
wr_ptr_commit_reg <= wr_ptr_reg;
285+
end
286+
end else begin
287+
// normal FIFO mode
288+
if (s_axis_tready && s_axis_tvalid) begin
289+
// transfer in
290+
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
291+
wr_ptr_reg <= wr_ptr_reg + 1;
292+
wr_ptr_commit_reg <= wr_ptr_reg + 1;
282293
end
283-
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
284-
// data valid with packet overflow
285-
// update write pointer
286-
send_frame_reg <= 1'b1;
287-
wr_ptr_commit_reg <= wr_ptr_reg;
288294
end
289295

290296
if (rst) begin

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