diff --git a/rtl/axi_ram.v b/rtl/axi_ram.v
index 7eea203..8740c24 100644
--- a/rtl/axi_ram.v
+++ b/rtl/axi_ram.v
@@ -42,7 +42,9 @@ module axi_ram #
     // Width of ID signal
     parameter ID_WIDTH = 8,
     // Extra pipeline register on output
-    parameter PIPELINE_OUTPUT = 0
+    parameter PIPELINE_OUTPUT = 0,
+    // Initialization file
+    parameter MEM_INIT = ""
 )
 (
     input  wire                   clk,
@@ -166,15 +168,20 @@ assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg
 integer i, j;
 
 initial begin
-    // two nested loops for smaller number of iterations per loop
-    // workaround for synthesizer complaints about large loop counts
-    for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 2**(VALID_ADDR_WIDTH/2)) begin
-        for (j = i; j < i + 2**(VALID_ADDR_WIDTH/2); j = j + 1) begin
-            mem[j] = 0;
+    if (MEM_INIT == "") begin
+        // two nested loops for smaller number of iterations per loop
+        // workaround for synthesizer complaints about large loop counts
+        for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 2**(VALID_ADDR_WIDTH/2)) begin
+            for (j = i; j < i + 2**(VALID_ADDR_WIDTH/2); j = j + 1) begin
+                mem[j] = 0;
+            end
         end
+    end else begin
+	    $readmemh(MEM_INIT, mem);
     end
 end
 
+
 always @* begin
     write_state_next = WRITE_STATE_IDLE;