axil_ram handshake between AW/AR-READY and B/R-RESP

[jimmysitu]

Hi, @alexforencich

I am doing a formal verificaion for verilog-axi IPs, see my repo verilog-axi-formal. And I found an AXI4 lite handshake issue with axil_ram interface, the aw/w-ready is assert with bvalid at the same clock, see the code below

verilog-axi/rtl/axil_ram.v

Lines 118 to 124 in 314ea7d

	if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready)) begin
	s_axil_awready_next = 1'b1;
	s_axil_wready_next = 1'b1;
	s_axil_bvalid_next = 1'b1;
	mem_wr_en = 1'b1;
	end

And the AXI standard says,

the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID
An explain from https://community.arm.com/ is here
Which means bvalid should at least one clock after wready.

[alexforencich]

I guess you didn't see #11. This is a known issue that's on my to-do list to fix; I haven't decided the best way to go about doing that yet.

[jimmysitu]

Hi, @alexforencich , is there any update about this bug?

[Bald-Badger]

The fix mentioned in #11 is legit. at least it passed my Cyclone V HPS AXI R/W test (and it didn't pass before the fix)