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AlexLao512AlexLao512
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Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select
1 parent 00c200f commit f7eeb4e

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2 files changed

+13
-13
lines changed

2 files changed

+13
-13
lines changed

‎rtl/axi_axil_adapter_rd.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -286,7 +286,7 @@ always @* begin
286286

287287
if (m_axil_rready && m_axil_rvalid) begin
288288
s_axi_rid_next = id_reg;
289-
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
289+
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
290290
s_axi_rresp_next = m_axil_rresp;
291291
s_axi_rlast_next = 1'b0;
292292
s_axi_rvalid_next = 1'b1;
@@ -316,7 +316,7 @@ always @* begin
316316
s_axi_rid_next = id_reg;
317317
data_next = m_axil_rdata;
318318
resp_next = m_axil_rresp;
319-
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
319+
s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
320320
s_axi_rresp_next = m_axil_rresp;
321321
s_axi_rlast_next = 1'b0;
322322
s_axi_rvalid_next = 1'b1;
@@ -346,7 +346,7 @@ always @* begin
346346

347347
if (s_axi_rready || !s_axi_rvalid) begin
348348
s_axi_rid_next = id_reg;
349-
s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
349+
s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
350350
s_axi_rresp_next = resp_reg;
351351
s_axi_rlast_next = 1'b0;
352352
s_axi_rvalid_next = 1'b1;
@@ -412,7 +412,7 @@ always @* begin
412412
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
413413

414414
if (m_axil_rready && m_axil_rvalid) begin
415-
data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
415+
data_next[addr_reg[AXI_ADDR_BIT_OFFSET:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
416416
if (m_axil_rresp) begin
417417
resp_next = m_axil_rresp;
418418
end

‎rtl/axi_axil_adapter_wr.v

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@ always @* begin
335335

336336
if (s_axi_wready && s_axi_wvalid) begin
337337
m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}};
338-
m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH);
338+
m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH);
339339
m_axil_wvalid_next = 1'b1;
340340
burst_next = burst_reg - 1;
341341
burst_active_next = burst_reg != 0;
@@ -354,13 +354,13 @@ always @* begin
354354
if (CONVERT_NARROW_BURST) begin
355355
for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin
356356
if (s_axi_wstrb[i]) begin
357-
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
358-
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
357+
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE];
358+
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1;
359359
end
360360
end
361361
end else begin
362-
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
363-
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
362+
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata;
363+
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb;
364364
end
365365
m_axil_wdata_next = data_next;
366366
m_axil_wstrb_next = strb_next;
@@ -451,8 +451,8 @@ always @* begin
451451
if (s_axi_wready && s_axi_wvalid) begin
452452
data_next = s_axi_wdata;
453453
strb_next = s_axi_wstrb;
454-
m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
455-
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
454+
m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
455+
m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
456456
m_axil_wvalid_next = 1'b1;
457457
burst_next = burst_reg - 1;
458458
burst_active_next = burst_reg != 0;
@@ -469,8 +469,8 @@ always @* begin
469469
s_axi_wready_next = 1'b0;
470470

471471
if (!m_axil_wvalid || m_axil_wready) begin
472-
m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
473-
m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
472+
m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH);
473+
m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH);
474474
m_axil_wvalid_next = 1'b1;
475475
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg);
476476
last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg];

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