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Description
Version
Yosys 0.51 (git sha1 c4b5190, g++ 14.2.1 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
module bug (
clk_a,
clk_b,
);
input wire clk_a;
input wire clk_b;
integer i;
always @(posedge clk_a) begin
i = 1;
end
always @(posedge clk_b) begin
i = 2;
end
endmodule
read_verilog bug.v; proc; check
This is notable as it seems to be a realistic pattern to iterate over integer i
from 0 to whatever in two distinct processes, like in techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v
. I intuitively expect it to be valid Verilog and can't figure out anything clearly to the contrary, even if the standard ominously says "If loops in two or more parallel processes use the same loop control variable, there is a potential of one loop modifying the variable while other loops are still using it."
Expected Behavior
No warnings
Actual Behavior
Warning: multiple conflicting drivers for bad.\i [31]:
port Q[31] of cell $procdff$4 ($dff)
port Q[31] of cell $procdff$3 ($dff)
Warning: multiple conflicting drivers for bad.\i [30]:
etc
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pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproduction