liberty multiple output

[jalcim]

Hi,

Long time i have this problem,
How to techmap a full_adder (by exemple).

In all my test, yosys accept multiple output from sequential logic, like DFF,
But dosn't not accept from combinatorial, like full_adder.

This is true or i do miss understanding ?
Why this limitation ?

The only way i found is to provide verilog netlist gate level description (its a exemple who concern more complexe macro).

read_verilog src/adder.v

synth

#extract_fa -fa -v #do the same thing than with the techmap
techmap -map lib/fa.v
abc -liberty lib/cmos_cells.lib

opt_clean

write_verilog out/synth.v
write_spice out/synth.sp

show

[Ravenslofty]

ABC does not support mapping to multiple-output gates, because of how the algorithm works.

You can use a techmap rule like that, but I would generally advise against it. Yosys must split the logic around the full adder, turning it into a logic path for the input and a logic path for the output, which can mislead ABC about the critical path of the design.