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tests: More autoname tests
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‎tests/various/autoname.ys‎

Lines changed: 170 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,187 @@
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# prefer output name
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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debug autoname
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logger -check-expected
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# fallback to shortest name if output is private
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design -reset
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read_rtlil <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire input 1 \ab
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wire input 2 \abcd
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cell $or $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \ab
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connect \B \abcd
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connect \Y $y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to ab_.or_A" 1
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debug autoname
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logger -check-expected
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# prefer low fanout over low name length
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire input 4 \c_has_a_long_name
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $y
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \c_has_a_long_name
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connect \Y $y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to bcd_.and_B" 1
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logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
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debug autoname
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logger -check-expected
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# names are unique
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
7-
cell $and \b_$and_B
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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cell $and $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1
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debug autoname
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logger -check-expected
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# wires get autonames too
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire $c
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wire $d
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wire $e
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cell $__unknown $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $c
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end
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cell $or \or
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $d
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $d
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connect \Y $e
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end
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cell $and $name3
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $e
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connect \Y $y
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end
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end
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EOT
19-
autoname
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# wires all named for being cell outputs
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logger -expect log "Rename wire .d in top to or_Y" 1
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# $name gets shortest name (otherwise bcd_$__unknown_B)
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logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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# another output wire
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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# $c gets shortest name, since the cell driving it doesn't have known port
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# directions
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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debug autoname t:$and
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logger -check-expected

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