CMake: Change Private Libs to Public

nickrallison · nickrallison · commit e88a1fc31f31 · 2025-07-03T16:51:30.000-06:00
diff --git a/backends/aiger/CMakeLists.txt b/backends/aiger/CMakeLists.txt
@@ -5,4 +5,4 @@ target_sources(yosys_backends_aiger INTERFACE
     xaiger.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_aiger)
+target_link_libraries(yosys PUBLIC yosys_backends_aiger)
diff --git a/backends/aiger2/CMakeLists.txt b/backends/aiger2/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_aiger2 INTERFACE
     aiger.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_aiger2)
+target_link_libraries(yosys PUBLIC yosys_backends_aiger2)
diff --git a/backends/blif/CMakeLists.txt b/backends/blif/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_blif INTERFACE
     blif.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_blif)
+target_link_libraries(yosys PUBLIC yosys_backends_blif)
diff --git a/backends/btor/CMakeLists.txt b/backends/btor/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_btor INTERFACE
     btor.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_btor)
+target_link_libraries(yosys PUBLIC yosys_backends_btor)
diff --git a/backends/cxxrtl/CMakeLists.txt b/backends/cxxrtl/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_backends_cxxrtl INTERFACE
     cxxrtl_backend.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_cxxrtl)
+target_link_libraries(yosys PUBLIC yosys_backends_cxxrtl)
 
 add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl.h")
 add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl_vcd.h")
diff --git a/backends/edif/CMakeLists.txt b/backends/edif/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_edif INTERFACE
     edif.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_edif)
+target_link_libraries(yosys PUBLIC yosys_backends_edif)
diff --git a/backends/firrtl/CMakeLists.txt b/backends/firrtl/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_firrtl INTERFACE
     firrtl.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_firrtl)
+target_link_libraries(yosys PUBLIC yosys_backends_firrtl)
diff --git a/backends/functional/CMakeLists.txt b/backends/functional/CMakeLists.txt
@@ -7,4 +7,4 @@ target_sources(yosys_backends_functional INTERFACE
     test_generic.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_functional)
+target_link_libraries(yosys PUBLIC yosys_backends_functional)
diff --git a/backends/intersynth/CMakeLists.txt b/backends/intersynth/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_intersynth INTERFACE
     intersynth.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_intersynth)
+target_link_libraries(yosys PUBLIC yosys_backends_intersynth)
diff --git a/backends/jny/CMakeLists.txt b/backends/jny/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_jny INTERFACE
     jny.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_jny)
+target_link_libraries(yosys PUBLIC yosys_backends_jny)
diff --git a/backends/json/CMakeLists.txt b/backends/json/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_json INTERFACE
     json.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_json)
+target_link_libraries(yosys PUBLIC yosys_backends_json)
diff --git a/backends/rtlil/CMakeLists.txt b/backends/rtlil/CMakeLists.txt
@@ -5,4 +5,4 @@ target_sources(yosys_backends_rtlil INTERFACE
     rtlil_backend.h
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_rtlil)
+target_link_libraries(yosys PUBLIC yosys_backends_rtlil)
diff --git a/backends/simplec/CMakeLists.txt b/backends/simplec/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_simplec INTERFACE
     simplec.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_simplec)
+target_link_libraries(yosys PUBLIC yosys_backends_simplec)
diff --git a/backends/smt2/CMakeLists.txt b/backends/smt2/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_backends_smt2 INTERFACE
     smt2.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_smt2)
+target_link_libraries(yosys PUBLIC yosys_backends_smt2)
 
 add_share_file("share/python3" "smtio.py")
 add_share_file("share/python3" "ywio.py")
diff --git a/backends/smv/CMakeLists.txt b/backends/smv/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_smv INTERFACE
     smv.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_smv)
+target_link_libraries(yosys PUBLIC yosys_backends_smv)
diff --git a/backends/spice/CMakeLists.txt b/backends/spice/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_spice INTERFACE
     spice.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_spice)
+target_link_libraries(yosys PUBLIC yosys_backends_spice)
diff --git a/backends/table/CMakeLists.txt b/backends/table/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_table INTERFACE
     table.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_table)
+target_link_libraries(yosys PUBLIC yosys_backends_table)
diff --git a/backends/verilog/CMakeLists.txt b/backends/verilog/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_backends_verilog INTERFACE
     verilog_backend.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_backends_verilog)
+target_link_libraries(yosys PUBLIC yosys_backends_verilog)
diff --git a/frontends/aiger/CMakeLists.txt b/frontends/aiger/CMakeLists.txt
@@ -5,4 +5,4 @@ target_sources(yosys_frontends_aiger INTERFACE
     aigerparse.h
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_aiger)
+target_link_libraries(yosys PUBLIC yosys_frontends_aiger)
diff --git a/frontends/aiger2/CMakeLists.txt b/frontends/aiger2/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_frontends_aiger2 INTERFACE
     xaiger.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_aiger2)
+target_link_libraries(yosys PUBLIC yosys_frontends_aiger2)
diff --git a/frontends/ast/CMakeLists.txt b/frontends/ast/CMakeLists.txt
@@ -10,4 +10,4 @@ target_sources(yosys_frontends_ast INTERFACE
     simplify.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_ast)
+target_link_libraries(yosys PUBLIC yosys_frontends_ast)
diff --git a/frontends/blif/CMakeLists.txt b/frontends/blif/CMakeLists.txt
@@ -5,4 +5,4 @@ target_sources(yosys_frontends_blif INTERFACE
     blifparse.h
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_blif)
+target_link_libraries(yosys PUBLIC yosys_frontends_blif)
diff --git a/frontends/json/CMakeLists.txt b/frontends/json/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_frontends_json INTERFACE
     jsonparse.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_json)
+target_link_libraries(yosys PUBLIC yosys_frontends_json)
diff --git a/frontends/liberty/CMakeLists.txt b/frontends/liberty/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_frontends_liberty INTERFACE
     liberty.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_liberty)
+target_link_libraries(yosys PUBLIC yosys_frontends_liberty)
diff --git a/frontends/rpc/CMakeLists.txt b/frontends/rpc/CMakeLists.txt
@@ -5,5 +5,5 @@ if (NOT DISABLE_SPAWN)
         rpc_frontend.cc
     )
 
-    target_link_libraries(yosys PRIVATE yosys_frontends_rpc)
+    target_link_libraries(yosys PUBLIC yosys_frontends_rpc)
 endif()
diff --git a/frontends/rtlil/CMakeLists.txt b/frontends/rtlil/CMakeLists.txt
@@ -13,4 +13,4 @@ add_library(yosys_frontends_rtlil_gen OBJECT
     ${FLEX_RTLIL_LEXER_OUTPUTS}
     ${BISON_RTLIL_PARSER_OUTPUTS}
 )
-target_link_libraries(yosys PRIVATE yosys_frontends_rtlil yosys_frontends_rtlil_gen)
+target_link_libraries(yosys PUBLIC yosys_frontends_rtlil yosys_frontends_rtlil_gen)
diff --git a/frontends/verific/CMakeLists.txt b/frontends/verific/CMakeLists.txt
@@ -5,4 +5,4 @@ target_sources(yosys_frontends_verific INTERFACE
     #verificsva.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_frontends_verific)
+target_link_libraries(yosys PUBLIC yosys_frontends_verific)
diff --git a/frontends/verilog/CMakeLists.txt b/frontends/verilog/CMakeLists.txt
@@ -43,4 +43,4 @@ add_library(yosys_frontends_verilog_gen OBJECT
     #${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.cc
     #${CMAKE_CURRENT_BINARY_DIR}/verilog_parser.tab.hh
 )
-target_link_libraries(yosys PRIVATE yosys_frontends_verilog yosys_frontends_verilog_gen)
+target_link_libraries(yosys PUBLIC yosys_frontends_verilog yosys_frontends_verilog_gen)
diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt
@@ -90,4 +90,4 @@ target_sources(yosys_kernel INTERFACE
 )
 endif()
 
-target_link_libraries(yosys PRIVATE yosys_kernel)
+target_link_libraries(yosys PUBLIC yosys_kernel)
diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt
@@ -67,4 +67,4 @@ target_sources(yosys_libs INTERFACE
 )
 endif()
 
-target_link_libraries(yosys PRIVATE yosys_libs)
+target_link_libraries(yosys PUBLIC yosys_libs)
diff --git a/passes/cmds/CMakeLists.txt b/passes/cmds/CMakeLists.txt
@@ -60,4 +60,4 @@ target_sources(yosys_passes_cmds INTERFACE
 )
 endif()
 
-target_link_libraries(yosys PRIVATE yosys_passes_cmds)
+target_link_libraries(yosys PUBLIC yosys_passes_cmds)
diff --git a/passes/equiv/CMakeLists.txt b/passes/equiv/CMakeLists.txt
@@ -14,4 +14,4 @@ target_sources(yosys_passes_equiv INTERFACE
     equiv_opt.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_equiv)
+target_link_libraries(yosys PUBLIC yosys_passes_equiv)
diff --git a/passes/fsm/CMakeLists.txt b/passes/fsm/CMakeLists.txt
@@ -13,4 +13,4 @@ target_sources(yosys_passes_fsm INTERFACE
     fsmdata.h
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_fsm)
+target_link_libraries(yosys PUBLIC yosys_passes_fsm)
diff --git a/passes/hierarchy/CMakeLists.txt b/passes/hierarchy/CMakeLists.txt
@@ -7,4 +7,4 @@ target_sources(yosys_passes_hierarchy INTERFACE
     keep_hierarchy.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_hierarchy)
+target_link_libraries(yosys PUBLIC yosys_passes_hierarchy)
diff --git a/passes/memory/CMakeLists.txt b/passes/memory/CMakeLists.txt
@@ -17,4 +17,4 @@ target_sources(yosys_passes_memory INTERFACE
     memlib.h
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_memory)
+target_link_libraries(yosys PUBLIC yosys_passes_memory)
diff --git a/passes/opt/CMakeLists.txt b/passes/opt/CMakeLists.txt
@@ -24,4 +24,4 @@ target_sources(yosys_passes_opt INTERFACE
     muxpack.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_opt)
+target_link_libraries(yosys PUBLIC yosys_passes_opt)
diff --git a/passes/pmgen/CMakeLists.txt b/passes/pmgen/CMakeLists.txt
@@ -50,22 +50,22 @@ target_sources(yosys_passes_pmgen INTERFACE
     ${yosys_SOURCE_DIR}/techlibs/xilinx/xilinx_srl.cc
 )
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/passes/pmgen/test_pmgen_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/passes/pmgen/test_pmgen_pm.h)
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/ice40/ice40_dsp_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/ice40/ice40_wrapcarry_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/ice40/ice40_dsp_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/ice40/ice40_wrapcarry_pm.h)
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp48a_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_CREG_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_cascade_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp48a_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_CREG_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_cascade_pm.h)
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_CREG_pm.h)
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_cascade_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_CREG_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_cascade_pm.h)
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h)
 
-target_sources(yosys_passes_pmgen PRIVATE ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_srl_pm.h)
+target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_srl_pm.h)
 
-target_link_libraries(yosys PRIVATE yosys_passes_pmgen)
+target_link_libraries(yosys PUBLIC yosys_passes_pmgen)
diff --git a/passes/proc/CMakeLists.txt b/passes/proc/CMakeLists.txt
@@ -14,4 +14,4 @@ target_sources(yosys_passes_proc INTERFACE
     proc_memwr.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_proc)
+target_link_libraries(yosys PUBLIC yosys_passes_proc)
diff --git a/passes/sat/CMakeLists.txt b/passes/sat/CMakeLists.txt
@@ -32,4 +32,4 @@ target_sources(yosys_passes_sat INTERFACE
 )
 endif()
 
-target_link_libraries(yosys PRIVATE yosys_passes_sat)
+target_link_libraries(yosys PUBLIC yosys_passes_sat)
diff --git a/passes/techmap/CMakeLists.txt b/passes/techmap/CMakeLists.txt
@@ -53,7 +53,7 @@ if (ENABLE_ABC)
     )
 endif()
 
-target_link_libraries(yosys PRIVATE yosys_passes_techmap)
+target_link_libraries(yosys PUBLIC yosys_passes_techmap)
 
 if (NOT DISABLE_SPAWN)
     set(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR})
diff --git a/passes/tests/CMakeLists.txt b/passes/tests/CMakeLists.txt
@@ -6,4 +6,4 @@ target_sources(yosys_passes_tests INTERFACE
     test_abcloop.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_passes_tests)
+target_link_libraries(yosys PUBLIC yosys_passes_tests)
diff --git a/techlibs/achronix/CMakeLists.txt b/techlibs/achronix/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_techlibs_achronix INTERFACE
     synth_achronix.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_achronix)
+target_link_libraries(yosys PUBLIC yosys_techlibs_achronix)
 
 add_share_file("share/achronix/speedster22i" "speedster22i/cells_sim.v")
 add_share_file("share/achronix/speedster22i" "speedster22i/cells_map.v")
diff --git a/techlibs/anlogic/CMakeLists.txt b/techlibs/anlogic/CMakeLists.txt
@@ -6,7 +6,7 @@ target_sources(yosys_techlibs_anlogic INTERFACE
     anlogic_fixcarry.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_anlogic)
+target_link_libraries(yosys PUBLIC yosys_techlibs_anlogic)
 
 add_share_file("share/anlogic" "cells_map.v")
 add_share_file("share/anlogic" "arith_map.v")
diff --git a/techlibs/common/CMakeLists.txt b/techlibs/common/CMakeLists.txt
@@ -27,7 +27,7 @@ target_sources(yosys_techlib_common INTERFACE
 
 add_dependencies(yosys_techlib_common yosys_techlib_common_gen)
 
-target_link_libraries(yosys PRIVATE yosys_techlib_common)
+target_link_libraries(yosys PUBLIC yosys_techlib_common)
 
 add_share_file("share" "simlib.v")
 add_share_file("share" "simcells.v")
diff --git a/techlibs/coolrunner2/CMakeLists.txt b/techlibs/coolrunner2/CMakeLists.txt
@@ -6,7 +6,7 @@ target_sources(yosys_techlibs_coolrunner2 INTERFACE
     coolrunner2_fixup.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_coolrunner2)
+target_link_libraries(yosys PUBLIC yosys_techlibs_coolrunner2)
 
 add_share_file("share/coolrunner2" "cells_latch.v")
 add_share_file("share/coolrunner2" "cells_sim.v")
diff --git a/techlibs/easic/CMakeLists.txt b/techlibs/easic/CMakeLists.txt
@@ -4,4 +4,4 @@ target_sources(yosys_techlibs_easic INTERFACE
     synth_easic.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_easic)
+target_link_libraries(yosys PUBLIC yosys_techlibs_easic)
diff --git a/techlibs/ecp5/CMakeLists.txt b/techlibs/ecp5/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_techlibs_ecp5 INTERFACE
     synth_ecp5.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_ecp5)
+target_link_libraries(yosys PUBLIC yosys_techlibs_ecp5)
 
 add_share_file("share/ecp5" "cells_ff.vh")
 add_share_file("share/ecp5" "cells_io.vh")
diff --git a/techlibs/efinix/CMakeLists.txt b/techlibs/efinix/CMakeLists.txt
@@ -5,7 +5,7 @@ target_sources(yosys_techlibs_efinix INTERFACE
     efinix_fixcarry.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_efinix)
+target_link_libraries(yosys PUBLIC yosys_techlibs_efinix)
 
 add_share_file("share/efinix" "cells_map.v")
 add_share_file("share/efinix" "arith_map.v")
diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_techlibs_fabulous INTERFACE
     synth_fabulous.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_fabulous)
+target_link_libraries(yosys PUBLIC yosys_techlibs_fabulous)
 
 add_share_file("share/fabulous" "cells_map.v")
 add_share_file("share/fabulous" "prims.v")
diff --git a/techlibs/gatemate/CMakeLists.txt b/techlibs/gatemate/CMakeLists.txt
@@ -18,7 +18,7 @@ target_sources(yosys_techlibs_gatemate PRIVATE
     ${CMAKE_CURRENT_BINARY_DIR}/lut_tree_map.v
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_gatemate)
+target_link_libraries(yosys PUBLIC yosys_techlibs_gatemate)
 
 add_share_file("share/gatemate" "reg_map.v")
 add_share_file("share/gatemate" "mux_map.v")
diff --git a/techlibs/gowin/CMakeLists.txt b/techlibs/gowin/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_techlibs_gowin INTERFACE
     synth_gowin.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_gowin)
+target_link_libraries(yosys PUBLIC yosys_techlibs_gowin)
 
 add_share_file("share/gowin" "cells_map.v")
 add_share_file("share/gowin" "cells_sim.v")
diff --git a/techlibs/greenpak4/CMakeLists.txt b/techlibs/greenpak4/CMakeLists.txt
@@ -5,7 +5,7 @@ target_sources(yosys_techlibs_greenpak4 INTERFACE
     greenpak4_dffinv.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_greenpak4)
+target_link_libraries(yosys PUBLIC yosys_techlibs_greenpak4)
 
 add_share_file("share/greenpak4" "cells_blackbox.v")
 add_share_file("share/greenpak4" "cells_latch.v")
diff --git a/techlibs/ice40/CMakeLists.txt b/techlibs/ice40/CMakeLists.txt
@@ -6,7 +6,7 @@ target_sources(yosys_techlibs_ice40 INTERFACE
     ice40_opt.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_ice40)
+target_link_libraries(yosys PUBLIC yosys_techlibs_ice40)
 
 add_share_file("share/ice40" "arith_map.v")
 add_share_file("share/ice40" "cells_map.v")
diff --git a/techlibs/intel/CMakeLists.txt b/techlibs/intel/CMakeLists.txt
@@ -4,7 +4,7 @@ target_sources(yosys_techlibs_intel INTERFACE
     synth_intel.cc
 )
 
-target_link_libraries(yosys PRIVATE yosys_techlibs_intel)
+target_link_libraries(yosys PUBLIC yosys_techlibs_intel)
 
 add_share_file("share/intel/common" "common/m9k_bb.v")
 add_share_file("share/intel/common" "common/altpll_bb.v")
diff --git a/techlibs/intel_alm/CMakeLists.txt b/techlibs/intel_alm/CMakeLists.txt
diff --git a/techlibs/lattice/CMakeLists.txt b/techlibs/lattice/CMakeLists.txt
diff --git a/techlibs/microchip/CMakeLists.txt b/techlibs/microchip/CMakeLists.txt
diff --git a/techlibs/nanoxplore/CMakeLists.txt b/techlibs/nanoxplore/CMakeLists.txt
diff --git a/techlibs/nexus/CMakeLists.txt b/techlibs/nexus/CMakeLists.txt
diff --git a/techlibs/quicklogic/CMakeLists.txt b/techlibs/quicklogic/CMakeLists.txt
diff --git a/techlibs/sf2/CMakeLists.txt b/techlibs/sf2/CMakeLists.txt
diff --git a/techlibs/xilinx/CMakeLists.txt b/techlibs/xilinx/CMakeLists.txt

Original file line number	Diff line number	Diff line change
`@@ -5,4 +5,4 @@ target_sources(yosys_backends_aiger INTERFACE`
`5`	`5`	`xaiger.cc`
`6`	`6`	`)`
`7`	`7`
`8`		`-target_link_libraries(yosys PRIVATE yosys_backends_aiger)`
	`8`	`+target_link_libraries(yosys PUBLIC yosys_backends_aiger)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_aiger2 INTERFACE`
`4`	`4`	`aiger.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_aiger2)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_aiger2)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_blif INTERFACE`
`4`	`4`	`blif.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_blif)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_blif)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_btor INTERFACE`
`4`	`4`	`btor.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_btor)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_btor)`
Original file line number	Diff line number	Diff line change
`@@ -4,7 +4,7 @@ target_sources(yosys_backends_cxxrtl INTERFACE`
`4`	`4`	`cxxrtl_backend.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_cxxrtl)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_cxxrtl)`
`8`	`8`
`9`	`9`	`add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl.h")`
`10`	`10`	`add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl_vcd.h")`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_edif INTERFACE`
`4`	`4`	`edif.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_edif)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_edif)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_firrtl INTERFACE`
`4`	`4`	`firrtl.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_firrtl)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_firrtl)`
Original file line number	Diff line number	Diff line change
`@@ -7,4 +7,4 @@ target_sources(yosys_backends_functional INTERFACE`
`7`	`7`	`test_generic.cc`
`8`	`8`	`)`
`9`	`9`
`10`		`-target_link_libraries(yosys PRIVATE yosys_backends_functional)`
	`10`	`+target_link_libraries(yosys PUBLIC yosys_backends_functional)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_intersynth INTERFACE`
`4`	`4`	`intersynth.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_intersynth)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_intersynth)`
Original file line number	Diff line number	Diff line change
`@@ -4,4 +4,4 @@ target_sources(yosys_backends_jny INTERFACE`
`4`	`4`	`jny.cc`
`5`	`5`	`)`
`6`	`6`
`7`		`-target_link_libraries(yosys PRIVATE yosys_backends_jny)`
	`7`	`+target_link_libraries(yosys PUBLIC yosys_backends_jny)`