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Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak
Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
2 parents 14aad09 + f34c4f2 commit dfe86b5

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2 files changed

+6
-10
lines changed

2 files changed

+6
-10
lines changed

kernel/log.cc

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -664,15 +664,9 @@ const char *log_const(const RTLIL::Const &value, bool autoint)
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665665
const char *log_id(const RTLIL::IdString &str)
666666
{
667-
log_id_cache.push_back(strdup(str.c_str()));
668-
const char *p = log_id_cache.back();
669-
if (p[0] != '\\')
670-
return p;
671-
if (p[1] == '$' || p[1] == '\\' || p[1] == 0)
672-
return p;
673-
if (p[1] >= '0' && p[1] <= '9')
674-
return p;
675-
return p+1;
667+
std::string unescaped = RTLIL::unescape_id(str);
668+
log_id_cache.push_back(strdup(unescaped.c_str()));
669+
return log_id_cache.back();
676670
}
677671

678672
const char *log_str(const char *str)

kernel/satgen.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,9 @@ struct SatGen
101101
else
102102
vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
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} else {
104-
std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset));
104+
std::string wire_name = RTLIL::unescape_id(bit.wire->name);
105+
std::string name = pf +
106+
(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset));
105107
vec.push_back(ez->frozen_literal(name));
106108
imported_signals[pf][bit] = vec.back();
107109
}

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