A question about the benchmark boom_med_pb

[xxccxcxc]

In the benchmark boom_med_pb_unrouted.phys, net 161905 ("system/spiClockDomainWrapper/spi_0/mac/phy/spi_0_dq_0_ie_OBUF") ends at pin "OP" of site "IOB_X0Y2". The pin connects to wire "HPIO_IOBPAIR_31_OP_PIN" in tile "HPIO_L_X35Y0".

However, the node that wire "HPIO_IOBPAIR_31_OP_PIN" belongs to contains only a single wire. And we cannot find any PIP that connects to wire "HPIO_IOBPAIR_31_OP_PIN".

Could you please take a look?

[eddieh-xlnx]

Hi @xxccxcxc.

This is the net_printer result from boom_med_pb_unrouted.phys:

============================================================
Route tree for net: system/spiClockDomainWrapper/spi_0/mac/phy/spi_0_dq_0_ie_OBUF

    Source: 0
    [{      belPin  SLICE_X104Y120 H6LUT O6
            belPin  SLICE_X104Y120 H_O H_O
         }] sitePin SLICE_X104Y120 H_O

    Stub: 0
    [{      sitePin IOB_X0Y2 OP
            belPin  IOB_X0Y2 OP OP
            belPin  IOB_X0Y2 OUTMUX OP
            sitePIP IOB_X0Y2 OUTMUX OP False
            belPin  IOB_X0Y2 OUTMUX OUTB
         }] belPin  IOB_X0Y2 OUTBUF I
============================================================

Indeed, there is one source and one stub.

This is the RWRoute result:

$ python3 net_printer/np.py boom_med_pb_rwroute.phys system/spiClockDomainWrapper/spi_0/mac/phy/spi_0_dq_0_ie_OBUF
============================================================
Route tree for net: system/spiClockDomainWrapper/spi_0/mac/phy/spi_0_dq_0_ie_OBUF

    Source: 0
    [{      belPin  SLICE_X104Y120 H6LUT O6
            belPin  SLICE_X104Y120 H_O H_O
            sitePin SLICE_X104Y120 H_O
            pip     INT_X67Y120 LOGIC_OUTS_W28 INT_NODE_SDQ_90_INT_OUT1 True False
            pip     INT_X67Y120 INT_NODE_SDQ_90_INT_OUT1 WW4_W_BEG7 True False
            pip     INT_X65Y120 WW4_W_END7 SS12_BEG6 True False
            pip     INT_X65Y108 SS12_END6 SS12_BEG7 True False
            pip     INT_X65Y96 SS12_END7 SS12_BEG6 True False
            pip     INT_X65Y84 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y72 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y60 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y48 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y36 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y24 SS12_END6 SS12_BEG6 True False
            pip     INT_X65Y12 SS12_END6 WW12_BEG7 True False
            pip     INT_X59Y12 WW12_END7 WW12_BEG6 True False
            pip     INT_X53Y12 WW12_END6 WW12_BEG6 True False
            pip     INT_X47Y12 WW12_END6 WW12_BEG6 True False
            pip     INT_X41Y12 WW12_END6 SS12_BEG6 True False
            pip     INT_X41Y0 SS12_END6 WW12_BEG7 True False
            pip     INT_X35Y0 WW12_END7 INT_NODE_SDQ_40_INT_OUT0 True False
            pip     INT_X35Y0 INT_NODE_SDQ_40_INT_OUT0 EE1_E_BEG6 True False
            pip     INT_X36Y0 EE1_E_END6 INT_NODE_SDQ_88_INT_OUT0 True False
            pip     INT_X36Y0 INT_NODE_SDQ_88_INT_OUT0 NN2_W_BEG6 True False
            pip     INT_X36Y2 NN2_W_END6 INODE_W_54_FT0 True False
            pip     INT_X36Y3 INODE_W_BLN_54_FT1 BYPASS_W1 True False
            pip     INT_X36Y3 BYPASS_W1 INT_NODE_IMUX_39_INT_OUT1 True False
            pip     INT_X36Y3 INT_NODE_IMUX_39_INT_OUT1 IMUX_W24 True False
            pip     INT_INTF_L_IO_X36Y3 IMUX_R24 IMUX_CMT_XIPHY24 True False
            pip     XIPHY_BYTE_L_X36Y0 XIPHY_BITSLICE_TILE_67_TX_D0 XIPHY_BITSLICE_TILE_67_TX_Q True False
            pip     HPIO_L_X35Y0 HPIO_IOBPAIR_31_OP HPIO_IOBPAIR_31_OP_PIN True False
            sitePin IOB_X0Y2 OP
            belPin  IOB_X0Y2 OP OP
            belPin  IOB_X0Y2 OUTMUX OP
            sitePIP IOB_X0Y2 OUTMUX OP False
            belPin  IOB_X0Y2 OUTMUX OUTB
         }] belPin  IOB_X0Y2 OUTBUF I
============================================================

The line pip HPIO_L_X35Y0 HPIO_IOBPAIR_31_OP HPIO_IOBPAIR_31_OP_PIN True False indicates that there is a PIP from *_OP to *_OP_PIN. Are you not seeing this PIP?

You can select this PIP for inspection in Vivado with the following Tcl:

sel [get_pips HPIO_L_X35Y0/HPIO_L.HPIO_IOBPAIR_31_OP->HPIO_IOBPAIR_31_OP_PIN]

Note that the PIP that precedes it is:

pip     XIPHY_BYTE_L_X36Y0 XIPHY_BITSLICE_TILE_67_TX_D0 XIPHY_BITSLICE_TILE_67_TX_Q True False

which is a routethru ("psuedo") PIP without which it is likely not possible to reach this sink.

Does your router consider routethrus? If not, you'll need to here. Recently, I improved nxroute-poc to consider non-INT/non-RCLK routethrus to resolve problems like this: #51