From 78f3df0493184fe6703d5e712fb9c88c5eefd8c6 Mon Sep 17 00:00:00 2001 From: Javier Valverde Date: Thu, 29 Feb 2024 07:53:33 +0100 Subject: [PATCH 1/2] Fix regex for VHDL component instantiations - Add comments to the multiline regex - Extend unittest for vhdl_parser --- tests/unit/test_vhdl_parser.py | 14 +++++++++++++- vunit/vhdl_parser.py | 13 ++++++++++--- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/tests/unit/test_vhdl_parser.py b/tests/unit/test_vhdl_parser.py index fd8a50518..478b198c9 100644 --- a/tests/unit/test_vhdl_parser.py +++ b/tests/unit/test_vhdl_parser.py @@ -568,15 +568,27 @@ def test_getting_component_instantiations_from_design_file(self): label3Foo : foo3 port map (clk, rst, X"A"); + label4Foo : foo4 + generic map ( + g_POWER => 2 ** 10, + g_DIVIDE => 10 / 5 + ) + port map( + clk => '1', + rst => '0', + output => "00" + ) ; + end architecture; """ ) component_instantiations = design_file.component_instantiations - self.assertEqual(len(component_instantiations), 3) + self.assertEqual(len(component_instantiations), 4) self.assertEqual(component_instantiations[0], "foo") self.assertEqual(component_instantiations[1], "foo2") self.assertEqual(component_instantiations[2], "foo3") + self.assertEqual(component_instantiations[3], "foo4") def test_adding_generics_to_entity(self): entity = VHDLEntity("name") diff --git a/vunit/vhdl_parser.py b/vunit/vhdl_parser.py index 71a58b469..2909e7bcc 100644 --- a/vunit/vhdl_parser.py +++ b/vunit/vhdl_parser.py @@ -85,9 +85,16 @@ def parse(cls, code): ) _component_re = re.compile( - r"[a-zA-Z]\w*\s*\:\s*(?:component)?\s*(?:(?:[a-zA-Z]\w*)\.)?([a-zA-Z]\w*)\s*" - r"(?:generic|port) map\s*\([\s\w\=\>\,\.\)\(\+\-\'\"]*\);", - re.IGNORECASE, + r""" + [a-zA-Z]\w* # Label + \s*\:\s* # Semicolon + (?:component)?\s* # Optional component keyword + (?:(?:[a-zA-Z]\w*)\.)? # Optional library name + ([a-zA-Z]\w*)\s* # Capture component name + (?:generic|port)\s+map\s* # Generic/port map + \(.*?\)\s*; # Open and closing brackets + """, + re.MULTILINE | re.IGNORECASE | re.VERBOSE | re.DOTALL, ) From b2a14e759fe2babd696295554e99bb8228ca99c7 Mon Sep 17 00:00:00 2001 From: Javier Valverde Date: Wed, 13 Mar 2024 15:55:34 +0100 Subject: [PATCH 2/2] Modify as suggested --- vunit/vhdl_parser.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vunit/vhdl_parser.py b/vunit/vhdl_parser.py index 2909e7bcc..494db177b 100644 --- a/vunit/vhdl_parser.py +++ b/vunit/vhdl_parser.py @@ -92,7 +92,7 @@ def parse(cls, code): (?:(?:[a-zA-Z]\w*)\.)? # Optional library name ([a-zA-Z]\w*)\s* # Capture component name (?:generic|port)\s+map\s* # Generic/port map - \(.*?\)\s*; # Open and closing brackets + \([\s\w\=\>\,\.\)\(\+\-\'\"\*\/]*\) """, re.MULTILINE | re.IGNORECASE | re.VERBOSE | re.DOTALL, )