@@ -104,6 +104,41 @@ def program(self, boffile, gain=1, demux_mode=1, chips=('a', 'b', 'c')):
104104 self .adc .calibrate ()
105105 self .logger .info ("Programming complete." )
106106
107+ def upload_to_ram_and_program (self , filename , port = - 1 , timeout = 10 ,
108+ wait_complete = True ,
109+ gain = 1 , demux_mode = 1 , chips = ('a' , 'b' , 'c' )):
110+ """
111+ Upload an FPG file to RAM and then program the FPGA.
112+ :param filename: the file to upload
113+ :param port: the port to use on the rx end, -1 means a random port
114+ :param timeout: how long to wait, seconds
115+ :param wait_complete: wait for the transaction to complete, return
116+ after upload if False
117+ :return:
118+ """
119+ rv = self .transport .upload_to_ram_and_program (
120+ filename , port , timeout , wait_complete )
121+ if filename [- 3 :] == 'fpg' :
122+ self .get_system_information (filename )
123+
124+ if self .is_adc16_based ():
125+ self .logger .info ("Design is ADC16 based. Calibration routines will run." )
126+
127+ # Check in case SnapAdc is already setup
128+ if self .uses_adc :
129+ if not isinstance (self .adc , SnapAdc ):
130+ self .adc = SnapAdc (self )
131+ self .fpga_set_demux (1 )
132+ self .adc .set_chip_select (chips )
133+ self .adc .initialize ()
134+ self .adc .set_demux (demux_mode )
135+ self .adc .set_gain (gain )
136+ self .adc .power_cycle ()
137+ self .adc .calibrate ()
138+ self .logger .info ("Programming complete." )
139+
140+ return rv
141+
107142 def set_debug (self ):
108143 """ Set logger levels to output debug info """
109144 self .logger .setLevel (5 )
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