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Added upload_and_program
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snap_control/snap_board.py

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,41 @@ def program(self, boffile, gain=1, demux_mode=1, chips=('a', 'b', 'c')):
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self.adc.calibrate()
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self.logger.info("Programming complete.")
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def upload_to_ram_and_program(self, filename, port=-1, timeout=10,
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wait_complete=True,
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gain=1, demux_mode=1, chips=('a', 'b', 'c')):
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"""
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Upload an FPG file to RAM and then program the FPGA.
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:param filename: the file to upload
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:param port: the port to use on the rx end, -1 means a random port
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:param timeout: how long to wait, seconds
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:param wait_complete: wait for the transaction to complete, return
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after upload if False
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:return:
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"""
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rv = self.transport.upload_to_ram_and_program(
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filename, port, timeout, wait_complete)
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if filename[-3:] == 'fpg':
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self.get_system_information(filename)
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if self.is_adc16_based():
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self.logger.info("Design is ADC16 based. Calibration routines will run.")
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# Check in case SnapAdc is already setup
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if self.uses_adc:
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if not isinstance(self.adc, SnapAdc):
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self.adc = SnapAdc(self)
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self.fpga_set_demux(1)
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self.adc.set_chip_select(chips)
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self.adc.initialize()
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self.adc.set_demux(demux_mode)
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self.adc.set_gain(gain)
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self.adc.power_cycle()
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self.adc.calibrate()
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self.logger.info("Programming complete.")
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return rv
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def set_debug(self):
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""" Set logger levels to output debug info """
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self.logger.setLevel(5)

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