@@ -1266,39 +1266,39 @@ source %{
12661266 // adlc register classes to make AArch64 rheapbase (r27) and rfp (r29)
12671267 // registers conditionally reserved.
12681268
1269- _ANY_REG32_mask = _ALL_REG32_mask;
1270- _ANY_REG32_mask.Remove (OptoReg::as_OptoReg(r31_sp->as_VMReg()));
1269+ _ANY_REG32_mask.assignFrom( _ALL_REG32_mask) ;
1270+ _ANY_REG32_mask.remove (OptoReg::as_OptoReg(r31_sp->as_VMReg()));
12711271
1272- _ANY_REG_mask = _ALL_REG_mask;
1272+ _ANY_REG_mask.assignFrom( _ALL_REG_mask) ;
12731273
1274- _PTR_REG_mask = _ALL_REG_mask;
1274+ _PTR_REG_mask.assignFrom( _ALL_REG_mask) ;
12751275
1276- _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1277- _NO_SPECIAL_REG32_mask.SUBTRACT (_NON_ALLOCATABLE_REG32_mask);
1276+ _NO_SPECIAL_REG32_mask.assignFrom( _ALL_REG32_mask) ;
1277+ _NO_SPECIAL_REG32_mask.subtract (_NON_ALLOCATABLE_REG32_mask);
12781278
1279- _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1280- _NO_SPECIAL_REG_mask.SUBTRACT (_NON_ALLOCATABLE_REG_mask);
1279+ _NO_SPECIAL_REG_mask.assignFrom( _ALL_REG_mask) ;
1280+ _NO_SPECIAL_REG_mask.subtract (_NON_ALLOCATABLE_REG_mask);
12811281
1282- _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1283- _NO_SPECIAL_PTR_REG_mask.SUBTRACT (_NON_ALLOCATABLE_REG_mask);
1282+ _NO_SPECIAL_PTR_REG_mask.assignFrom( _ALL_REG_mask) ;
1283+ _NO_SPECIAL_PTR_REG_mask.subtract (_NON_ALLOCATABLE_REG_mask);
12841284
12851285 // r27 is not allocatable when compressed oops is on and heapbase is not
12861286 // zero, compressed klass pointers doesn't use r27 after JDK-8234794
12871287 if (UseCompressedOops && (CompressedOops::base() != nullptr)) {
1288- _NO_SPECIAL_REG32_mask.Remove (OptoReg::as_OptoReg(r27->as_VMReg()));
1289- _NO_SPECIAL_REG_mask.Remove (OptoReg::as_OptoReg(r27->as_VMReg()));
1290- _NO_SPECIAL_PTR_REG_mask.Remove (OptoReg::as_OptoReg(r27->as_VMReg()));
1288+ _NO_SPECIAL_REG32_mask.remove (OptoReg::as_OptoReg(r27->as_VMReg()));
1289+ _NO_SPECIAL_REG_mask.remove (OptoReg::as_OptoReg(r27->as_VMReg()));
1290+ _NO_SPECIAL_PTR_REG_mask.remove (OptoReg::as_OptoReg(r27->as_VMReg()));
12911291 }
12921292
12931293 // r29 is not allocatable when PreserveFramePointer is on
12941294 if (PreserveFramePointer) {
1295- _NO_SPECIAL_REG32_mask.Remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1296- _NO_SPECIAL_REG_mask.Remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1297- _NO_SPECIAL_PTR_REG_mask.Remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1295+ _NO_SPECIAL_REG32_mask.remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1296+ _NO_SPECIAL_REG_mask.remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1297+ _NO_SPECIAL_PTR_REG_mask.remove (OptoReg::as_OptoReg(r29->as_VMReg()));
12981298 }
12991299
1300- _NO_SPECIAL_NO_RFP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1301- _NO_SPECIAL_NO_RFP_PTR_REG_mask.Remove (OptoReg::as_OptoReg(r29->as_VMReg()));
1300+ _NO_SPECIAL_NO_RFP_PTR_REG_mask.assignFrom( _NO_SPECIAL_PTR_REG_mask) ;
1301+ _NO_SPECIAL_NO_RFP_PTR_REG_mask.remove (OptoReg::as_OptoReg(r29->as_VMReg()));
13021302 }
13031303
13041304 // Optimizaton of volatile gets and puts
@@ -1734,7 +1734,7 @@ uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
17341734 }
17351735
17361736//=============================================================================
1737- const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty ;
1737+ const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::EMPTY ;
17381738
17391739int ConstantTable::calculate_table_base_offset() const {
17401740 return 0; // absolute addressing, no offset
@@ -2520,10 +2520,10 @@ uint Matcher::int_pressure_limit()
25202520 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
25212521 // derived pointers and lastly fail to spill after reaching maximum
25222522 // number of iterations. Lowering the default pressure threshold to
2523- // (_NO_SPECIAL_REG32_mask.Size () minus 1) forces CallNode to become
2523+ // (_NO_SPECIAL_REG32_mask.size () minus 1) forces CallNode to become
25242524 // a high register pressure area of the code so that split_DEF can
25252525 // generate DefinitionSpillCopy for the derived pointer.
2526- uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size () - 1;
2526+ uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.size () - 1;
25272527 if (!PreserveFramePointer) {
25282528 // When PreserveFramePointer is off, frame pointer is allocatable,
25292529 // but different from other SOC registers, it is excluded from
@@ -2538,34 +2538,34 @@ uint Matcher::int_pressure_limit()
25382538uint Matcher::float_pressure_limit()
25392539{
25402540 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2541- return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size () : FLOATPRESSURE;
2541+ return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.size () : FLOATPRESSURE;
25422542}
25432543
25442544bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
25452545 return false;
25462546}
25472547
2548- RegMask Matcher::divI_proj_mask() {
2548+ const RegMask& Matcher::divI_proj_mask() {
25492549 ShouldNotReachHere();
2550- return RegMask() ;
2550+ return RegMask::EMPTY ;
25512551}
25522552
25532553// Register for MODI projection of divmodI.
2554- RegMask Matcher::modI_proj_mask() {
2554+ const RegMask& Matcher::modI_proj_mask() {
25552555 ShouldNotReachHere();
2556- return RegMask() ;
2556+ return RegMask::EMPTY ;
25572557}
25582558
25592559// Register for DIVL projection of divmodL.
2560- RegMask Matcher::divL_proj_mask() {
2560+ const RegMask& Matcher::divL_proj_mask() {
25612561 ShouldNotReachHere();
2562- return RegMask() ;
2562+ return RegMask::EMPTY ;
25632563}
25642564
25652565// Register for MODL projection of divmodL.
2566- RegMask Matcher::modL_proj_mask() {
2566+ const RegMask& Matcher::modL_proj_mask() {
25672567 ShouldNotReachHere();
2568- return RegMask() ;
2568+ return RegMask::EMPTY ;
25692569}
25702570
25712571bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
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