From c79bbddf7417a962c858b26216258ae28fa9f0b4 Mon Sep 17 00:00:00 2001 From: Daniel Garcia Date: Mon, 6 Apr 2020 12:49:10 +0200 Subject: [PATCH] Register classes Classes to store information about registers and interact with them Signed-off-by: Daniel Garcia --- tbot_contrib/register/SVDParser.py | 37 + tbot_contrib/register/example_testcase.py | 22 + tbot_contrib/register/iMX6SDL.pkl | Bin 0 -> 210186 bytes tbot_contrib/register/iMX6SDL.svd.xml | 340270 +++++++++++++++++++ tbot_contrib/register/register.py | 210 + 5 files changed, 340539 insertions(+) create mode 100644 tbot_contrib/register/SVDParser.py create mode 100644 tbot_contrib/register/example_testcase.py create mode 100644 tbot_contrib/register/iMX6SDL.pkl create mode 100644 tbot_contrib/register/iMX6SDL.svd.xml create mode 100644 tbot_contrib/register/register.py diff --git a/tbot_contrib/register/SVDParser.py b/tbot_contrib/register/SVDParser.py new file mode 100644 index 00000000..7f560843 --- /dev/null +++ b/tbot_contrib/register/SVDParser.py @@ -0,0 +1,37 @@ +import os +import xml.etree.ElementTree as ET +import pickle +import register +from register import Register +class SVDParser: + def __init__(self): + self._groups_dict ={} + self._registers_dict = {} + + def parse_file(self, file_name:str, output_name:str) -> None: + THIS_FOLDER = os.path.dirname(os.path.abspath(__file__)) + file_name = os.path.join(THIS_FOLDER, f"{file_name}") + output_name = os.path.join(THIS_FOLDER, f"{output_name}.pkl") + tree = ET.parse(file_name) + root = tree.getroot() + + cpu_width = int(root.find("width").text) + print(cpu_width) + for peripherals in root.findall("peripherals"): + + for peripheral in peripherals.findall("peripheral"): + group_name= peripheral.find("name").text + base_address = int(peripheral.find("baseAddress").text,16) + print(hex(base_address)) + self._groups_dict[group_name]= [] + for registers in peripheral.findall("registers"): + for register in registers.findall("register"): + register_name = register.find("name").text + register_width = int(register.find("size").text) + register_address = base_address + int(register.find("addressOffset").text,16) + print(hex(register_address)) + self._registers_dict[register_name] = Register(register_name,register_address,register_width) + self._groups_dict[group_name].append(register_name) + + with open(f"{output_name}", "wb") as f: + pickle.dump([cpu_width, self._groups_dict, self._registers_dict], f) diff --git a/tbot_contrib/register/example_testcase.py b/tbot_contrib/register/example_testcase.py new file mode 100644 index 00000000..5d27c570 --- /dev/null +++ b/tbot_contrib/register/example_testcase.py @@ -0,0 +1,22 @@ +import tbot +from register import CPU + + +@tbot.testcase +def testcase_prueba() -> None: + + with tbot.acquire_lab() as lb: + with tbot.acquire_board(lb) as b: + with tbot.acquire_uboot(b) as ub: + cpu2 = CPU(ub, processor_name="iMX6SDL") + cpu2.read_register("VDI_PS_4") + cpu2.write_register("VDI_PS_4", 0x1) + cpu2.read_register("VDI_PS_4") + # cpu2.read_all_registers_from_group("IPU") + with tbot.acquire_linux(ub) as lx: + cpu2.set_host(lx) + # cpu2.read_register("GPUSR1") + # cpu2.read_all_registers_from_group("IPU") + cpu2.read_register("VDI_PS_4") + cpu2.write_register("VDI_PS_4", 0x12) + cpu2.read_register("VDI_PS_4") diff --git a/tbot_contrib/register/iMX6SDL.pkl b/tbot_contrib/register/iMX6SDL.pkl new file mode 100644 index 0000000000000000000000000000000000000000..02f29fd2df490e3af19d5c5a2b501461a40fe043 GIT binary patch literal 210186 zcma%EcYqtk`8B=w-aD8Uv@2Z$0_Y^&ov?J0CEcA32x0JnO|j8uo8Ad65JC%`(0lJa z)P$Ns4WZX01PDD4LixQntJ$3`(*FL?-o5v|`KIpd?Ck99Q47?Y6DCet_weR?6Q?XN zVZwy!j+y5C_2vQ-rz{LKSRScXtmc9qu$v2cAlY1a%0fz3tyY?gCEYpAp~3VvSDUhI zfKr}T57TtGMwq7GHC3TzbEDNu=EQCC;YHrMxHKSFHaV?ErEAUYjH=yU>2(3`&}tT_bi0}MK(g6CWjRztC6~@Nve`-_TWGb$%#`K9k5%%u zoZpaD4bK;#TB|m5%8y@9eqdak!~L0|=3u=!G*P8iRYqQ=kO?2DCYn1cL$Q?2H7BWJ z$qi=!%C$(Vg3~SVzyG>N; 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zeiR~tS^~Xf=qJ!zAtI=2pqCB(4EjZg24Gr|3q2)l8LPXH8K<^t`9<+iG5i~r|2ZmMz zRS6M6BLYn~v=V4#AtGpGpbrhL0;(1wf<^`U$k3{w)r5$k(SbfT)B#i@LNLPXHaK;IeK2DGgZ5i~2% z_lC9uH3|_yvjfdBv^{7CAtGo_pdSqF2x<}{g60PL(a=tyorQ>?-va$)Xcthk5E1lO zpt**21??t81eFZ*-=BUqv^%Ja5D`=w=odqKfc6w3g31E@YG^M|ix3f19_TkidxQ27 zB7!Oc{cdPqP*))$s4~zWhV}#PFGK`Y1^Uy_0ibR|L{N30zYHA+I!K5JstNSBp@Tu) zg@~ZqK>rvz1aznn5mXoGUqgq1T7`(9`amU1+Wk+UBZP>chCmA#Iug`FhzRN!XhB0g zK}QJ@L7f6EWawy6FCikRbD&Z~$AFF%B7zzNEo|sGP;Vh3s437QhK>iFAVdT;2U^t7 ziJ(40L{OJNWrj`yoh(EIwFFws&?%t4LPSv4K#Lpd2Rc=V2*+N86uRu#1ItSDyL)dXrV^bF`(AtIS*XC(91$ZP{%-<8F~dYS%?TKY4cgWxuI7?;s47rrL+^p!7b1eH U18rmI1JHCKBB;huzn&ZZKlu&vmH+?% literal 0 HcmV?d00001 diff --git a/tbot_contrib/register/iMX6SDL.svd.xml b/tbot_contrib/register/iMX6SDL.svd.xml new file mode 100644 index 00000000..eea55861 --- /dev/null +++ b/tbot_contrib/register/iMX6SDL.svd.xml @@ -0,0 +1,340270 @@ + + + iMX6SDL + 1.6 + iMX6SDL Freescale Microcontroller + 8 + 32 + + + SJC + SJC Registers + SJC_ + 0 + + 0 + 0xB + registers + + + + GPUSR1 + General Purpose Unsecured Status Register 1 + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + A_DBG + no description available + 0 + 1 + read-only + + + A_WFI + no description available + 1 + 1 + read-only + + + S_STAT + no description available + 2 + 3 + read-only + + + RESERVED + no description available + 5 + 2 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + PLL_LOCK + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + GPUSR2 + General Purpose Unsecured Status Register 2 + 0x1 + 32 + read-only + 0 + 0xFFFFFFFF + + + STBYWFI + no description available + 0 + 4 + read-only + + + S_STAT + no description available + 4 + 4 + read-only + + + STBYWFE + no description available + 8 + 4 + read-only + + + RESERVED + no description available + 12 + 20 + read-only + + + + + GPUSR3 + General Purpose Unsecured Status Register 3 + 0x2 + 32 + read-only + 0 + 0xFFFFFFFF + + + IPG_WAIT + no description available + 0 + 1 + read-only + + + IPG_STOP + no description available + 1 + 1 + read-only + + + SYS_WAIT + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 29 + read-only + + + + + GPSSR + General Purpose Secured Status Register + 0x3 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPSSR + no description available + 0 + 32 + read-only + + + + + DCR + Debug Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DE_TO_ARM + no description available + 0 + 1 + read-write + + + 0 + Disable propagation of debug request to ARM platform + #0 + + + 1 + Enable propagation of debug request to ARM platform + #1 + + + + + DE_TO_SDMA + no description available + 1 + 1 + read-write + + + 0 + Disable propagation of debug request to SDMA + #0 + + + 1 + Enable propagation of debug request to SDMA + #1 + + + + + RESERVED + no description available + 2 + 1 + read-only + + + DEBUG_OBS + no description available + 3 + 1 + read-write + + + 0 + Disable propagation of system debug to DE_B pin + #0 + + + 1 + unconditional assertion of pad. DE_B + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + DIRECT_SDMA_REQ_EN + no description available + 5 + 1 + read-write + + + 0 + Disable propagation of system debug to (DE_B pin) to sdma. + #0 + + + 1 + Enable propagation of system debug to (DE_B pin) to sdma. + #1 + + + + + DIRECT_ARM_REQ_EN + no description available + 6 + 1 + read-write + + + 0 + Disable propagation of system debug to (DE_B pin) to Arm platform. + #0 + + + 1 + Enable propagation of system debug to (DE_B pin) to Arm platform. + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + SSR + Security Status Register + 0x5 + 32 + read-only + 0x100 + 0xFFFFFFFF + + + KTF + no description available + 0 + 1 + read-only + + + 0 + (intact) - kill trace is never active + #0 + + + 1 + (burned) - kill trace functionality enabled + #1 + + + + + KTA + no description available + 1 + 1 + read-only + + + 1 + active + #1 + + + 0 + not active + #0 + + + + + SWF + no description available + 2 + 1 + read-only + + + 0 + (intact) - SW enable possible + #0 + + + 1 + (intact) - no SW enable possible + #1 + + + + + SWE + no description available + 3 + 1 + read-only + + + 1 + enabled + #1 + + + 0 + disabled + #0 + + + + + EBF + no description available + 4 + 1 + read-only + + + 0 + (intact) - external boot is allowed + #0 + + + 1 + (burned) - external boot is disabled + #1 + + + + + EBG + no description available + 5 + 1 + read-only + + + 1 + granted + #1 + + + 0 + not granted + #0 + + + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + FT + no description available + 8 + 1 + read-only + + + 0 + E-fuse technology + #0 + + + 1 + Laser fuse technology + #1 + + + + + SJM + no description available + 9 + 2 + read-only + + + 00 + No debug (#1) + #00 + + + 01 + Secure JTAG (#2) + #01 + + + 10 + Reserved + #10 + + + 11 + JTAG enabled (#3) + #11 + + + + + RSSTAT + no description available + 11 + 2 + read-only + + + 00 + Response wasn't entered + #00 + + + 01 + Response was entered but not verified + #01 + + + 10 + Response was entered and is incorrect + #10 + + + 11 + Response is correct + #11 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + BOOTIND + no description available + 14 + 1 + read-only + + + RESERVED + no description available + 15 + 2 + read-only + + + RESERVED + no description available + 17 + 15 + read-only + + + + + GPCCR + General Purpose Clocks Control Register + 0x7 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLKR + no description available + 0 + 1 + read-write + + + ACLKOFFDIS + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 30 + read-write + + + + + + + APBH + APBH Register Reference Index + APBH_ + 0x110000 + + 0 + 0x804 + registers + + + + CTRL0 + AHB to APBH Bridge Control and Status Register 0 + 0 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + no description available + 0 + 16 + read-write + + + 1 + NAND0 + #1 + + + 10 + NAND1 + #10 + + + 100 + NAND2 + #100 + + + 1000 + NAND3 + #1000 + + + 10000 + NAND4 + #10000 + + + 100000 + NAND5 + #100000 + + + 1000000 + NAND6 + #1000000 + + + 10000000 + NAND7 + #10000000 + + + 100000000 + SSP + #100000000 + + + + + RSVD0 + no description available + 16 + 12 + read-only + + + APB_BURST_EN + no description available + 28 + 1 + read-write + + + AHB_BURST8_EN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_SET + AHB to APBH Bridge Control and Status Register 0 + 0x4 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + no description available + 0 + 16 + read-write + + + 1 + NAND0 + #1 + + + 10 + NAND1 + #10 + + + 100 + NAND2 + #100 + + + 1000 + NAND3 + #1000 + + + 10000 + NAND4 + #10000 + + + 100000 + NAND5 + #100000 + + + 1000000 + NAND6 + #1000000 + + + 10000000 + NAND7 + #10000000 + + + 100000000 + SSP + #100000000 + + + + + RSVD0 + no description available + 16 + 12 + read-only + + + APB_BURST_EN + no description available + 28 + 1 + read-write + + + AHB_BURST8_EN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_CLR + AHB to APBH Bridge Control and Status Register 0 + 0x8 + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + no description available + 0 + 16 + read-write + + + 1 + NAND0 + #1 + + + 10 + NAND1 + #10 + + + 100 + NAND2 + #100 + + + 1000 + NAND3 + #1000 + + + 10000 + NAND4 + #10000 + + + 100000 + NAND5 + #100000 + + + 1000000 + NAND6 + #1000000 + + + 10000000 + NAND7 + #10000000 + + + 100000000 + SSP + #100000000 + + + + + RSVD0 + no description available + 16 + 12 + read-only + + + APB_BURST_EN + no description available + 28 + 1 + read-write + + + AHB_BURST8_EN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_TOG + AHB to APBH Bridge Control and Status Register 0 + 0xC + 32 + read-write + 0xE0000000 + 0xFFFFFFFF + + + CLKGATE_CHANNEL + no description available + 0 + 16 + read-write + + + 1 + NAND0 + #1 + + + 10 + NAND1 + #10 + + + 100 + NAND2 + #100 + + + 1000 + NAND3 + #1000 + + + 10000 + NAND4 + #10000 + + + 100000 + NAND5 + #100000 + + + 1000000 + NAND6 + #1000000 + + + 10000000 + NAND7 + #10000000 + + + 100000000 + SSP + #100000000 + + + + + RSVD0 + no description available + 16 + 12 + read-only + + + APB_BURST_EN + no description available + 28 + 1 + read-write + + + AHB_BURST8_EN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL1 + AHB to APBH Bridge Control and Status Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + no description available + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + no description available + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + no description available + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + no description available + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + no description available + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + no description available + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + no description available + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + no description available + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + no description available + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + no description available + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + no description available + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + no description available + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + no description available + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + no description available + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + no description available + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + no description available + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + no description available + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + no description available + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + no description available + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + no description available + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + no description available + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + no description available + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + no description available + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + no description available + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + no description available + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + no description available + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + no description available + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + no description available + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + no description available + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + no description available + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + no description available + 31 + 1 + read-write + + + + + CTRL1_SET + AHB to APBH Bridge Control and Status Register 1 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + no description available + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + no description available + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + no description available + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + no description available + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + no description available + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + no description available + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + no description available + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + no description available + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + no description available + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + no description available + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + no description available + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + no description available + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + no description available + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + no description available + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + no description available + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + no description available + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + no description available + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + no description available + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + no description available + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + no description available + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + no description available + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + no description available + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + no description available + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + no description available + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + no description available + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + no description available + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + no description available + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + no description available + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + no description available + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + no description available + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + no description available + 31 + 1 + read-write + + + + + CTRL1_CLR + AHB to APBH Bridge Control and Status Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + no description available + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + no description available + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + no description available + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + no description available + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + no description available + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + no description available + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + no description available + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + no description available + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + no description available + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + no description available + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + no description available + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + no description available + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + no description available + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + no description available + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + no description available + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + no description available + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + no description available + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + no description available + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + no description available + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + no description available + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + no description available + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + no description available + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + no description available + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + no description available + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + no description available + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + no description available + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + no description available + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + no description available + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + no description available + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + no description available + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + no description available + 31 + 1 + read-write + + + + + CTRL1_TOG + AHB to APBH Bridge Control and Status Register 1 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_CMDCMPLT_IRQ + no description available + 0 + 1 + read-write + + + CH1_CMDCMPLT_IRQ + no description available + 1 + 1 + read-write + + + CH2_CMDCMPLT_IRQ + no description available + 2 + 1 + read-write + + + CH3_CMDCMPLT_IRQ + no description available + 3 + 1 + read-write + + + CH4_CMDCMPLT_IRQ + no description available + 4 + 1 + read-write + + + CH5_CMDCMPLT_IRQ + no description available + 5 + 1 + read-write + + + CH6_CMDCMPLT_IRQ + no description available + 6 + 1 + read-write + + + CH7_CMDCMPLT_IRQ + no description available + 7 + 1 + read-write + + + CH8_CMDCMPLT_IRQ + no description available + 8 + 1 + read-write + + + CH9_CMDCMPLT_IRQ + no description available + 9 + 1 + read-write + + + CH10_CMDCMPLT_IRQ + no description available + 10 + 1 + read-write + + + CH11_CMDCMPLT_IRQ + no description available + 11 + 1 + read-write + + + CH12_CMDCMPLT_IRQ + no description available + 12 + 1 + read-write + + + CH13_CMDCMPLT_IRQ + no description available + 13 + 1 + read-write + + + CH14_CMDCMPLT_IRQ + no description available + 14 + 1 + read-write + + + CH15_CMDCMPLT_IRQ + no description available + 15 + 1 + read-write + + + CH0_CMDCMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + CH1_CMDCMPLT_IRQ_EN + no description available + 17 + 1 + read-write + + + CH2_CMDCMPLT_IRQ_EN + no description available + 18 + 1 + read-write + + + CH3_CMDCMPLT_IRQ_EN + no description available + 19 + 1 + read-write + + + CH4_CMDCMPLT_IRQ_EN + no description available + 20 + 1 + read-write + + + CH5_CMDCMPLT_IRQ_EN + no description available + 21 + 1 + read-write + + + CH6_CMDCMPLT_IRQ_EN + no description available + 22 + 1 + read-write + + + CH7_CMDCMPLT_IRQ_EN + no description available + 23 + 1 + read-write + + + CH8_CMDCMPLT_IRQ_EN + no description available + 24 + 1 + read-write + + + CH9_CMDCMPLT_IRQ_EN + no description available + 25 + 1 + read-write + + + CH10_CMDCMPLT_IRQ_EN + no description available + 26 + 1 + read-write + + + CH11_CMDCMPLT_IRQ_EN + no description available + 27 + 1 + read-write + + + CH12_CMDCMPLT_IRQ_EN + no description available + 28 + 1 + read-write + + + CH13_CMDCMPLT_IRQ_EN + no description available + 29 + 1 + read-write + + + CH14_CMDCMPLT_IRQ_EN + no description available + 30 + 1 + read-write + + + CH15_CMDCMPLT_IRQ_EN + no description available + 31 + 1 + read-write + + + + + CTRL2 + AHB to APBH Bridge Control and Status Register 2 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + no description available + 0 + 1 + read-write + + + CH1_ERROR_IRQ + no description available + 1 + 1 + read-write + + + CH2_ERROR_IRQ + no description available + 2 + 1 + read-write + + + CH3_ERROR_IRQ + no description available + 3 + 1 + read-write + + + CH4_ERROR_IRQ + no description available + 4 + 1 + read-write + + + CH5_ERROR_IRQ + no description available + 5 + 1 + read-write + + + CH6_ERROR_IRQ + no description available + 6 + 1 + read-write + + + CH7_ERROR_IRQ + no description available + 7 + 1 + read-write + + + CH8_ERROR_IRQ + no description available + 8 + 1 + read-write + + + CH9_ERROR_IRQ + no description available + 9 + 1 + read-write + + + CH10_ERROR_IRQ + no description available + 10 + 1 + read-write + + + CH11_ERROR_IRQ + no description available + 11 + 1 + read-write + + + CH12_ERROR_IRQ + no description available + 12 + 1 + read-write + + + CH13_ERROR_IRQ + no description available + 13 + 1 + read-write + + + CH14_ERROR_IRQ + no description available + 14 + 1 + read-write + + + CH15_ERROR_IRQ + no description available + 15 + 1 + read-write + + + CH0_ERROR_STATUS + no description available + 16 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH1_ERROR_STATUS + no description available + 17 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH2_ERROR_STATUS + no description available + 18 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH3_ERROR_STATUS + no description available + 19 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH4_ERROR_STATUS + no description available + 20 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH5_ERROR_STATUS + no description available + 21 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH6_ERROR_STATUS + no description available + 22 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH7_ERROR_STATUS + no description available + 23 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH8_ERROR_STATUS + no description available + 24 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH9_ERROR_STATUS + no description available + 25 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH10_ERROR_STATUS + no description available + 26 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH11_ERROR_STATUS + no description available + 27 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH12_ERROR_STATUS + no description available + 28 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH13_ERROR_STATUS + no description available + 29 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH14_ERROR_STATUS + no description available + 30 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + CH15_ERROR_STATUS + no description available + 31 + 1 + read-only + + + 0 + TERMINATION + #0 + + + 1 + BUS_ERROR + #1 + + + + + + + CTRL2_SET + AHB to APBH Bridge Control and Status Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_ERROR_IRQ + no description available + 0 + 1 + read-write + + + CH1_ERROR_IRQ + no description available + 1 + 1 + read-write + + + CH2_ERROR_IRQ + no description available + 2 + 1 + read-write + + + CH3_ERROR_IRQ + no description available + 3 + 1 + read-write + + + CH4_ERROR_IRQ + no description available + 4 + 1 + read-write + + + CH5_ERROR_IRQ + no description available + 5 + 1 + read-write + + + CH6_ERROR_IRQ + no description available + 6 + 1 + read-write + + + CH7_ERROR_IRQ + no description available + 7 + 1 + read-write + + + CH8_ERROR_IRQ + no description available + 8 + 1 + read-write + + + CH9_ERROR_IRQ + no description available + 9 + 1 + read-write + + + CH10_ERROR_IRQ + no description available + 10 + 1 + read-write + + + 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Address does not increment. + #0 + + + 1 + Increment address. + #1 + + + + + ADDRESS + no description available + 17 + 3 + read-write + + + CS + no description available + 20 + 3 + read-write + + + WORD_LENGTH + no description available + 23 + 1 + read-write + + + 0 + Reserved. + #0 + + + 1 + 8-bit Data Bus mode. + #1 + + + + + COMMAND_MODE + no description available + 24 + 2 + read-write + + + 00 + Write mode. + #00 + + + 01 + Read Mode. + #01 + + + 10 + Read and Compare Mode (setting sense flop). + #10 + + + 11 + Wait for Ready. + #11 + + + + + UDMA + no description available + 26 + 1 + read-write + + + 0 + Use ATA-PIO mode on the external bus. + #0 + + + 1 + Use ATA-Ultra DMA mode on the external bus. + #1 + + + + + LOCK_CS + no description available + 27 + 1 + read-write + + + DEV_IRQ_EN + no description available + 28 + 1 + read-write + + + RUN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_SET + GPMI Control Register 0 Description + 0x4 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + no description available + 0 + 16 + read-write + + + ADDRESS_INCREMENT + no description available + 16 + 1 + read-write + + + 0 + Address does not increment. + #0 + + + 1 + Increment address. + #1 + + + + + ADDRESS + no description available + 17 + 3 + read-write + + + CS + no description available + 20 + 3 + read-write + + + WORD_LENGTH + no description available + 23 + 1 + read-write + + + 0 + Reserved. + #0 + + + 1 + 8-bit Data Bus mode. + #1 + + + + + COMMAND_MODE + no description available + 24 + 2 + read-write + + + 00 + Write mode. + #00 + + + 01 + Read Mode. + #01 + + + 10 + Read and Compare Mode (setting sense flop). + #10 + + + 11 + Wait for Ready. + #11 + + + + + UDMA + no description available + 26 + 1 + read-write + + + 0 + Use ATA-PIO mode on the external bus. + #0 + + + 1 + Use ATA-Ultra DMA mode on the external bus. + #1 + + + + + LOCK_CS + no description available + 27 + 1 + read-write + + + DEV_IRQ_EN + no description available + 28 + 1 + read-write + + + RUN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_CLR + GPMI Control Register 0 Description + 0x8 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + no description available + 0 + 16 + read-write + + + ADDRESS_INCREMENT + no description available + 16 + 1 + read-write + + + 0 + Address does not increment. + #0 + + + 1 + Increment address. + #1 + + + + + ADDRESS + no description available + 17 + 3 + read-write + + + CS + no description available + 20 + 3 + read-write + + + WORD_LENGTH + no description available + 23 + 1 + read-write + + + 0 + Reserved. + #0 + + + 1 + 8-bit Data Bus mode. + #1 + + + + + COMMAND_MODE + no description available + 24 + 2 + read-write + + + 00 + Write mode. + #00 + + + 01 + Read Mode. + #01 + + + 10 + Read and Compare Mode (setting sense flop). + #10 + + + 11 + Wait for Ready. + #11 + + + + + UDMA + no description available + 26 + 1 + read-write + + + 0 + Use ATA-PIO mode on the external bus. + #0 + + + 1 + Use ATA-Ultra DMA mode on the external bus. + #1 + + + + + LOCK_CS + no description available + 27 + 1 + read-write + + + DEV_IRQ_EN + no description available + 28 + 1 + read-write + + + RUN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL0_TOG + GPMI Control Register 0 Description + 0xC + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + XFER_COUNT + no description available + 0 + 16 + read-write + + + ADDRESS_INCREMENT + no description available + 16 + 1 + read-write + + + 0 + Address does not increment. + #0 + + + 1 + Increment address. + #1 + + + + + ADDRESS + no description available + 17 + 3 + read-write + + + CS + no description available + 20 + 3 + read-write + + + WORD_LENGTH + no description available + 23 + 1 + read-write + + + 0 + Reserved. + #0 + + + 1 + 8-bit Data Bus mode. + #1 + + + + + COMMAND_MODE + no description available + 24 + 2 + read-write + + + 00 + Write mode. + #00 + + + 01 + Read Mode. + #01 + + + 10 + Read and Compare Mode (setting sense flop). + #10 + + + 11 + Wait for Ready. + #11 + + + + + UDMA + no description available + 26 + 1 + read-write + + + 0 + Use ATA-PIO mode on the external bus. + #0 + + + 1 + Use ATA-Ultra DMA mode on the external bus. + #1 + + + + + LOCK_CS + no description available + 27 + 1 + read-write + + + DEV_IRQ_EN + no description available + 28 + 1 + read-write + + + RUN + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + COMPARE + GPMI Compare Register Description + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFERENCE + no description available + 0 + 16 + read-write + + + MASK + no description available + 16 + 16 + read-write + + + + + ECCCTRL + GPMI Integrated ECC Control Register Description + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + no description available + 0 + 9 + read-write + + + RSVD1 + no description available + 9 + 3 + read-only + + + ENABLE_ECC + no description available + 12 + 1 + read-write + + + ECC_CMD + no description available + 13 + 2 + read-write + + + RSVD2 + no description available + 15 + 1 + read-write + + + HANDLE + no description available + 16 + 16 + read-write + + + + + ECCCTRL_SET + GPMI Integrated ECC Control Register Description + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + no description available + 0 + 9 + read-write + + + RSVD1 + no description available + 9 + 3 + read-only + + + ENABLE_ECC + no description available + 12 + 1 + read-write + + + ECC_CMD + no description available + 13 + 2 + read-write + + + RSVD2 + no description available + 15 + 1 + read-write + + + HANDLE + no description available + 16 + 16 + read-write + + + + + ECCCTRL_CLR + GPMI Integrated ECC Control Register Description + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + no description available + 0 + 9 + read-write + + + RSVD1 + no description available + 9 + 3 + read-only + + + ENABLE_ECC + no description available + 12 + 1 + read-write + + + ECC_CMD + no description available + 13 + 2 + read-write + + + RSVD2 + no description available + 15 + 1 + read-write + + + HANDLE + no description available + 16 + 16 + read-write + + + + + ECCCTRL_TOG + GPMI Integrated ECC Control Register Description + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFFER_MASK + no description available + 0 + 9 + read-write + + + RSVD1 + no description available + 9 + 3 + read-only + + + ENABLE_ECC + no description available + 12 + 1 + read-write + + + ECC_CMD + no description available + 13 + 2 + read-write + + + RSVD2 + no description available + 15 + 1 + read-write + + + HANDLE + no description available + 16 + 16 + read-write + + + + + ECCCOUNT + GPMI Integrated ECC Transfer Count Register Description + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 16 + read-write + + + RSVD2 + no description available + 16 + 16 + read-write + + + + + PAYLOAD + GPMI Payload Address Register Description + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 2 + read-only + + + ADDRESS + no description available + 2 + 30 + read-write + + + + + AUXILIARY + GPMI Auxiliary Address Register Description + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 2 + read-only + + + ADDRESS + no description available + 2 + 30 + read-write + + + + + CTRL1 + GPMI Control Register 1 Description + 0x60 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + no description available + 0 + 1 + read-write + + + 0 + NAND mode. + #0 + + + 1 + ATA mode. + #1 + + + + + CAMERA_MODE + no description available + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + no description available + 2 + 1 + read-write + + + 0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + #0 + + + 1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + #1 + + + + + DEV_RESET + no description available + 3 + 1 + read-write + + + 0 + NANDF_WP_B pin is held low (asserted). + #0 + + + 1 + NANDF_WP_B pin is held high (de-asserted). + #1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + no description available + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + no description available + 7 + 1 + read-write + + + BURST_EN + no description available + 8 + 1 + read-write + + + TIMEOUT_IRQ + no description available + 9 + 1 + read-write + + + DEV_IRQ + no description available + 10 + 1 + read-write + + + DMA2ECC_MODE + no description available + 11 + 1 + read-write + + + RDN_DELAY + no description available + 12 + 4 + read-write + + + HALF_PERIOD + no description available + 16 + 1 + read-write + + + DLL_ENABLE + no description available + 17 + 1 + read-write + + + BCH_MODE + no description available + 18 + 1 + read-write + + + GANGED_RDYBUSY + no description available + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + no description available + 20 + 1 + read-write + + + RSVD1 + no description available + 21 + 1 + read-only + + + WRN_DLY_SEL + no description available + 22 + 2 + read-write + + + DECOUPLE_CS + no description available + 24 + 1 + read-write + + + SSYNCMODE + no description available + 25 + 1 + read-write + + + UPDATE_CS + no description available + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + no description available + 27 + 1 + read-write + + + 0 + internal factor-2 clock divider is disabled + #0 + + + 1 + internal factor-2 clock divider is enabled. + #1 + + + + + TOGGLE_MODE + no description available + 28 + 1 + read-write + + + WRITE_CLK_STOP + no description available + 29 + 1 + read-write + + + SSYNC_CLK_STOP + no description available + 30 + 1 + read-write + + + DEV_CLK_STOP + no description available + 31 + 1 + read-write + + + + + CTRL1_SET + GPMI Control Register 1 Description + 0x64 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + no description available + 0 + 1 + read-write + + + 0 + NAND mode. + #0 + + + 1 + ATA mode. + #1 + + + + + CAMERA_MODE + no description available + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + no description available + 2 + 1 + read-write + + + 0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + #0 + + + 1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + #1 + + + + + DEV_RESET + no description available + 3 + 1 + read-write + + + 0 + NANDF_WP_B pin is held low (asserted). + #0 + + + 1 + NANDF_WP_B pin is held high (de-asserted). + #1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + no description available + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + no description available + 7 + 1 + read-write + + + BURST_EN + no description available + 8 + 1 + read-write + + + TIMEOUT_IRQ + no description available + 9 + 1 + read-write + + + DEV_IRQ + no description available + 10 + 1 + read-write + + + DMA2ECC_MODE + no description available + 11 + 1 + read-write + + + RDN_DELAY + no description available + 12 + 4 + read-write + + + HALF_PERIOD + no description available + 16 + 1 + read-write + + + DLL_ENABLE + no description available + 17 + 1 + read-write + + + BCH_MODE + no description available + 18 + 1 + read-write + + + GANGED_RDYBUSY + no description available + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + no description available + 20 + 1 + read-write + + + RSVD1 + no description available + 21 + 1 + read-only + + + WRN_DLY_SEL + no description available + 22 + 2 + read-write + + + DECOUPLE_CS + no description available + 24 + 1 + read-write + + + SSYNCMODE + no description available + 25 + 1 + read-write + + + UPDATE_CS + no description available + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + no description available + 27 + 1 + read-write + + + 0 + internal factor-2 clock divider is disabled + #0 + + + 1 + internal factor-2 clock divider is enabled. + #1 + + + + + TOGGLE_MODE + no description available + 28 + 1 + read-write + + + WRITE_CLK_STOP + no description available + 29 + 1 + read-write + + + SSYNC_CLK_STOP + no description available + 30 + 1 + read-write + + + DEV_CLK_STOP + no description available + 31 + 1 + read-write + + + + + CTRL1_CLR + GPMI Control Register 1 Description + 0x68 + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + no description available + 0 + 1 + read-write + + + 0 + NAND mode. + #0 + + + 1 + ATA mode. + #1 + + + + + CAMERA_MODE + no description available + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + no description available + 2 + 1 + read-write + + + 0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + #0 + + + 1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + #1 + + + + + DEV_RESET + no description available + 3 + 1 + read-write + + + 0 + NANDF_WP_B pin is held low (asserted). + #0 + + + 1 + NANDF_WP_B pin is held high (de-asserted). + #1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + no description available + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + no description available + 7 + 1 + read-write + + + BURST_EN + no description available + 8 + 1 + read-write + + + TIMEOUT_IRQ + no description available + 9 + 1 + read-write + + + DEV_IRQ + no description available + 10 + 1 + read-write + + + DMA2ECC_MODE + no description available + 11 + 1 + read-write + + + RDN_DELAY + no description available + 12 + 4 + read-write + + + HALF_PERIOD + no description available + 16 + 1 + read-write + + + DLL_ENABLE + no description available + 17 + 1 + read-write + + + BCH_MODE + no description available + 18 + 1 + read-write + + + GANGED_RDYBUSY + no description available + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + no description available + 20 + 1 + read-write + + + RSVD1 + no description available + 21 + 1 + read-only + + + WRN_DLY_SEL + no description available + 22 + 2 + read-write + + + DECOUPLE_CS + no description available + 24 + 1 + read-write + + + SSYNCMODE + no description available + 25 + 1 + read-write + + + UPDATE_CS + no description available + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + no description available + 27 + 1 + read-write + + + 0 + internal factor-2 clock divider is disabled + #0 + + + 1 + internal factor-2 clock divider is enabled. + #1 + + + + + TOGGLE_MODE + no description available + 28 + 1 + read-write + + + WRITE_CLK_STOP + no description available + 29 + 1 + read-write + + + SSYNC_CLK_STOP + no description available + 30 + 1 + read-write + + + DEV_CLK_STOP + no description available + 31 + 1 + read-write + + + + + CTRL1_TOG + GPMI Control Register 1 Description + 0x6C + 32 + read-write + 0x40004 + 0xFFFFFFFF + + + GPMI_MODE + no description available + 0 + 1 + read-write + + + 0 + NAND mode. + #0 + + + 1 + ATA mode. + #1 + + + + + CAMERA_MODE + no description available + 1 + 1 + read-write + + + ATA_IRQRDY_POLARITY + no description available + 2 + 1 + read-write + + + 0 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. + #0 + + + 1 + External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. + #1 + + + + + DEV_RESET + no description available + 3 + 1 + read-write + + + 0 + NANDF_WP_B pin is held low (asserted). + #0 + + + 1 + NANDF_WP_B pin is held high (de-asserted). + #1 + + + + + ABORT_WAIT_FOR_READY_CHANNEL + no description available + 4 + 3 + read-write + + + ABORT_WAIT_REQUEST + no description available + 7 + 1 + read-write + + + BURST_EN + no description available + 8 + 1 + read-write + + + TIMEOUT_IRQ + no description available + 9 + 1 + read-write + + + DEV_IRQ + no description available + 10 + 1 + read-write + + + DMA2ECC_MODE + no description available + 11 + 1 + read-write + + + RDN_DELAY + no description available + 12 + 4 + read-write + + + HALF_PERIOD + no description available + 16 + 1 + read-write + + + DLL_ENABLE + no description available + 17 + 1 + read-write + + + BCH_MODE + no description available + 18 + 1 + read-write + + + GANGED_RDYBUSY + no description available + 19 + 1 + read-write + + + TIMEOUT_IRQ_EN + no description available + 20 + 1 + read-write + + + RSVD1 + no description available + 21 + 1 + read-only + + + WRN_DLY_SEL + no description available + 22 + 2 + read-write + + + DECOUPLE_CS + no description available + 24 + 1 + read-write + + + SSYNCMODE + no description available + 25 + 1 + read-write + + + UPDATE_CS + no description available + 26 + 1 + read-write + + + GPMI_CLK_DIV2_EN + no description available + 27 + 1 + read-write + + + 0 + internal factor-2 clock divider is disabled + #0 + + + 1 + internal factor-2 clock divider is enabled. + #1 + + + + + TOGGLE_MODE + no description available + 28 + 1 + read-write + + + WRITE_CLK_STOP + no description available + 29 + 1 + read-write + + + SSYNC_CLK_STOP + no description available + 30 + 1 + read-write + + + DEV_CLK_STOP + no description available + 31 + 1 + read-write + + + + + TIMING0 + GPMI Timing Register 0 Description + 0x70 + 32 + read-write + 0x10203 + 0xFFFFFFFF + + + DATA_SETUP + no description available + 0 + 8 + read-write + + + DATA_HOLD + no description available + 8 + 8 + read-write + + + ADDRESS_SETUP + no description available + 16 + 8 + read-write + + + RSVD1 + no description available + 24 + 8 + write-only + + + + + TIMING1 + GPMI Timing Register 1 Description + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD1 + no description available + 0 + 16 + read-only + + + DEVICE_BUSY_TIMEOUT + no description available + 16 + 16 + read-write + + + + + TIMING2 + GPMI Timing Register 2 Description + 0x90 + 32 + read-write + 0x3023336 + 0xFFFFFFFF + + + DATA_PAUSE + no description available + 0 + 4 + read-write + + + CMDADD_PAUSE + no description available + 4 + 4 + read-write + + + POSTAMBLE_DELAY + no description available + 8 + 4 + read-write + + + PREAMBLE_DELAY + no description available + 12 + 4 + read-write + + + CE_DELAY + no description available + 16 + 5 + read-write + + + RSVD0 + no description available + 21 + 3 + read-only + + + READ_LATENCY + no description available + 24 + 3 + read-write + + + 000 + READ LATENCY is 0 + #000 + + + 001 + READ LATENCY is 1 + #001 + + + 010 + READ LATENCY is 2 + #010 + + + 011 + READ LATENCY is 3 + #011 + + + 100 + READ LATENCY is 4 + #100 + + + 101 + READ LATENCY is 5 + #101 + + + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + DATA + GPMI DMA Data Transfer Register Description + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + STAT + GPMI Status Register Description + 0xB0 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + PRESENT + no description available + 0 + 1 + read-only + + + 0 + GPMI is not present in this product. + #0 + + + 1 + GPMI is present is in this product. + #1 + + + + + FIFO_FULL + no description available + 1 + 1 + read-only + + + 0 + FIFO is not full. + #0 + + + 1 + FIFO is full. + #1 + + + + + FIFO_EMPTY + no description available + 2 + 1 + read-only + + + 0 + FIFO is not empty. + #0 + + + 1 + FIFO is empty. + #1 + + + + + INVALID_BUFFER_MASK + no description available + 3 + 1 + read-only + + + 0 + ECC Buffer Mask is not invalid. + #0 + + + 1 + ECC Buffer Mask is invalid. + #1 + + + + + ATA_IRQ + no description available + 4 + 1 + read-only + + + RSVD1 + no description available + 5 + 3 + read-only + + + DEV0_ERROR + no description available + 8 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 0. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV1_ERROR + no description available + 9 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 1. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV2_ERROR + no description available + 10 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 2. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV3_ERROR + no description available + 11 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 3. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV4_ERROR + no description available + 12 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 4. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV5_ERROR + no description available + 13 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 5. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV6_ERROR + no description available + 14 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 6. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + DEV7_ERROR + no description available + 15 + 1 + read-only + + + 0 + No error condition present on ATA/NAND Device accessed by DMA channel 7. + #0 + + + 1 + An Error has occurred on ATA/NAND Device accessed by + #1 + + + + + RDY_TIMEOUT + no description available + 16 + 8 + read-only + + + READY_BUSY + no description available + 24 + 8 + read-only + + + + + DEBUG + GPMI Debug Information Register Description + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMD_END + no description available + 0 + 8 + read-only + + + DMAREQ + no description available + 8 + 8 + read-only + + + DMA_SENSE + no description available + 16 + 8 + read-only + + + WAIT_FOR_READY_END + no description available + 24 + 8 + read-only + + + + + VERSION + GPMI Version Register Description + 0xD0 + 32 + read-only + 0x5010000 + 0xFFFFFFFF + + + STEP + no description available + 0 + 16 + read-only + + + MINOR + no description available + 16 + 8 + read-only + + + MAJOR + no description available + 24 + 8 + read-only + + + + + DEBUG2 + GPMI Debug2 Information Register Description + 0xE0 + 32 + read-write + 0xF100 + 0xFFFFFFFF + + + RDN_TAP + no description available + 0 + 6 + read-only + + + UPDATE_WINDOW + no description available + 6 + 1 + read-only + + + VIEW_DELAYED_RDN + no description available + 7 + 1 + read-write + + + SYND2GPMI_READY + no description available + 8 + 1 + read-only + + + SYND2GPMI_VALID + no description available + 9 + 1 + read-only + + + GPMI2SYND_READY + no description available + 10 + 1 + read-only + + + GPMI2SYND_VALID + no description available + 11 + 1 + read-only + + + SYND2GPMI_BE + no description available + 12 + 4 + read-only + + + MAIN_STATE + no description available + 16 + 4 + read-only + + + PIN_STATE + no description available + 20 + 3 + read-only + + + BUSY + no description available + 23 + 1 + read-only + + + UDMA_STATE + no description available + 24 + 4 + read-only + + + RSVD1 + no description available + 28 + 4 + read-write + + + + + DEBUG3 + GPMI Debug3 Information Register Description + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEV_WORD_CNTR + no description available + 0 + 16 + read-only + + + APB_WORD_CNTR + no description available + 16 + 16 + read-only + + + + + READ_DDR_DLL_CTRL + GPMI Double Rate Read DLL Control Register Description + 0x100 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + RESET + no description available + 1 + 1 + read-write + + + SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + SLV_DLY_TARGET + no description available + 3 + 4 + read-write + + + GATE_UPDATE + no description available + 7 + 1 + read-write + + + REFCLK_ON + no description available + 8 + 1 + read-write + + + SLV_OVERRIDE + no description available + 9 + 1 + read-write + + + SLV_OVERRIDE_VAL + no description available + 10 + 8 + read-write + + + RSVD1 + no description available + 18 + 2 + read-only + + + SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + WRITE_DDR_DLL_CTRL + GPMI Double Rate Write DLL Control Register Description + 0x110 + 32 + read-write + 0x38 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + RESET + no description available + 1 + 1 + read-write + + + SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + SLV_DLY_TARGET + no description available + 3 + 4 + read-write + + + GATE_UPDATE + no description available + 7 + 1 + read-write + + + REFCLK_ON + no description available + 8 + 1 + read-write + + + SLV_OVERRIDE + no description available + 9 + 1 + read-write + + + SLV_OVERRIDE_VAL + no description available + 10 + 8 + read-write + + + RSVD1 + no description available + 18 + 2 + read-only + + + SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + READ_DDR_DLL_STS + GPMI Double Rate Read DLL Status Register Description + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + no description available + 0 + 1 + read-only + + + SLV_SEL + no description available + 1 + 8 + read-only + + + RSVD0 + no description available + 9 + 7 + read-only + + + REF_LOCK + no description available + 16 + 1 + read-only + + + REF_SEL + no description available + 17 + 8 + read-only + + + RSVD1 + no description available + 25 + 7 + read-only + + + + + WRITE_DDR_DLL_STS + GPMI Double Rate Write DLL Status Register Description + 0x130 + 32 + read-only + 0 + 0xFFFFFFFF + + + SLV_LOCK + no description available + 0 + 1 + read-only + + + SLV_SEL + no description available + 1 + 8 + read-only + + + RSVD0 + no description available + 9 + 7 + read-only + + + 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+ 2 + 1 + read-write + + + fifofullremap + no description available + 3 + 1 + read-write + + + fifoemptypp + no description available + 4 + 1 + read-write + + + fifofullpp + no description available + 5 + 1 + read-write + + + fifoemptyrepet + no description available + 6 + 1 + read-write + + + fifofullrepet + no description available + 7 + 1 + read-write + + + + + IH_I2CMPHY_STAT0 + PHY GEN2 I2C Master Interrupt Status Register + 0x108 + 8 + read-write + 0 + 0xFF + + + i2cmphyerror + no description available + 0 + 1 + read-write + + + i2cmphydone + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + IH_AHBDMAAUD_STAT0 + AHB Audio DMA Interrupt Status Register + 0x109 + 8 + read-write + 0 + 0xFF + + + ahbdmaaud_intbuffempty + no description available + 0 + 1 + read-write + + + ahbdmaaud_intbufffull + no description available + 1 + 1 + read-write + + + ahbdmaaud_intdone + no description available + 2 + 1 + read-write + + + ahbdmaaud_intretrysplit + no description available + 3 + 1 + read-write + + + ahbdmaaud_intlostownership + no description available + 4 + 1 + read-write + + + ahbdmaaud_interror + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + IH_MUTE_FC_STAT0 + Frame Composer Interrupt Mute Control Register 0 + 0x180 + 8 + read-write + 0 + 0xFF + + + NULL + no description available + 0 + 1 + read-write + + + ACR + no description available + 1 + 1 + read-write + + + AUDS + no description available + 2 + 1 + read-write + + + OBA + no description available + 3 + 1 + read-write + + + DST + no description available + 4 + 1 + read-write + + + HBR + no description available + 5 + 1 + read-write + + + ACP + no description available + 6 + 1 + read-write + + + AUDI + no description available + 7 + 1 + read-write + + + + + IH_MUTE_FC_STAT1 + Frame Composer Interrupt Mute Control Register 1 + 0x181 + 8 + read-write + 0 + 0xFF + + + GCP + no description available + 0 + 1 + read-write + + + AVI + no description available + 1 + 1 + read-write + + + MPEG + no description available + 2 + 1 + read-write + + + SPD + no description available + 3 + 1 + read-write + + + VSD + no description available + 4 + 1 + read-write + + + ISCR2 + no description available + 5 + 1 + read-write + + + ISCR1 + no description available + 6 + 1 + read-write + + + GMD + no description available + 7 + 1 + read-write + + + + + IH_MUTE_FC_STAT2 + Frame Composer Interrupt Mute Control Register 2 + 0x182 + 8 + read-write + 0 + 0xFF + + + HighPriority_overflow + no description available + 0 + 1 + read-write + + + LowPriority_overflow + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + IH_MUTE_AS_STAT0 + Audio Sampler Interrupt Mute Control Register 0 + 0x183 + 8 + read-write + 0 + 0xFF + + + Aud_fifo_overflow + no description available + 0 + 1 + read-write + + + Aud_fifo_underflow + no description available + 1 + 1 + read-write + + + Aud_fifo_underflow_thr + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 5 + read-only + + + + + IH_MUTE_PHY_STAT0 + PHY Interface Interrupt Mute Control Register + 0x184 + 8 + read-write + 0 + 0xFF + + + HDP + no description available + 0 + 1 + read-write + + + TX_PHY_LOCK + no description available + 1 + 1 + read-write + + + RX_SENSE0 + no description available + 2 + 1 + read-write + + + RX_SENSE1 + no description available + 3 + 1 + read-write + + + RX_SENSE2 + no description available + 4 + 1 + read-write + + + RX_SENSE3 + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + IH_MUTE_I2CM_STAT0 + E-DDC I2C Master Interrupt Mute Control Register + 0x185 + 8 + read-write + 0 + 0xFF + + + I2CMASTER_ERROR + no description available + 0 + 1 + read-write + + + I2Cmasterdone + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + IH_MUTE_CEC_STAT0 + CEC Interrupt Mute Control Register + 0x186 + 8 + read-write + 0 + 0xFF + + + DONE + no description available + 0 + 1 + read-write + + + EOM + no description available + 1 + 1 + read-write + + + NACK + no description available + 2 + 1 + read-write + + + ARB_LOST + no description available + 3 + 1 + read-write + + + ERROR_INITIATOR + no description available + 4 + 1 + read-write + + + ERROR_FOLLOW + no description available + 5 + 1 + read-write + + + WAKEUP + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + IH_MUTE_VP_STAT0 + Video Packetizer Interrupt Mute Control Register + 0x187 + 8 + read-write + 0 + 0xFF + + + fifoemptybyp + no description available + 0 + 1 + read-write + + + fifofullbyp + no description available + 1 + 1 + read-write + + + fifoemptyremap + no description available + 2 + 1 + read-write + + + fifofullremap + no description available + 3 + 1 + read-write + + + fifoemptypp + no description available + 4 + 1 + read-write + + + fifofullpp + no description available + 5 + 1 + read-write + + + fifoemptyrepet + no description available + 6 + 1 + read-write + + + fifofullrepet + no description available + 7 + 1 + read-write + + + + + IH_MUTE_I2CMPHY_STAT0 + PHY GEN 2 I2C Master Interrupt Mute Control Register + 0x188 + 8 + read-write + 0 + 0xFF + + + i2cmphyerror + no description available + 0 + 1 + read-write + + + i2cmphydone + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + IH_MUTE_AHBDMAAUD_STAT0 + AHB Audio DMA Interrupt Mute Control Register + 0x189 + 8 + read-write + 0 + 0xFF + + + ahbdmaaud_intbuffempty + no description available + 0 + 1 + read-write + + + ahbdmaaud_intbufffull + no description available + 1 + 1 + read-write + + + ahbdmaaud_intdone + no description available + 2 + 1 + read-write + + + ahbdmaaud_intretrysplit + no description available + 3 + 1 + read-write + + + ahbdmaaud_intlostownership + no description available + 4 + 1 + read-write + + + ahbdmaaud_interror + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + IH_MUTE + Global Interrupt Mute Control Register + 0x1FF + 8 + read-write + 0x3 + 0xFF + + + ahbdmaaud_intbuffempty + no description available + 0 + 1 + read-write + + + ahbdmaaud_intbufffull + no description available + 1 + 1 + read-write + + + ahbdmaaud_intdone + no description available + 2 + 1 + read-write + + + ahbdmaaud_intretrysplit + no description available + 3 + 1 + read-write + + + ahbdmaaud_intlostownership + no description available + 4 + 1 + read-write + + + ahbdmaaud_interror + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + TX_INVID0 + Video Input Mapping and Internal Data Enable Configuration Register + 0x200 + 8 + read-write + 0x1 + 0xFF + + + video_mapping + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 2 + read-only + + + internal_de_generator + no description available + 7 + 1 + read-write + + + + + TX_INSTUFFING + Video Input Stuffing Enable Register + 0x201 + 8 + read-write + 0 + 0xFF + + + GYDATA_STUFFING + no description available + 0 + 1 + read-write + + + 0 + when the dataen signal is low, the value in the gydata[15:0] output is the one sampled from the corresponding input data. + #0 + + + 1 + When the dataen signal is low, the value in the gydata[15:0] output is given by the values in TX_GYDTA0 and TX_GYDATA1 registers. + #1 + + + + + RCRDATA_STUFFING + no description available + 1 + 1 + read-write + + + 0 + When the dataen signal is low, the value in the rcrdata[15:0] output is the one sampled from the corresponding input data. + #0 + + + 1 + When the dataen signal is low, the value in the rcrdata[15:0] output is given by the values in TX_RCRDTA0 and TX_RCRDATA1 registers. + #1 + + + + + BCBDATA_STUFFING + no description available + 2 + 1 + read-write + + + 0 + When the dataen signal is low, the value in the bcbdata[15:0] output is the one sampled from the corresponding input data. + #0 + + + 1 + When the dataen signal is low, the value in the bcbdata[15:0] output is given by the values in register TX_BCBDTA0 and TX_BCBDATA1. + #1 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + + + TX_GYDATA0 + Video Input GY Data Channel Stuffing Register 0 + 0x202 + 8 + read-write + 0 + 0xFF + + + gydata + no description available + 0 + 8 + read-write + + + + + TX_GYDATA1 + Video Input GY Data Channel Stuffing Register 1 + 0x203 + 8 + read-write + 0 + 0xFF + + + gydata + no description available + 0 + 8 + read-write + + + + + TX_RCRDATA0 + Video Input RCR Data Channel Stuffing Register 0 + 0x204 + 8 + read-write + 0 + 0xFF + + + rcrdata + no description available + 0 + 8 + read-write + + + + + TX_RCRDATA1 + Video Input RCR Data Channel Stuffing Register 1 + 0x205 + 8 + read-write + 0 + 0xFF + + + rcrdata + no description available + 0 + 8 + read-write + + + + + TX_BCBDATA0 + Video Input RCB Data Channel Stuffing Register 0 + 0x206 + 8 + read-write + 0 + 0xFF + + + bcbdata + no description available + 0 + 8 + read-write + + + + + TX_BCBDATA1 + Video Input RCB Data Channel Stuffing Register 1 + 0x207 + 8 + read-write + 0 + 0xFF + + + bcbdata + no description available + 0 + 8 + read-write + + + + + VP_STATUS + Video Packetizer Packing Phase Status Register + 0x800 + 8 + read-only + 0 + 0xFF + + + packing_phase + no description available + 0 + 4 + read-only + + + RESERVED + no description available + 4 + 4 + read-only + + + + + VP_PR_CD + Video Packetizer Pixel Repetition and Color Depth Register + 0x801 + 8 + read-write + 0 + 0xFF + + + desired_pr_factor + no description available + 0 + 4 + read-write + + + 0000 + No pixel repetition (pixel sent only once) + #0000 + + + 0001 + Pixel sent 2 times (pixel repeated once) + #0001 + + + 0010 + Pixel sent 3 times + #0010 + + + 0011 + Pixel sent 4 times + #0011 + + + 0100 + Pixel sent 5 times + #0100 + + + 0101 + Pixel sent 6 times + #0101 + + + 0110 + Pixel sent 7 times + #0110 + + + 0111 + Pixel sent 8 times + #0111 + + + 1000 + Pixel sent 9 times + #1000 + + + 1001 + Pixel sent 10 times + #1001 + + + + + color_depth + no description available + 4 + 4 + read-write + + + 0000 + 24 bits per pixel video (8 bit per component). 8-bit packing mode. + #0000 + + + 0100 + 24 bits per pixel video (8 bit per component). 8-bit packing mode. + #0100 + + + 0101 + 30 bits per pixel video (10 bit per component). 10-bit packing mode. + #0101 + + + 0110 + 36 bits per pixel video (12 bit per component). 12-bit packing mode. + #0110 + + + 0111 + 48 bits per pixel video (16 bit per component). 16-bit packing mode. + #0111 + + + + + + + VP_STUFF + Video Packetizer Stuffing and Default Packing Phase Register + 0x802 + 8 + read-write + 0 + 0xFF + + + pr_stuffing + no description available + 0 + 1 + read-write + + + 0 + Pixel repeater block in direct mode (input blanking data goes directly to output). + #0 + + + 1 + Pixel repeater block in stuffing mode. When "de" goes to low the outputs are fixed to 0x00. + #1 + + + + + pp_stuffing + no description available + 1 + 1 + read-write + + + 0 + Pixel packing block in direct mode (input blanking data goes directly to output). + #0 + + + 1 + Pixel packing block in stuffing mode. When "de_rep" goes to low the outputs are fixed to 0x00. + #1 + + + + + ycc422_stuffing + no description available + 2 + 1 + read-write + + + 0 + YCC 422 remap block in direct mode (input blanking data goes directly to output). + #0 + + + 1 + YCC 422 remap block in stuffing mode. When "de" goes to low the outputs are fixed to 0x00. + #1 + + + + + icx_goto_p0_st + no description available + 3 + 1 + read-write + + + ifix_pp_to_last + no description available + 4 + 1 + read-write + + + idefault_phase + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + VP_REMAP + Video Packetizer YCC422 Remapping Register + 0x803 + 8 + read-write + 0 + 0xFF + + + ycc422_size + no description available + 0 + 2 + read-write + + + 00 + YCC 422 16-bit input video (8 bits per component). + #00 + + + 01 + YCC 422 20-bit input video (10 bits per component). + #01 + + + 10 + YCC 422 24-bit input video (12 bits per component). + #10 + + + 11 + Reserved. Not used. + #11 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + + + VP_CONF + Video Packetizer Output, Bypass, and Enable Configuration Register + 0x804 + 8 + read-write + 0x46 + 0xFF + + + output_selector + no description available + 0 + 2 + read-write + + + 00 + Data from pixel packing block. + #00 + + + 01 + Data from YCC 422 remap block. + #01 + + + 10 + Data from 8-bit bypass block. + #10 + + + 11 + Data from 8-bit bypass block. + #11 + + + + + BYPASS_SELECT + no description available + 2 + 1 + read-write + + + 0 + Data from pixel repeater block. + #0 + + + 1 + Data from input of video packetizer block. + #1 + + + + + ycc422_en + no description available + 3 + 1 + read-write + + + pr_en + no description available + 4 + 1 + read-write + + + pp_en + no description available + 5 + 1 + read-write + + + bypass_en + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + VP_MASK + Video Packetizer Interrupt Mask Register + 0x807 + 8 + read-write + 0 + 0xFF + + + VPMASK0 + no description available + 0 + 1 + read-write + + + VPMASK1 + no description available + 1 + 1 + read-write + + + VPMASK2 + no description available + 2 + 1 + read-write + + + VPMASK3 + no description available + 3 + 1 + read-write + + + VPMASK4 + no description available + 4 + 1 + read-write + + + VPMASK5 + no description available + 5 + 1 + read-write + + + VPMASK6 + no description available + 6 + 1 + read-write + + + VPMASK7 + no description available + 7 + 1 + read-write + + + + + FC_INHACTIV0 + Frame Composer Input Video HActive Pixels Register 0 + 0x1001 + 8 + read-write + 0 + 0xFF + + + H_in_activ + no description available + 0 + 8 + read-write + + + + + FC_INHACTIV1 + Frame Composer Input Video HActive Pixels Register 1 + 0x1002 + 8 + read-write + 0 + 0xFF + + + H_in_activ + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_INHBLANK0 + Frame Composer Input Video HBlank Pixels Register 0 + 0x1003 + 8 + read-write + 0 + 0xFF + + + H_in_blank + no description available + 0 + 8 + read-write + + + + + FC_INHBLANK1 + Frame Composer Input Video HBlank Pixels Register 1 + 0x1004 + 8 + read-write + 0 + 0xFF + + + H_in_blank + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_INVACTIV0 + Frame Composer Input Video VActive Pixels Register 0 + 0x1005 + 8 + read-write + 0 + 0xFF + + + V_in_activ + no description available + 0 + 8 + read-write + + + + + FC_INVACTIV1 + Frame Composer Input Video VActive Pixels Register 1 + 0x1006 + 8 + read-write + 0 + 0xFF + + + V_in_activ + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_INVBLANK + Frame Composer Input Video VBlank Pixels Register + 0x1007 + 8 + read-write + 0 + 0xFF + + + V_in_blank + no description available + 0 + 8 + read-write + + + + + FC_HSYNCINDELAY0 + Frame Composer Input Video HSync Front Porch Register 0 + 0x1008 + 8 + read-write + 0 + 0xFF + + + H_in_delay + no description available + 0 + 8 + read-write + + + + + FC_HSYNCINDELAY1 + Frame Composer Input Video HSync Front Porch Register 1 + 0x1009 + 8 + read-write + 0 + 0xFF + + + H_in_delay + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_HSYNCINWIDTH0 + Frame Composer Input Video HSync Width Register 0 + 0x100A + 8 + read-write + 0 + 0xFF + + + H_in_width + no description available + 0 + 8 + read-write + + + + + FC_HSYNCINWIDTH1 + Frame Composer Input Video HSync Width Register 1 + 0x100B + 8 + read-write + 0 + 0xFF + + + H_in_width + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + FC_VSYNCINDELAY + Frame Composer Input Video VSync Front Porch Register + 0x100C + 8 + read-write + 0 + 0xFF + + + V_in_delay + no description available + 0 + 8 + read-write + + + + + FC_VSYNCINWIDTH + Frame Composer Input Video VSync Width Register + 0x100D + 8 + read-write + 0 + 0xFF + + + V_in_width + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + FC_INFREQ0 + Frame Composer Input Video Refresh Rate Register 0 + 0x100E + 8 + read-write + 0 + 0xFF + + + infreq + no description available + 0 + 8 + read-write + + + + + FC_INFREQ1 + Frame Composer Input Video Refresh Rate Register 1 + 0x100F + 8 + read-write + 0 + 0xFF + + + infreq + no description available + 0 + 8 + read-write + + + + + FC_INFREQ2 + Frame Composer Input Video Refresh Rate Register 2 + 0x1010 + 8 + read-write + 0 + 0xFF + + + infreq + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_CTRLDUR + Frame Composer Control Period Duration Register + 0x1011 + 8 + read-write + 0 + 0xFF + + + ctrlperiodduration + no description available + 0 + 8 + read-write + + + + + FC_EXCTRLDUR + Frame Composer Extended Control Period Duration Register + 0x1012 + 8 + read-write + 0 + 0xFF + + + exctrlperiodduration + no description available + 0 + 8 + read-write + + + + + FC_EXCTRLSPAC + Frame Composer Extended Control Period Maximum Spacing Register + 0x1013 + 8 + read-write + 0 + 0xFF + + + exctrlperiodspacing + no description available + 0 + 8 + read-write + + + + + FC_CH0PREAM + Frame Composer Channel 0 Non-Preamble Data Register + 0x1014 + 8 + read-write + 0 + 0xFF + + + ch0_preamble_filter + no description available + 0 + 8 + read-write + + + + + FC_CH1PREAM + Frame Composer Channel 1 Non-Preamble Data Register + 0x1015 + 8 + read-write + 0 + 0xFF + + + ch1_preamble_filter + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + FC_CH2PREAM + Frame Composer Channel 2 Non-Preamble Data Register + 0x1016 + 8 + read-write + 0 + 0xFF + + + ch2_preamble_filter + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + FC_AVICONF3 + Frame Composer AVI Configuration Register 3 + 0x1017 + 8 + read-write + 0 + 0xFF + + + CN1_CN0 + no description available + 0 + 2 + read-write + + + YQ1_YQ0_YCC + no description available + 2 + 2 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_GCP + Frame Composer GCP Packet Configuration Register + 0x1018 + 8 + read-write + 0 + 0xFF + + + clear_avmute + no description available + 0 + 1 + read-write + + + set_avmute + no description available + 1 + 1 + read-write + + + default_phase + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 5 + read-only + + + + + FC_AVICONF0 + Frame Composer AVI Packet Configuration Register 0 + 0x1019 + 8 + read-write + 0 + 0xFF + + + FC_AVICONF0_RGB_YCC + no description available + 0 + 2 + read-write + + + FC_AVICONF0_BAR + no description available + 2 + 2 + read-write + + + FC_AVICONF0_SCAN + no description available + 4 + 2 + read-write + + + FC_AVICONF0_ACTIVE_FORMAT + no description available + 6 + 1 + read-write + + + FC_AVICONF0_MISC + no description available + 7 + 1 + read-write + + + + + FC_AVICONF1 + Frame Composer AVI Packet Configuration Register 1 + 0x101A + 8 + read-write + 0 + 0xFF + + + FC_AVICONF1_ACTIVE_AR + no description available + 0 + 4 + read-write + + + FC_AVICONF1_PICTURE_AR + no description available + 4 + 2 + read-write + + + FC_AVICONF0_COLOR + no description available + 6 + 2 + read-write + + + + + FC_AVICONF2 + FC_AVICONFFrame Composer AVI Packet Configuration Register 2 + 0x101B + 8 + read-write + 0 + 0xFF + + + FC_AVICONF2_SCALE + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 2 + read-write + + + FC_AVICONF2_EXT_COLOR + no description available + 4 + 3 + read-write + + + FC_AVICONF2_IT + no description available + 7 + 1 + read-write + + + + + FC_AVIVID + Frame Composer AVI Packet VIC Register + 0x101C + 8 + read-write + 0 + 0xFF + + + FC_AVIVID + no description available + 0 + 8 + read-write + + + + + FC_AVIETB0 + Frame Composer AVI Packet End of Top Bar Register 0 + 0x101D + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_AVIETB1 + Frame Composer AVI Packet End of Top Bar Register 1 + 0x101E + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_AVISBB0 + Frame Composer AVI Packet Start of Bottom Bar Register 0 + 0x101F + 8 + read-write + 0 + 0xFF + + + FC_AVISBB0 + no description available + 0 + 8 + read-write + + + + + FC_AVISBB1 + Frame Composer AVI Packet Start of Bottom Bar Register 1 + 0x1020 + 8 + read-write + 0 + 0xFF + + + FC_AVISBB1 + no description available + 0 + 8 + read-write + + + + + FC_AVIELB0 + Frame Composer AVI Packet End of Left Bar Register 0 + 0x1021 + 8 + read-write + 0 + 0xFF + + + FC_AVIELB0 + no description available + 0 + 8 + read-write + + + + + FC_AVIELB1 + Frame Composer AVI Packet End of Left Bar Register 1 + 0x1022 + 8 + read-write + 0 + 0xFF + + + FC_AVIELB1 + no description available + 0 + 8 + read-write + + + + + FC_AVISRB0 + Frame Composer AVI Packet Start of Right Bar Register 0 + 0x1023 + 8 + read-write + 0 + 0xFF + + + FC_AVISRB0 + no description available + 0 + 8 + read-write + + + + + FC_AVISRB1 + Frame Composer AVI Packet Start of Right Bar Register 1 + 0x1024 + 8 + read-write + 0 + 0xFF + + + FC_AVISRB1 + no description available + 0 + 8 + read-write + + + + + FC_AUDICONF0 + Frame Composer AUD Packet Configuration Register 0 + 0x1025 + 8 + read-write + 0 + 0xFF + + + CT + no description available + 0 + 4 + read-write + + + CC + no description available + 4 + 3 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + FC_AUDICONF1 + Frame Composer AUD Packet Configuration Register 1 + 0x1026 + 8 + read-write + 0 + 0xFF + + + SF + no description available + 0 + 3 + read-write + + + RESERVED + no description available + 3 + 1 + read-only + + + SS + no description available + 4 + 2 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + FC_AUDICONF2 + Frame Composer AUD Packet Configuration Register 2 + 0x1027 + 8 + read-write + 0 + 0xFF + + + CA + no description available + 0 + 8 + read-write + + + + + FC_AUDICONF3 + Frame Composer AUD Packet Configuration Register 3 + 0x1028 + 8 + read-write + 0 + 0xFF + + + LSV + no description available + 0 + 4 + read-write + + + DM_INH + no description available + 4 + 1 + read-write + + + LFEPBL + no description available + 5 + 2 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + FC_VSDIEEEID0 + Frame Composer VSI Packet Data IEEE Register 0 + 0x1029 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDSIZE + Frame Composer VSI Packet Data Size Register + 0x102A + 8 + read-write + 0x1B + 0xFF + + + VSDSIZE + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_VSDIEEEID1 + Frame Composer VSI Packet Data IEEE Register 1 + 0x1030 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDIEEEID2 + Frame Composer VSI Packet Data IEEE Register 2 + 0x1031 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD0 + Frame Composer VSI Packet Data IEEE Register 0 + 0x1032 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD1 + Frame Composer VSI Packet Data IEEE Register 1 + 0x1033 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD2 + Frame Composer VSI Packet Data IEEE Register 2 + 0x1034 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD3 + Frame Composer VSI Packet Data IEEE Register 3 + 0x1035 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD4 + Frame Composer VSI Packet Data IEEE Register 4 + 0x1036 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD5 + Frame Composer VSI Packet Data IEEE Register 5 + 0x1037 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD6 + Frame Composer VSI Packet Data IEEE Register 6 + 0x1038 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD7 + Frame Composer VSI Packet Data IEEE Register 7 + 0x1039 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD8 + Frame Composer VSI Packet Data IEEE Register 8 + 0x103A + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD9 + Frame Composer VSI Packet Data IEEE Register 9 + 0x103B + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD10 + Frame Composer VSI Packet Data IEEE Register 10 + 0x103C + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD11 + Frame Composer VSI Packet Data IEEE Register 11 + 0x103D + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD12 + Frame Composer VSI Packet Data IEEE Register 12 + 0x103E + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD13 + Frame Composer VSI Packet Data IEEE Register 13 + 0x103F + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD14 + Frame Composer VSI Packet Data IEEE Register 14 + 0x1040 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD15 + Frame Composer VSI Packet Data IEEE Register 15 + 0x1041 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD16 + Frame Composer VSI Packet Data IEEE Register 16 + 0x1042 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD17 + Frame Composer VSI Packet Data IEEE Register 17 + 0x1043 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD18 + Frame Composer VSI Packet Data IEEE Register 18 + 0x1044 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD19 + Frame Composer VSI Packet Data IEEE Register 19 + 0x1045 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD20 + Frame Composer VSI Packet Data IEEE Register 20 + 0x1046 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD21 + Frame Composer VSI Packet Data IEEE Register 21 + 0x1047 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD22 + Frame Composer VSI Packet Data IEEE Register 22 + 0x1048 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_VSDPAYLOAD23 + Frame Composer VSI Packet Data IEEE Register 23 + 0x1049 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 8 + read-write + + + + + FC_SPDVENDORNAME0 + Frame Composer SPD Packet Data Vendor Name Register 0 + 0x104A + 8 + read-write + 0 + 0xFF + + + vendor_name + no description available + 0 + 8 + read-write + + + + + FC_SPDPRODUCTNAME0 + Frame Composer SPD Packet Data Product Name Register 0 + 0x1052 + 8 + read-write + 0 + 0xFF + + + product_name + no description available + 0 + 8 + read-write + + + + + FC_SPDDEVICEINF + Frame Composer SPD Packet Data Source Product Descriptor Register + 0x1062 + 8 + read-write + 0 + 0xFF + + + product_descriptor + no description available + 0 + 8 + read-write + + + + + FC_AUDSCONF + Frame Composer Audio Sample Flat and Layout Configuration Register + 0x1063 + 8 + read-write + 0 + 0xFF + + + aud_packet_layout + no description available + 0 + 1 + read-write + + + 1 + layout 1 + #1 + + + 0 + layout 0 + #0 + + + + + RESERVED + no description available + 1 + 3 + read-only + + + aud_packet_sampfit + no description available + 4 + 4 + read-write + + + + + FC_AUDSSTAT + Frame Composer Audio Packet Sample Present Status Register + 0x1064 + 8 + read-only + 0 + 0xFF + + + packet_sampprs + no description available + 0 + 4 + read-only + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_CTRLQHIGH + Frame Composer Number of High Priority Packets Attended Configuration Register + 0x1073 + 8 + read-write + 0xF + 0xFF + + + onhighattended + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_CTRLQLOW + Frame Composer Number of Low Priority Packets Attended Configuration Register + 0x1074 + 8 + read-write + 0x3 + 0xFF + + + onlowattended + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_ACP0 + Frame Composer ACP Packet Type Configuration Register 0 + 0x1075 + 8 + read-write + 0 + 0xFF + + + acptype + no description available + 0 + 8 + read-write + + + + + FC_ACP1 + Frame Composer ACP Packet Type Configuration Register 1 + 0x1091 + 8 + read-write + 0 + 0xFF + + + Audio_contentpacket + no description available + 0 + 8 + read-write + + + + + FC_ISCR1_0 + FC_ISCR1_Frame Composer Packet Status, Valid, and Continue Configuration Register + 0x1092 + 8 + read-write + 0 + 0xFF + + + isrc_cont + no description available + 0 + 1 + read-write + + + isrc_valid + no description available + 1 + 1 + read-write + + + isrc_status + no description available + 2 + 3 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_ISCR1_1 + Frame Composer ISCR1 Packet Body Register 1 + 0x1093 + 8 + read-write + 0 + 0xFF + + + isrc1 + no description available + 0 + 8 + read-write + + + + + FC_ISCR2_0 + Frame Composer ISCR2 Packet Body Register 0 + 0x10A3 + 8 + read-write + 0 + 0xFF + + + isrc2 + no description available + 0 + 8 + read-write + + + + + FC_DATAUTO0 + Frame Composer Data Island Auto Packet Scheduling Register 0 + 0x10B3 + 8 + read-write + 0 + 0xFF + + + acp_auto + no description available + 0 + 1 + read-write + + + iscr1_auto + no description available + 1 + 1 + read-write + + + iscr2_auto + no description available + 2 + 1 + read-write + + + vsd_auto + no description available + 3 + 1 + read-write + + + spd_auto + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_DATAUTO1 + Frame Composer Data Island Auto Packet Scheduling Register 1 + 0x10B4 + 8 + read-write + 0 + 0xFF + + + AUTO_FRAME_INTERPOLATION + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_DATAUTO2 + Frame Composer Data Island Auto Packet Scheduling Register 2 + 0x10B5 + 8 + read-write + 0 + 0xFF + + + AUTO_LINE_SPACING + no description available + 0 + 4 + read-write + + + AUTO_FRAME_PACKETS + no description available + 4 + 4 + read-write + + + + + FC_DATMAN + Frame Composer Data Island Manual Packet Request Register + 0x10B6 + 8 + read-write + 0 + 0xFF + + + acp_tx + no description available + 0 + 1 + write-only + + + isr1_tx + no description available + 1 + 1 + write-only + + + iscr2_tx + no description available + 2 + 1 + write-only + + + vsd_tx + no description available + 3 + 1 + write-only + + + spd_tx + no description available + 4 + 1 + write-only + + + null_tx + no description available + 5 + 1 + write-only + + + RESERVED + no description available + 6 + 2 + read-only + + + + + FC_DATAUTO3 + Frame Composer Data Island Auto Packet Scheduling Register 3 + 0x10B7 + 8 + read-write + 0xF + 0xFF + + + acr_auto + no description available + 0 + 1 + read-write + + + audi_auto + no description available + 1 + 1 + read-write + + + gcp_auto + no description available + 2 + 1 + read-write + + + avi_auto + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_RDRB0 + Frame Composer Round Robin ACR Packet Insertion Register 0 + 0x10B8 + 8 + read-write + 0 + 0xFF + + + ACRframeinterpolation + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_RDRB1 + Frame Composer Round Robin ACR Packet Insertion Register 1 + 0x10B9 + 8 + read-write + 0 + 0xFF + + + ACRpacketlinespacing + no description available + 0 + 4 + read-write + + + ACRpacketsinframe + no description available + 4 + 4 + read-write + + + + + FC_RDRB2 + Frame Composer Round Robin ACR Packet Insertion Register 2 + 0x10BA + 8 + read-write + 0 + 0xFF + + + AUDIframeinterpolation + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_RDRB3 + Frame Composer Round Robin ACR Packet Insertion Register 3 + 0x10BB + 8 + read-write + 0 + 0xFF + + + AUDIpacketlinespacing + no description available + 0 + 4 + read-write + + + AUDIpacketsinframe + no description available + 4 + 4 + read-write + + + + + FC_RDRB4 + Frame Composer Round Robin ACR Packet Insertion Register 4 + 0x10BC + 8 + read-write + 0 + 0xFF + + + GCPframeinterpolation + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_RDRB5 + Frame Composer Round Robin ACR Packet Insertion Register 5 + 0x10BD + 8 + read-write + 0 + 0xFF + + + GCPpacketlinespacing + no description available + 0 + 4 + read-write + + + GCPpacketsinframe + no description available + 4 + 4 + read-write + + + + + FC_RDRB6 + Frame Composer Round Robin ACR Packet Insertion Register 6 + 0x10BE + 8 + read-write + 0 + 0xFF + + + AVIframeinterpolation + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + FC_RDRB7 + Frame Composer Round Robin ACR Packet Insertion Register 7 + 0x10BF + 8 + read-write + 0 + 0xFF + + + AVIpacketlinespacing + no description available + 0 + 4 + read-write + + + AVIpacketsinframe + no description available + 4 + 4 + read-write + + + + + FC_MASK0 + Frame Composer Packet Interrupt Mask Register 0 + 0x10D2 + 8 + read-write + 0x25 + 0xFF + + + NULL + no description available + 0 + 1 + read-write + + + ACR + no description available + 1 + 1 + read-write + + + AUDS + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 2 + read-only + + + HBR + no description available + 5 + 1 + read-write + + + ACP + no description available + 6 + 1 + read-write + + + AUDI + no description available + 7 + 1 + read-write + + + + + FC_MASK1 + Frame Composer Packet Interrupt Mask Register 1 + 0x10D6 + 8 + read-write + 0 + 0xFF + + + GCP + no description available + 0 + 1 + read-write + + + AVI + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 1 + read-only + + + SPD + no description available + 3 + 1 + read-write + + + VSD + no description available + 4 + 1 + read-write + + + ISCR2 + no description available + 5 + 1 + read-write + + + ISCR1 + no description available + 6 + 1 + read-write + + + GMD + no description available + 7 + 1 + read-write + + + + + FC_PRCONF + Frame Composer Pixel Repetition Configuration Register + 0x10E0 + 8 + read-write + 0x10 + 0xFF + + + output_pr_factor + no description available + 0 + 4 + read-write + + + 0000 + No action. Shall not be used. + #0000 + + + 0001 + Pixel sent twice (pixel repeated once). + #0001 + + + 0010 + Pixel sent 3 times. + #0010 + + + 0011 + Pixel sent 4 times. + #0011 + + + 0100 + Pixel sent 5 times. + #0100 + + + 0101 + Pixel sent 6 times. + #0101 + + + 0110 + Pixel sent 7 times. + #0110 + + + 0111 + Pixel sent 8 times. + #0111 + + + 1000 + Pixel sent 9 times. + #1000 + + + 1001 + Pixel sent 10 times. + #1001 + + + + + incoming_pr_factor + no description available + 4 + 4 + read-write + + + 0000 + No action. Shall not be used. + #0000 + + + 0001 + No pixel repetition (pixel sent only once). + #0001 + + + 0010 + Pixel sent twice (pixel repeated once). + #0010 + + + 0011 + Pixel sent 3 times. + #0011 + + + 0100 + Pixel sent 4 times. + #0100 + + + 0101 + Pixel sent 5 times. + #0101 + + + 0110 + Pixel sent 6 times. + #0110 + + + 0111 + Pixel sent 7 times. + #0111 + + + 1000 + Pixel sent 8 times. + #1000 + + + 1001 + Pixel sent 9 times. + #1001 + + + 1010 + Pixel sent 10 times. + #1010 + + + + + + + FC_GMD_STAT + Frame Composer GMD Packet Status Register + 0x1100 + 8 + read-only + 0 + 0xFF + + + igmdcurrent_gamut_seq_num + no description available + 0 + 4 + read-only + + + igmdpacket_seq + no description available + 4 + 2 + read-only + + + igmddnext_field + no description available + 6 + 1 + read-only + + + igmdno_crnt_gbd + no description available + 7 + 1 + read-only + + + + + FC_GMD_EN + Frame Composer GMD Packet Enable Register + 0x1101 + 8 + read-write + 0 + 0xFF + + + gmdenabletx + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + FC_GMD_UP + Frame Composer GMD Packet Update Register + 0x1102 + 8 + read-write + 0 + 0xFF + + + gmdupdatepacket + no description available + 0 + 1 + write-only + + + RESERVED + no description available + 1 + 7 + read-only + + + + + FC_GMD_CONF + Frame Composer GMD Packet Schedule Configuration Register + 0x1103 + 8 + read-write + 0x10 + 0xFF + + + gmdpacketlinespacing + no description available + 0 + 4 + read-write + + + gmdpacketsinframe + no description available + 4 + 4 + read-write + + + + + FC_GMD_HB + Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register + 0x1104 + 8 + read-write + 0 + 0xFF + + + gmdaffected_gamut_seq_num + no description available + 0 + 4 + read-write + + + gmdgbd_profile + no description available + 4 + 3 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + FC_GMD_PB0 + Frame Composer GMD Packet Body Register 0 + 0x1105 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB0 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB1 + Frame Composer GMD Packet Body Register 1 + 0x1106 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB1 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB2 + Frame Composer GMD Packet Body Register 2 + 0x1107 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB2 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB3 + Frame Composer GMD Packet Body Register 3 + 0x1108 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB3 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB4 + Frame Composer GMD Packet Body Register 4 + 0x1109 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB4 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB5 + Frame Composer GMD Packet Body Register 5 + 0x110A + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB5 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB6 + Frame Composer GMD Packet Body Register 6 + 0x110B + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB6 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB7 + Frame Composer GMD Packet Body Register 7 + 0x110C + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB2 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB8 + Frame Composer GMD Packet Body Register 8 + 0x110D + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB8 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB9 + Frame Composer GMD Packet Body Register 9 + 0x110E + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB9 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB10 + Frame Composer GMD Packet Body Register 10 + 0x110F + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB10 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB11 + Frame Composer GMD Packet Body Register 11 + 0x1110 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB11 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB12 + Frame Composer GMD Packet Body Register 12 + 0x1111 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB12 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB13 + Frame Composer GMD Packet Body Register 13 + 0x1112 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB13 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB14 + Frame Composer GMD Packet Body Register 14 + 0x1113 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB14 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB15 + Frame Composer GMD Packet Body Register 15 + 0x1114 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB15 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB16 + Frame Composer GMD Packet Body Register 16 + 0x1115 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB16 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB17 + Frame Composer GMD Packet Body Register 17 + 0x1116 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB17 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB18 + Frame Composer GMD Packet Body Register 18 + 0x1117 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB18 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB19 + Frame Composer GMD Packet Body Register 19 + 0x1118 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB18 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB20 + Frame Composer GMD Packet Body Register 20 + 0x1119 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB20 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB21 + Frame Composer GMD Packet Body Register 21 + 0x111A + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB21 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB22 + Frame Composer GMD Packet Body Register 22 + 0x111B + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB22 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB23 + Frame Composer GMD Packet Body Register 23 + 0x111C + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB23 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB24 + Frame Composer GMD Packet Body Register 24 + 0x111D + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB24 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB25 + Frame Composer GMD Packet Body Register 25 + 0x111E + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB25 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB26 + Frame Composer GMD Packet Body Register 26 + 0x111F + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB26 + no description available + 0 + 8 + read-write + + + + + FC_GMD_PB27 + Frame Composer GMD Packet Body Register 27 + 0x1120 + 8 + read-write + 0 + 0xFF + + + FC_GMD_PB27 + no description available + 0 + 8 + read-write + + + + + FC_DBGFORCE + Frame Composer Video/Audio Force Enable Register + 0x1200 + 8 + read-write + 0 + 0xFF + + + forcevideo + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + forceaudio + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + + + FC_DBGAUD0CH0 + Frame Composer Audio Channel 0 Register 0 + 0x1201 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH0 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH0 + Frame Composer Audio Channel 0 Register 1 + 0x1202 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH0 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH0 + Frame Composer Audio Channel 0 Register 2 + 0x1203 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH0 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH1 + Frame Composer Audio Channel 1 Register 0 + 0x1204 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH1 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH1 + Frame Composer Audio Channel 1 Register 1 + 0x1205 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH1 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH1 + Frame Composer Audio Channel 1 Register 2 + 0x1206 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH1 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH2 + Frame Composer Debug Audio Channel 2 Register 0 + 0x1207 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH2 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH2 + Frame Composer Debug Audio Channel 2 Register 1 + 0x1208 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH2 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH2 + Frame Composer Audio Channel 2 Register 2 + 0x1209 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH2 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH3 + Frame Composer Audio Channel 3 Register 0 + 0x120A + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH3 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH3 + Frame Composer Audio Channel 3 Register 1 + 0x120B + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH3 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH3 + Frame Composer Audio Channel 3 Register 2 + 0x120C + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH3 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH4 + Frame Composer Audio Channel 4 Register 0 + 0x120D + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH4 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH4 + Frame Composer Audio Channel 4 Register 1 + 0x120E + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH4 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH4 + Frame Composer Audio Channel 4 Register 2 + 0x120F + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH4 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH5 + Frame Composer Audio Channel 5 Register 0 + 0x1210 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH5 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH5 + Frame Composer Audio Channel 5 Register 1 + 0x1211 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH5 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH5 + Frame Composer Audio Channel 5 Register 2 + 0x1212 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH5 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH6 + Frame Composer Audio Channel 6 Register 0 + 0x1213 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH6 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH6 + Frame Composer Audio Channel 6 Register 1 + 0x1214 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH6 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH6 + Frame Composer Audio Channel 6 Register 2 + 0x1215 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH6 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD0CH7 + Frame Composer Audio Channel 7 Register 1 + 0x1216 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD0CH7 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD1CH7 + Frame Composer Audio Channel 7 Register 0 + 0x1217 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD1CH7 + no description available + 0 + 8 + read-write + + + + + FC_DBGAUD2CH7 + Frame Composer Audio Channel 7 Register 2 + 0x1218 + 8 + read-write + 0 + 0xFF + + + FC_DBGAUD2CH7 + no description available + 0 + 8 + read-write + + + + + FC_DBGTMDS0 + Frame Composer TMDS Channel 0 Register + 0x1219 + 8 + read-write + 0 + 0xFF + + + FC_DBGTMDS0 + no description available + 0 + 8 + read-write + + + + + FC_DBGTMDS1 + Frame Composer TMDS Channel 1 Register + 0x121A + 8 + read-write + 0 + 0xFF + + + FC_DBGTMDS1 + no description available + 0 + 8 + read-write + + + + + FC_DBGTMDS2 + Frame Composer TMDS Channel 2 Register + 0x121B + 8 + read-write + 0 + 0xFF + + + FC_DBGTMDS2 + no description available + 0 + 8 + read-write + + + + + PHY_CONF0 + PHY Configuration Register + 0x3000 + 8 + read-write + 0x6 + 0xFF + + + seldipif + no description available + 0 + 1 + read-write + + + seldataenpol + no description available + 1 + 1 + read-write + + + gen2_enhpdrxsense + no description available + 2 + 1 + read-write + + + gen2_txpwron + no description available + 3 + 1 + read-write + + + gen2_pddq + no description available + 4 + 1 + read-write + + + sparectrl + no description available + 5 + 1 + read-write + + + ENTMDS + no description available + 6 + 1 + read-write + + + PDZ + no description available + 7 + 1 + read-write + + + + + PHY_TST0 + PHY Test Interface Register 0 + 0x3001 + 8 + read-write + 0 + 0xFF + + + testclk + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + testen + no description available + 4 + 1 + read-write + + + testclr + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + PHY_TST1 + PHY Test Interface Register 1 + 0x3002 + 8 + read-write + 0 + 0xFF + + + testdin + no description available + 0 + 8 + read-write + + + + + PHY_TST2 + PHY Test Interface Register 2 + 0x3003 + 8 + read-only + 0 + 0xFF + + + testdout + no description available + 0 + 8 + read-only + + + + + PHY_STAT0 + PHY RXSENSE, PLL lock, and HPD Status Register + 0x3004 + 8 + read-only + 0 + 0xFF + + + TX_PHY_LOCK + no description available + 0 + 1 + read-only + + + HPD + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + RX_SENSE0 + no description available + 4 + 1 + read-only + + + RX_SENSE1 + no description available + 5 + 1 + read-only + + + RX_SENSE2 + no description available + 6 + 1 + read-only + + + RX_SENSE3 + no description available + 7 + 1 + read-only + + + + + PHY_INT0 + PHY RXSENSE, PLL lock, and HPD Interrupt Register + 0x3005 + 8 + read-only + 0 + 0xFF + + + TX_PHY_LOCK + no description available + 0 + 1 + read-only + + + HPD + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + RX_SENSE0 + no description available + 4 + 1 + read-only + + + RX_SENSE1 + no description available + 5 + 1 + read-only + + + RX_SENSE2 + no description available + 6 + 1 + read-only + + + RX_SENSE3 + no description available + 7 + 1 + read-only + + + + + PHY_MASK0 + PHY RXSENSE, PLL lock, and HPD Mask Register + 0x3006 + 8 + read-write + 0 + 0xFF + + + TX_PHY_LOCK + no description available + 0 + 1 + read-write + + + HPD + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 2 + read-only + + + RX_SENSE0 + no description available + 4 + 1 + read-write + + + RX_SENSE1 + no description available + 5 + 1 + read-write + + + RX_SENSE2 + no description available + 6 + 1 + read-write + + + RX_SENSE3 + no description available + 7 + 1 + read-write + + + + + PHY_POL0 + PHY RXSENSE, PLL lock and HPD Polarity Register + 0x3007 + 8 + read-write + 0xF3 + 0xFF + + + TX_PHY_LOCK + no description available + 0 + 1 + read-write + + + HPD + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 2 + read-only + + + RX_SENSE0 + no description available + 4 + 1 + read-write + + + RX_SENSE1 + no description available + 5 + 1 + read-write + + + RX_SENSE2 + no description available + 6 + 1 + read-write + + + RX_SENSE3 + no description available + 7 + 1 + read-write + + + + + PHY_I2CM_SLAVE_ADDR + PHY I2C Slave Address Configuration Register + 0x3020 + 8 + read-write + 0 + 0xFF + + + RESERVED + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + PHY_I2CM_ADDRESS_ADDR + PHY I2C Address Configuration Register + 0x3021 + 8 + read-write + 0 + 0xFF + + + address + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_DATAO_1_ADDR + PHY I2C Data Write Register 1 + 0x3022 + 8 + read-write + 0 + 0xFF + + + datao + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_DATAO_0_ADDR + PHY I2C Data Write Register 0 + 0x3023 + 8 + read-write + 0 + 0xFF + + + datao + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_DATAI_1_ADDR + PHY I2C Data Read Register 1 + 0x3024 + 8 + read-only + 0 + 0xFF + + + datai + no description available + 0 + 8 + read-only + + + + + PHY_I2CM_DATAI_0_ADDR + PHY I2C Data Read Register 0 + 0x3025 + 8 + read-write + 0 + 0xFF + + + datai + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_OPERATION_ADDR + PHY I2C Read/Write Operation + 0x3026 + 8 + read-write + 0 + 0xFF + + + read + no description available + 0 + 1 + write-only + + + RESERVED + no description available + 1 + 3 + read-only + + + write + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 3 + read-only + + + + + PHY_I2CM_INT_ADDR + PHY I2C Done Interrupt Register + 0x3027 + 8 + read-write + 0x8 + 0xFF + + + done_status + no description available + 0 + 1 + read-write + + + done_interrupt + no description available + 1 + 1 + read-write + + + done_mask + no description available + 2 + 1 + read-write + + + done_pol + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + PHY_I2CM_CTLINT_ADDR + PHY I2C Done Interrupt Register + 0x3028 + 8 + read-write + 0x88 + 0xFF + + + arbitration_status + no description available + 0 + 1 + read-write + + + arbitration_interrupt + no description available + 1 + 1 + read-write + + + arbitration_mask + no description available + 2 + 1 + read-write + + + arbitration_pol + no description available + 3 + 1 + read-write + + + nack_status + no description available + 4 + 1 + read-write + + + nack_interrupt + no description available + 5 + 1 + read-write + + + nack_mask + no description available + 6 + 1 + read-write + + + nack_pol + no description available + 7 + 1 + read-write + + + + + PHY_I2CM_DIV_ADDR + PHY I2C Speed Control Register + 0x3029 + 8 + read-write + 0xB + 0xFF + + + fast_mode + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + PHY_I2CM_SOFTRSTZ_ADDR + PHY I2C Software Reset Register + 0x302A + 8 + read-write + 0x1 + 0xFF + + + i2c_softrst + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + PHY_I2CM_SS_SCL_HCNT_1_ADDR + PHY I2C Slow Speed SCL High Level Control Register 1 + 0x302B + 8 + read-write + 0 + 0xFF + + + i2cmp_ss_scl_hcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_SS_SCL_HCNT_0_ADDR + PHY I2C Slow Speed SCL High Level Control Register 0 + 0x302C + 8 + read-write + 0x6C + 0xFF + + + i2cmp_ss_scl_hcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_SS_SCL_LCNT_1_ADDR + PHY I2C Slow Speed SCL Low Level Control Register 1 + 0x302D + 8 + read-write + 0 + 0xFF + + + i2cmp_ss_scl_lcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_SS_SCL_LCNT_0_ADDR + PHY I2C Slow Speed SCL Low Level Control Register 0 + 0x302E + 8 + read-write + 0x7F + 0xFF + + + i2cmp_ss_scl_lcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_FS_SCL_HCNT_1_ADDR + PHY I2C Fast Speed SCL High Level Control Register 1 + 0x302F + 8 + read-write + 0 + 0xFF + + + i2cmp_fs_scl_hcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_FS_SCL_HCNT_0_ADDR + PHY I2C Fast Speed SCL High Level Control Register 0 + 0x3030 + 8 + read-write + 0x11 + 0xFF + + + i2cmp_fs_scl_hcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_FS_SCL_LCNT_1_ADDR + PHY I2C Fast Speed SCL Low Level Control Register 1 + 0x3031 + 8 + read-write + 0 + 0xFF + + + i2cmp_fs_scl_lcnt + no description available + 0 + 8 + read-write + + + + + PHY_I2CM_FS_SCL_LCNT_0_ADDR + PHY I2C Fast Speed SCL Low Level Control Register 0 + 0x3032 + 8 + read-write + 0x24 + 0xFF + + + i2cmp_fs_scl_lcnt + no description available + 0 + 8 + read-write + + + + + AUD_N1 + Audio Clock Regenerator N Value Register 1 + 0x3200 + 8 + read-write + 0 + 0xFF + + + AudN + no description available + 0 + 8 + read-write + + + + + AUD_N2 + Audio Clock Regenerator N Value Register 2 + 0x3201 + 8 + read-write + 0 + 0xFF + + + AudN + no description available + 0 + 8 + read-write + + + + + AUD_N3 + Audio Clock Regenerator N Value Register 3 + 0x3202 + 8 + read-write + 0 + 0xFF + + + AudN + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + AUD_CTS1 + AUD_CTS1 + 0x3203 + 8 + read-write + 0 + 0xFF + + + audCTS + no description available + 0 + 8 + read-write + + + + + AUD_CTS2 + AUD_CTS2 + 0x3204 + 8 + read-write + 0 + 0xFF + + + audCTS + no description available + 0 + 8 + read-write + + + + + AUD_CTS3 + AUD_CTS3 + 0x3205 + 8 + read-write + 0 + 0xFF + + + audCTS + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + AHB_DMA_CONF0 + Audio DMA Start Register + 0x3600 + 8 + read-write + 0 + 0xFF + + + burst_mode + no description available + 0 + 1 + read-write + + + 1 + Forces the burst mode to be fixed beat incremental burst mode designated by the incr_type[1:0] signal. + #1 + + + 0 + Normal operation is unspecified length incremental burst. It corresponds to INCR AHB burst mode. + #0 + + + + + incr_type + no description available + 1 + 2 + read-write + + + 00 + Corresponds to INCR4 fixed four beat incremental AHB burst mode. Only valid when burst_mode is high. + #00 + + + 01 + Corresponds to INCR8 fixed eight beat incremental AHB burst mode. Only valid when burst_mode is high. + #01 + + + 10 + Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only valid when burst_mode is high. + #10 + + + 11 + Corresponds to INCR16 fixed 16 beat incremental AHB burst mode. Only valid when burst_mode is high. + #11 + + + + + enable_hlock + no description available + 3 + 1 + read-write + + + 1 + Enables the usage of ohlock for master request to arbiter of a locked complete burst.\ + #1 + + + 0 + Disables request of locked burst AHB mechanism + #0 + + + + + hbr + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 2 + read-only + + + sw_fifo_rst + no description available + 7 + 1 + read-write + + + + + AHB_DMA_START + AHB_DMA_START + 0x3601 + 8 + read-write + 0 + 0xFF + + + data_buffer_ready + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + AHB_DMA_STOP + Audio DMA Stop Register + 0x3602 + 8 + read-write + 0 + 0xFF + + + stop_dma_transaction + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + AHB_DMA_THRSLD + Audio DMA FIFO Threshold Register + 0x3603 + 8 + read-write + 0 + 0xFF + + + fifo_threshold + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STRADDR0 + Audio DMA Start Address Register 0 + 0x3604 + 8 + read-write + 0 + 0xFF + + + initial_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STRADDR1 + Audio DMA Start Address Register 1 + 0x3605 + 8 + read-write + 0 + 0xFF + + + initial_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STRADDR2 + Audio DMA Start Address Register 2 + 0x3606 + 8 + read-write + 0 + 0xFF + + + initial_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STRADDR3 + Audio DMA Start Address Register 3 + 0x3607 + 8 + read-write + 0 + 0xFF + + + initial_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STPADDR0 + Audio DMA Stop Address Register 0 + 0x3608 + 8 + read-write + 0 + 0xFF + + + final_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STPADDR1 + Audio DMA Stop Address Register 1 + 0x3609 + 8 + read-write + 0 + 0xFF + + + final_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STPADDR2 + Audio DMA Stop Address Register 2 + 0x360A + 8 + read-write + 0 + 0xFF + + + final_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_STPADDR3 + Audio DMA Stop Address Register 3 + 0x360B + 8 + read-write + 0 + 0xFF + + + final_addr + no description available + 0 + 8 + read-write + + + + + AHB_DMA_BSTADDR0 + Audio DMA Burst Start Address Register 0 + 0x360C + 8 + read-only + 0 + 0xFF + + + burst_start + no description available + 0 + 8 + read-only + + + + + AHB_DMA_BSTADDR1 + Audio DMA Burst Start Address Register 1 + 0x360D + 8 + read-only + 0 + 0xFF + + + burst_start + no description available + 0 + 8 + read-only + + + + + AHB_DMA_BSTADDR2 + Audio DMA Burst Start Address Register 2 + 0x360E + 8 + read-only + 0 + 0xFF + + + burst_start + no description available + 0 + 8 + read-only + + + + + AHB_DMA_BSTADDR3 + Audio DMA Burst Start Address Register 3 + 0x360F + 8 + read-only + 0 + 0xFF + + + burst_start + no description available + 0 + 8 + read-only + + + + + AHB_DMA_MBLENGTH0 + Audio DMA Burst Length Register 0 + 0x3610 + 8 + read-only + 0 + 0xFF + + + MBURSTLENGTH7 + no description available + 0 + 8 + read-only + + + + + AHB_DMA_MBLENGTH1 + Audio DMA Burst Length Register 1 + 0x3611 + 8 + read-only + 0 + 0xFF + + + MBURSTLENGTH8 + no description available + 0 + 1 + read-only + + + MBURSTLENGTH9 + no description available + 1 + 1 + read-only + + + MBURSTLENGTH10 + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 5 + read-only + + + + + AHB_DMA_STAT + Audio DMA Interrupt Status Register + 0x3612 + 8 + read-only + 0 + 0xFF + + + statfifoempty + no description available + 0 + 1 + read-only + + + statfifofull + no description available + 1 + 1 + read-only + + + statthrfifoempty + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 1 + read-only + + + staterror + no description available + 4 + 1 + read-only + + + statlostownership + no description available + 5 + 1 + read-only + + + statretrysplit + no description available + 6 + 1 + read-only + + + statdone + no description available + 7 + 1 + read-only + + + + + AHB_DMA_INT + Audio DMA Interrupt Register + 0x3613 + 8 + read-only + 0 + 0xFF + + + intfifoempty + no description available + 0 + 1 + read-only + + + intfifofull + no description available + 1 + 1 + read-only + + + intthrfifoempty + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 1 + read-only + + + interror + no description available + 4 + 1 + read-only + + + intlostownership + no description available + 5 + 1 + read-only + + + intretrysplit + no description available + 6 + 1 + read-only + + + intdone + no description available + 7 + 1 + read-only + + + + + AHB_DMA_MASK + Audio DMA Mask Interrupt Register + 0x3614 + 8 + read-write + 0 + 0xFF + + + fifo_empty_mask + no description available + 0 + 1 + read-write + + + fifo_full_mask + no description available + 1 + 1 + read-write + + + fifo_thrempty_mask + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 1 + read-only + + + error_mask + no description available + 4 + 1 + read-write + + + lostownership_mask + no description available + 5 + 1 + read-write + + + retrysplit_mask + no description available + 6 + 1 + read-write + + + done_mask + no description available + 7 + 1 + read-write + + + + + AHB_DMA_POL + Audio DMA Polarity Interrupt Register + 0x3615 + 8 + read-write + 0 + 0xFF + + + fifo_empty_polarity + no description available + 0 + 1 + read-write + + + fifo_full_polarity + no description available + 1 + 1 + read-write + + + fifo_thrfifoempty_polarity + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 1 + read-only + + + error_polarity + no description available + 4 + 1 + read-write + + + lostownership_polarity + no description available + 5 + 1 + read-write + + + retrysplit_polarity + no description available + 6 + 1 + read-write + + + done_polarity + no description available + 7 + 1 + read-write + + + + + AHB_DMA_CONF1 + Audio DMA Channel Enable Configuration Register 1 + 0x3616 + 8 + read-write + 0 + 0xFF + + + CH_IN_EN0 + no description available + 0 + 1 + read-write + + + CH_IN_EN1 + no description available + 1 + 1 + read-write + + + CH_IN_EN2 + no description available + 2 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + CH_IN_EN3 + no description available + 3 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + CH_IN_EN4 + no description available + 4 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + CH_IN_EN5 + no description available + 5 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + CH_IN_EN6 + no description available + 6 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + CH_IN_EN7 + no description available + 7 + 1 + read-write + + + 1 + Channel enabled + #1 + + + 0 + Channel disabled + #0 + + + + + + + AHB_DMA_BUFFSTAT + Audio DMA Buffer Interrupt Status Register + 0x3617 + 8 + read-only + 0 + 0xFF + + + buff_empty + no description available + 0 + 1 + read-only + + + buff_full + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 6 + read-only + + + + + AHB_DMA_BUFFINT + Audio DMA Buffer Interrupt Register + 0x3618 + 8 + read-only + 0 + 0xFF + + + int_buff_empty + no description available + 0 + 1 + read-only + + + int_buff_full + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 6 + read-only + + + + + AHB_DMA_BUFFMASK + Audio DMA Buffer Mask Interrupt Register + 0x3619 + 8 + read-write + 0 + 0xFF + + + int_buff_empty + no description available + 0 + 1 + read-write + + + int_buff_full + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + AHB_DMA_BUFFPOL + Audio DMA Buffer Polarity Interrupt Register + 0x361A + 8 + read-write + 0 + 0xFF + + + int_buff_empty + no description available + 0 + 1 + read-write + + + int_buff_full + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 6 + read-only + + + + + MC_CLKDIS + Main Controller Synchronous Clock Domain Disable Register + 0x4001 + 8 + read-write + 0 + 0xFF + + + pixelclk_disable + no description available + 0 + 1 + read-write + + + tmdsclk_disable + no description available + 1 + 1 + read-write + + + prepclk_disable + no description available + 2 + 1 + read-write + + + audclk_disable + no description available + 3 + 1 + read-write + + + cscclk_disable + no description available + 4 + 1 + read-write + + + cecclk_disable + no description available + 5 + 1 + read-write + + + hdcpclk_disable + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + + + MC_SWRSTZREQ + Main Controller Software Reset Register + 0x4002 + 8 + read-write + 0xFF + 0xFF + + + pixelswrst_req + no description available + 0 + 1 + read-write + + + tmdsswrst_req + no description available + 1 + 1 + read-write + + + prepswrst_req + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 3 + read-only + + + cecswrst_req + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + MC_FLOWCTRL + Main Controller Feed Through Control Register + 0x4004 + 8 + read-write + 0 + 0xFF + + + Feed_through_off + no description available + 0 + 1 + read-write + + + 1 + Color Space Converter is in the video data path. + #1 + + + 0 + Color Space Converter is bypassed (not in the video data path). + #0 + + + + + RESERVED + no description available + 1 + 7 + read-only + + + + + MC_PHYRSTZ + Main Controller PHY Reset Register + 0x4005 + 8 + read-write + 0 + 0xFF + + + phyrstz + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + MC_LOCKONCLOCK + Main Controller Clock Present Register + 0x4006 + 8 + read-write + 0 + 0xFF + + + cecclk + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + prepclk + no description available + 4 + 1 + read-write + + + tclktclk + no description available + 5 + 1 + read-write + + + pclk + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + MC_HEACPHY_RST + Main Controller HEAC PHY Reset Register + 0x4007 + 8 + read-write + 0 + 0xFF + + + heacphyrst + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + CSC_CFG + Color Space Converter Interpolation and Decimation Configuration Register + 0x4100 + 8 + read-write + 0 + 0xFF + + + DECMODE + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 2 + read-only + + + INTMODE + no description available + 4 + 2 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + + + CSC_SCALE + Color Space Converter Scale and Deep Color Configuration Register + 0x4101 + 8 + read-write + 0x1 + 0xFF + + + RESERVED + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 2 + read-only + + + csc_colorde_pth + no description available + 4 + 4 + read-write + + + 0000 + 24 bit per pixel video (8 bit per component). + #0000 + + + 0100 + 24 bit per pixel video (8 bit per component). + #0100 + + + 0101 + 30 bit per pixel video (10 bit per component). + #0101 + + + 0110 + 36 bit per pixel video (12 bit per component). + #0110 + + + 0111 + 48 bit per pixel video (16 bit per component). + #0111 + + + + + + + CSC_COEF_A1_MSB + CSC_COEF_A1_MSB + 0x4102 + 8 + read-write + 0x20 + 0xFF + + + CSC_COEF_A1_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A1_LSB + CSC_COEF_A1_LSB + 0x4103 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A1_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A2_MSB + CSC_COEF_A2_MSB + 0x4104 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A2_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A2_LSB + CSC_COEF_A2_LSB + 0x4105 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A2_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A3_MSB + CSC_COEF_A3_MSB + 0x4106 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A3_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A3_LSB + CSC_COEF_A3_LSB + 0x4107 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A3_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A4_MSB + CSC_COEF_A4_MSB + 0x4108 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A4_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_A4_LSB + CSC_COEF_A4_LSB + 0x4109 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_A4_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B1_MSB + CSC_COEF_B1_MSB + 0x410A + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B1_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B1_LSB + CSC_COEF_B1_LSB + 0x410B + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B1_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B2_MSB + CSC_COEF_B2_MSB + 0x410C + 8 + read-write + 0x20 + 0xFF + + + CSC_COEF_B2_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B2_LSB + CSC_COEF_B2_LSB + 0x410D + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B2_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B3_MSB + CSC_COEF_B3_MSB + 0x410E + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B3_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B3_LSB + CSC_COEF_B3_LSB + 0x410F + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B3_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B4_MSB + CSC_COEF_B4_MSB + 0x4110 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B4_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_B4_LSB + CSC_COEF_B4_LSB + 0x4111 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_B4_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C1_MSB + CSC_COEF_C1_MSB + 0x4112 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_C1_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C1_LSB + CSC_COEF_C1_LSB + 0x4113 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_C1_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C2_MSB + CSC_COEF_C2_MSB + 0x4114 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_C2_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C2_LSB + CSC_COEF_C2_LSB + 0x4115 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_C2_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C3_MSB + CSC_COEF_C3_MSB + 0x4116 + 8 + read-write + 0x20 + 0xFF + + + CSC_COEF_C3_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEF_C3_LSB + CSC_COEF_C3_LSB + 0x4117 + 8 + read-write + 0 + 0xFF + + + CSC_COEF_C3_LSB + no description available + 0 + 8 + read-write + + + + + CSC_COEFC4_MSB + CSC_COEFC4_MSB + 0x4118 + 8 + read-write + 0 + 0xFF + + + CSC_COEFC4_MSB + no description available + 0 + 8 + read-write + + + + + CSC_COEFC4_LSB + CSC_COEFC4_LSB + 0x4119 + 8 + read-write + 0 + 0xFF + + + CSC_COEFC4_LSB + no description available + 0 + 8 + read-write + + + + + CEC_CTRL + CEC_CTRL + 0x7D00 + 8 + read-write + 0x2 + 0xFF + + + SEND + no description available + 0 + 1 + read-write + + + 0 + Reset to 0 by hardware when the CEC transmission is done (no matter successful or failed). It can also work as an indicator checked by software to see whether the transmission is finished. + #0 + + + 1 + Set by software to trigger CEC sending a frame as an initiator. This bit keeps at 1 while the transmission is going on. + #1 + + + + + FRAME_TYP + no description available + 1 + 2 + read-write + + + 00 + Signal Free Time = 3-bit periods. Previous attempt to send frame is unsuccessful. + #00 + + + 01 + Signal Free Time = 5-bit periods. New initiator wants to send a frame. + #01 + + + 10 + Signal Free Time = 7-bit periods. Present initiator wants to send another frame immediately after its previous frame. (spec CEC 9.1) + #10 + + + 11 + Illegal value. If software write this value, hardware will set the value to the default 2'b01. + #11 + + + + + BC_NACK + no description available + 3 + 1 + read-write + + + 0 + Reset by software to ACK the received broadcast message. + #0 + + + 1 + Set by software to NACK the received broadcast message. This bit holds till software resets. The broadcasts will be answered with 1'b0. It means the follower reject the message. + #1 + + + + + STANDBY + no description available + 4 + 1 + read-write + + + 0 + CEC controller responds the ACK to all messages. + #0 + + + 1 + CEC controller responds with ACK to all ping messages (only when the EOM is received) and responds with NACK to all other messages, generating wake-up status for selected opcodes. Attention that the NACK will only be posted on the last block of a frame. + #1 + + + + + RESERVED + no description available + 5 + 3 + read-only + + + + + CEC_MASK + CEC_MASK + 0x7D02 + 8 + read-write + 0 + 0xFF + + + DONE_MASK + no description available + 0 + 1 + read-write + + + EOM_MASK + no description available + 1 + 1 + read-write + + + NACK_MASK + no description available + 2 + 1 + read-write + + + ARB_LOST_MASK + no description available + 3 + 1 + read-write + + + ERROR_INIT_MASK + no description available + 4 + 1 + read-write + + + ERROR_FOLL_MASK + no description available + 5 + 1 + read-write + + + WAKEUP_MASK + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + CEC_ADDR_L + CEC_ADDR_L + 0x7D05 + 8 + read-write + 0 + 0xFF + + + CEC_ADDR_L0 + no description available + 0 + 1 + read-write + + + CEC_ADDR_L1 + no description available + 1 + 1 + read-write + + + CEC_ADDR_L2 + no description available + 2 + 1 + read-write + + + CEC_ADDR_L3 + no description available + 3 + 1 + read-write + + + CEC_ADDR_L4 + no description available + 4 + 1 + read-write + + + CEC_ADDR_L5 + no description available + 5 + 1 + read-write + + + CEC_ADDR_L6 + no description available + 6 + 1 + read-write + + + CEC_ADDR_L7 + no description available + 7 + 1 + read-write + + + + + CEC_ADDR_H + CEC_ADDR_H + 0x7D06 + 8 + read-write + 0x80 + 0xFF + + + CEC_ADDR_H0 + no description available + 0 + 1 + read-write + + + CEC_ADDR_H1 + no description available + 1 + 1 + read-write + + + CCEC_ADDR_H2 + no description available + 2 + 1 + read-write + + + CEC_ADDR_H3 + no description available + 3 + 1 + read-write + + + CEC_ADDR_H4 + no description available + 4 + 1 + read-write + + + CEC_ADDR_H5 + no description available + 5 + 1 + read-write + + + CEC_ADDR_H6 + no description available + 6 + 1 + read-write + + + CEC_ADDR_H7 + no description available + 7 + 1 + read-write + + + + + CEC_TX_CNT + CEC_TX_CNT + 0x7D07 + 8 + read-write + 0 + 0xFF + + + CEC_TX_CNT + no description available + 0 + 5 + read-write + + + 0 + No data needs to be transmitted. + #0 + + + 1 + Frame size is 1 byte. + #1 + + + + + RESERVED + no description available + 5 + 3 + read-only + + + + + CEC_RX_CNT + CEC_RX_CNT + 0x7D08 + 8 + read-only + 0 + 0xFF + + + CEC_RX_CNT + no description available + 0 + 5 + read-only + + + 0 + No data received + #0 + + + 1 + 1-byte data is received. + #1 + + + + + RESERVED + no description available + 5 + 3 + read-only + + + + + 16 + 0x1 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CEC_TX_DATA%s + CEC_TX_DATA + 0x7D10 + 8 + read-write + 0 + 0xFF + + + CEC_TX_DATA + no description available + 0 + 8 + read-write + + + + + 16 + 0x1 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + CEC_RX_DATA%s + CEC_RX_DATA + 0x7D20 + 8 + read-only + 0 + 0xFF + + + CEC_RX_DATA + no description available + 0 + 8 + read-only + + + + + CEC_LOCK + CEC_LOCK + 0x7D30 + 8 + read-write + 0 + 0xFF + + + LOCKED_BUFFER + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + CEC_WKUPCTRL + CEC_WKUPCTRL + 0x7D31 + 8 + read-write + 0xFF + 0xFF + + + OPCODE0x04en + no description available + 0 + 1 + read-write + + + OPCODE0x0Den + no description available + 1 + 1 + read-write + + + OPCODE0x41en + no description available + 2 + 1 + read-write + + + OPCODE0x42en + no description available + 3 + 1 + read-write + + + OPCODE0x44en + no description available + 4 + 1 + read-write + + + OPCODE0x70en + no description available + 5 + 1 + read-write + + + OPCODE0x82en + no description available + 6 + 1 + read-write + + + OPCODE0x86en + no description available + 7 + 1 + read-write + + + + + I2CM_SLAVE + I2CM_SLAVE + 0x7E00 + 8 + read-write + 0 + 0xFF + + + slaveaddr + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + I2CM_ADDRESS + I2CM_ADDRESS + 0x7E01 + 8 + read-write + 0 + 0xFF + + + address + no description available + 0 + 8 + read-write + + + + + I2CM_DATAO + I2CM_DATAO + 0x7E02 + 8 + read-write + 0 + 0xFF + + + datao + no description available + 0 + 8 + read-write + + + + + I2CM_DATAI + I2CM_DATAI + 0x7E03 + 8 + read-only + 0 + 0xFF + + + datai + no description available + 0 + 8 + read-only + + + + + I2CM_OPERATION + I2CM_OPERATION + 0x7E04 + 8 + read-write + 0 + 0xFF + + + rd + no description available + 0 + 1 + write-only + + + rd_ext + no description available + 1 + 1 + write-only + + + RESERVED + no description available + 2 + 2 + read-only + + + wr + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 3 + read-only + + + + + I2CM_INT + I2CM_INT + 0x7E05 + 8 + read-write + 0x8 + 0xFF + + + done_status + no description available + 0 + 1 + read-write + + + done_interrupt + no description available + 1 + 1 + read-write + + + done_mask + no description available + 2 + 1 + read-write + + + done_pol + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + + + I2CM_CTLINT + I2CM_CTLINT + 0x7E06 + 8 + read-write + 0x88 + 0xFF + + + arbitration_status + no description available + 0 + 1 + read-write + + + arbitration_interrupt + no description available + 1 + 1 + read-write + + + arbitration_mask + no description available + 2 + 1 + read-write + + + arbitration_pol + no description available + 3 + 1 + read-write + + + nack_status + no description available + 4 + 1 + read-write + + + nack_interrupt + no description available + 5 + 1 + read-write + + + nack_mask + no description available + 6 + 1 + read-write + + + nack_pol + no description available + 7 + 1 + read-write + + + + + I2CM_DIV + I2CM_DIV + 0x7E07 + 8 + read-write + 0xB + 0xFF + + + RESERVED + no description available + 0 + 3 + read-only + + + fast_std_mode + no description available + 3 + 1 + read-write + + + 1 + Fast Mode + #1 + + + 0 + Standard Mode + #0 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + + + I2CM_SEGADDR + I2CM_SEGADDR + 0x7E08 + 8 + read-write + 0 + 0xFF + + + SEGADDR + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + + + I2CM_SOFTRSTZ + I2CM_SOFTRSTZ + 0x7E09 + 8 + read-write + 0x1 + 0xFF + + + i2c_softrst + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 7 + read-only + + + + + I2CM_SEGPTR + I2CM_SEGPTR + 0x7E0A + 8 + read-write + 0 + 0xFF + + + I2CM_SEGPTR + no description available + 0 + 8 + read-write + + + + + I2CM_SS_SCL_HCNT_1_ADDR + I2CM_SS_SCL_HCNT_1_ADDR + 0x7E0B + 8 + read-write + 0 + 0xFF + + + i2cmp_ss_scl_hcnt + no description available + 0 + 8 + read-write + + + + + I2CM_SS_SCL_HCNT_0_ADDR + I2CM_SS_SCL_HCNT_0_ADDR + 0x7E0C + 8 + read-write + 0x6C + 0xFF + + + i2cmp_ss_scl_hcnt + no description available + 0 + 8 + read-write + + + + + I2CM_SS_SCL_LCNT_1_ADDR + I2CM_SS_SCL_LCNT_1_ADDR + 0x7E0D + 8 + read-write + 0 + 0xFF + + + i2cmp_ss_scl_lcnt + no description available + 0 + 8 + read-write + + + + + I2CM_SS_SCL_LCNT_0_ADDR + I2CM_SS_SCL_LCNT_0_ADDR + 0x7E0E + 8 + read-write + 0x7F + 0xFF + + + i2cmp_ss_scl_lcnt + no description available + 0 + 8 + read-write + + + + + I2CM_FS_SCL_HCNT_1_ADDR + I2CM_FS_SCL_HCNT_1_ADDR + 0x7E0F + 8 + read-write + 0 + 0xFF + + + i2cmp_fs_scl_hcnt + no description available + 0 + 8 + read-write + + + + + I2CM_FS_SCL_HCNT_0_ADDR + I2CM_FS_SCL_HCNT_0_ADDR + 0x7E10 + 8 + read-write + 0x11 + 0xFF + + + i2cmp_fs_scl_hcnt + no description available + 0 + 8 + read-write + + + + + I2CM_FS_SCL_LCNT_1_ADDR + I2CM_FS_SCL_LCNT_1_ADDR + 0x7E11 + 8 + read-write + 0 + 0xFF + + + i2cmp_fs_scl_lcnt + no description available + 0 + 8 + read-write + + + + + I2CM_FS_SCL_LCNT_0_ADDR + I2CM_FS_SCL_LCNT_0_ADDR + 0x7E12 + 8 + read-write + 0x24 + 0xFF + + + i2cmp_fs_scl_lcnt + no description available + 0 + 8 + read-write + + + + + BASE_POINTER_ADDR + BASE_POINTER_ADDR + 0x7F00 + 8 + read-write + 0 + 0xFF + + + base_pointer_base_addr + no description available + 0 + 7 + read-write + + + en_base_pointer_addr + no description available + 7 + 1 + read-write + + + + + + + GPU3D + GPU3D + GPU3D_ + 0x130000 + + 0 + 0x84 + registers + + + + AQH_CLK_CTRL + AQHiClockControl + 0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CLK3D_DIS + no description available + 0 + 1 + read-write + + + CLK2D_DIS + no description available + 1 + 1 + read-write + + + FSCALE_VAL + no description available + 2 + 7 + read-write + + + FSCALE_CMD_LOAD + no description available + 9 + 1 + read-write + + + DISABLE_RAM_CLOCK_GATING + no description available + 10 + 1 + read-write + + + DISABLE_DEBUG_REGISTERS + no description available + 11 + 1 + read-write + + + SOFT_RESET + no description available + 12 + 1 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + IDLE3_D + no description available + 16 + 1 + read-write + + + IDLE2_D + no description available + 17 + 1 + read-write + + + IDLE_VG + no description available + 18 + 1 + read-write + + + ISOLATE_GPU + no description available + 19 + 1 + read-write + + + MULTI_PIPE_REG_SELECT + no description available + 20 + 4 + read-write + + + MULTI_PIPE_USE_SINGLE_AXI + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + AQH_IDLE + AQHIdle + 0x4 + 32 + read-only + 0x7FFFFFFF + 0xFFFFFFFF + + + IDLE_FE + no description available + 0 + 1 + read-only + + + IDLE_DE + no description available + 1 + 1 + read-only + + + IDLE_PE + no description available + 2 + 1 + read-only + + + IDLE_SH + no description available + 3 + 1 + read-only + + + IDLE_PA + no description available + 4 + 1 + read-only + + + IDLE_SE + no description available + 5 + 1 + read-only + + + IDLE_RA + no description available + 6 + 1 + read-only + + + IDLE_TX + no description available + 7 + 1 + read-only + + + IDLE_VG + no description available + 8 + 1 + read-only + + + IDLE_IM + no description available + 9 + 1 + read-only + + + IDLE_FP + no description available + 10 + 1 + read-only + + + IDLE_TS + no description available + 11 + 1 + read-only + + + RESERVED + no description available + 12 + 19 + read-only + + + AXI_LP + no description available + 31 + 1 + read-only + + + + + AQA_CFG + AQAxiConfig + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + AWID + no description available + 0 + 4 + read-write + + + ARID + no description available + 4 + 4 + read-write + + + AWCACHE + no description available + 8 + 4 + read-write + + + ARCACHE + no description available + 12 + 4 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + AQA_STATUS + AQAxiStatus + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_ERR_ID + no description available + 0 + 4 + read-only + + + RD_ERR_ID + no description available + 4 + 4 + read-only + + + DET_WR_ERR + no description available + 8 + 1 + read-only + + + DET_RD_ERR + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 22 + read-only + + + + + AQI_ACK + AQIntrAcknowledge + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTR_VEC + no description available + 0 + 32 + read-only + + + + + AQI_ENBL + AQIntrEnbl + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTR_ENBL_VEC + no description available + 0 + 32 + read-write + + + + + AQIDENT + AQIdent + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CUSTOMER + no description available + 0 + 8 + read-only + + + TECHNOLOGY + no description available + 8 + 4 + read-only + + + REVISION + no description available + 12 + 4 + read-only + + + PRODUCT + no description available + 16 + 8 + read-only + + + FAMILY + no description available + 24 + 8 + read-only + + + + + GC_FEAT + GCFeatures + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FAST_CLEAR + no description available + 0 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + SPECIAL_ANTI_ALIASING + no description available + 1 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + PIPE_3D + no description available + 2 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + DXT_TEXTURE_COMPRESSION + no description available + 3 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + DEBUG_MODE + no description available + 4 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + ZCOMPRESSION + no description available + 5 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + YUV420_FILTER + no description available + 6 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + MSAA + no description available + 7 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + DC + no description available + 8 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + + PIPE_2D + no description available + 9 + 1 + read-only + + + 0 + =>NONE + #0 + + + 1 + =>AVAILABLE + #1 + + + + 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General Purpose Register 2 + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 32 + read-write + + + + + AxiControl + AXI Control Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + WR_FULL_BURST_MODE + no description available + 0 + 32 + read-write + + + 0 + NO_BURST_RESET_VALUE + #0 + + + 1 + BURST_RESET_VALUE + #1 + + + + + + + MinorFeatures1 + Minor Features Register 1 + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 26 + read-only + + + TEXTURE_STRIDE + no description available + 26 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + BUG_FIXES2 + no description available + 27 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + BUG_FIXES1 + no description available + 28 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + VG_DOUBLE_BUFFER + no description available + 29 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + V2_COMPRESSION + no description available + 30 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + RSUV_SWIZZLE + no description available + 31 + 1 + read-only + + + 0 + NONE + #0 + + + 1 + AVAILABLE + #1 + + + + + + + TotalCycles + Total Cycle Counter Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + CYCLES + no description available + 0 + 32 + read-write + + + + + TotalIdleCyles + Total Idle Cycle Register + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + CYCLES + no description available + 0 + 32 + read-write + + + + + ChipSpecs2 + Chip Specification Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CYCLES + no description available + 0 + 32 + read-write + + + + + ModulePowerControls + Power Control Register + 0x84 + 32 + read-write + 0x140020 + 0xFFFFFFFF + + + TURN_OFF_COUNTER + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + TURN_ON_COUNTER + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 1 + read-only + + + DISABLE_STARVE_MODULE_CLOCK_GATING + no description available + 29 + 1 + read-write + + + DISABLE_STALL_MODULE_CLOCK_GATING + no description available + 30 + 1 + read-write + + + ENABLE_MODULE_CLOCK_GATING + no description available + 31 + 1 + read-write + + + + + ModulePowerModuleControl + Power Level Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 20 + read-only + + + DISABLE_MODULE_CLOCK_GATING_TS + no description available + 20 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_FP + no description available + 21 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_IM + no description available + 22 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_VG + no description available + 23 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_TX + no description available + 24 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_RA + no description available + 25 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_SE + no description available + 26 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_PA + no description available + 27 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_SH + no description available + 28 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_PE + no description available + 29 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_DE + no description available + 30 + 1 + read-write + + + DISABLE_MODULE_CLOCK_GATING_FE + no description available + 31 + 1 + read-write + + + + + ModulePowerModuleStatus + Power Status Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 20 + read-only + + + MODULE_CLOCK_GATED_TS + no description available + 20 + 1 + read-only + + + MODULE_CLOCK_GATED_FP + no description available + 21 + 1 + read-only + + + MODULE_CLOCK_GATED_IM + no description available + 22 + 1 + read-only + + + MODULE_CLOCK_GATED_VG + no description available + 23 + 1 + read-only + + + MODULE_CLOCK_GATED_TX + no description available + 24 + 1 + read-only + + + MODULE_CLOCK_GATED_RA + no description available + 25 + 1 + read-only + + + MODULE_CLOCK_GATED_SE + no description available + 26 + 1 + read-only + + + MODULE_CLOCK_GATED_PA + no description available + 27 + 1 + read-only + + + MODULE_CLOCK_GATED_SH + no description available + 28 + 1 + read-only + + + MODULE_CLOCK_GATED_PE + no description available + 29 + 1 + read-only + + + MODULE_CLOCK_GATED_DE + no description available + 30 + 1 + read-only + + + MODULE_CLOCK_GATED_FE + no description available + 31 + 1 + read-only + + + + + + + ARMGLOBALTIMER + ARM Cortex-A9 Global Timer + ARMGLOBALTIMER_ + 0xA00000 + + 0x200 + 0x1C + registers + + + + 2 + 0x4 + 0,1 + COUNTER%s + Global Timer Counter Registers + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + VALUE + no description available + 0 + 32 + read-write + + + + + CONTROL + Global Timer Control Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER_ENABLE + no description available + 0 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + COMP_ENABLE + no description available + 1 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + IRQ_ENABLE + no description available + 2 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + AUTO_INCREMENT + no description available + 3 + 1 + read-write + + + 0 + SINGLE_SHOT_MODE + #0 + + + 1 + AUTO_INCREMENT_MODE + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + PRESCALER + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + IRQSTATUS + Global Timer Interrupt Status Register + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + EVENT_FLAG + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + 2 + 0x4 + 0,1 + COMPARATOR%s + Global Timer Comparator Value Registers + 0x210 + 32 + read-write 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+ Force_Link + no description available + 15 + 1 + read-write + + + Link_State + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 2 + read-only + + + Low_Power_Entrance_Count + no description available + 24 + 8 + read-write + + + + + AFLACR + Ack Frequency and L0-L1 ASPM Control Register + 0x70C + 32 + read-write + 0x1B2C2C00 + 0xFFFFFFFF + + + Ack_Frequency + no description available + 0 + 8 + read-write + + + N_FTS + no description available + 8 + 8 + read-write + + + Common_Clock_N_FTS + no description available + 16 + 8 + read-write + + + L0s_Entrance_Latency + no description available + 24 + 3 + read-write + + + 000 + 1 ìs + #000 + + + 001 + 2 ìs + #001 + + + 010 + 3 ìs + #010 + + + 011 + 4 ìs + #011 + + + 100 + 5 ìs + #100 + + + 101 + 6 ìs + #101 + + + 110 + 7 ìs + #110 + + + 111 + 7 ìs + #111 + + + + + L1_Entrance_Latency + no description available + 27 + 3 + read-write + + + 000 + 1 ìs + #000 + + + 001 + 2 ìs + #001 + + + 010 + 4 ìs + #010 + + + 011 + 8 ìs + #011 + + + 100 + 16 ìs + #100 + + + 101 + 32 ìs + #101 + + + 110 + 64 ìs + #110 + + + 111 + 64 ìs + #111 + + + + + Enter_ASPM_L1 + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + PLCR + Port Link Control Register + 0x710 + 32 + read-write + 0x10020 + 0xFFFFFFFF + + + Vendor_Specific_DLLP_Request + no description available + 0 + 1 + read-write + + + Scramble_Disable + no description available + 1 + 1 + read-write + + + Loopback_Enable + no description available + 2 + 1 + read-write + + + Reset_Assert + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 1 + read-only + + + DLL_Link_Enable + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + Fast_Link_Mode + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + Link_Mode_Enable + no description available + 16 + 6 + read-write + + + 000001 + x1 + #000001 + + + 000011 + x2 + #000011 + + + 000111 + x4 + #000111 + + + 001111 + x8 + #001111 + + + 011111 + x16 + #011111 + + + 111111 + x32 (not supported) + #111111 + + + + + Crosslink_Enable + no description available + 22 + 1 + read-write + + + Crosslink_Active + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + LSR + Lane Skew Register + 0x714 + 32 + read-write + 0 + 0xFFFFFFFF + + + Insert_Lane_Skew_for_Transmit + no description available + 0 + 24 + read-write + + + Flow_Control_Disable + no description available + 24 + 1 + read-write + + + Ack_Nak_Disable + no description available + 25 + 1 + read-write + + + RESERVED + no description available + 26 + 5 + read-only + + + Disable_Lane_to_Lane_Deskew + no description available + 31 + 1 + read-write + + + + + SNR + Symbol Number Register + 0x718 + 32 + read-write + 0x830A + 0xFFFFFFFF + + + Number_of_TS_Symbols + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + Number_of_SKP_Symbols + no description available + 8 + 3 + read-write + + + RESERVED + no description available + 11 + 3 + read-only + + + Timer_Modifier_for_Replay_Timer + no description available + 14 + 5 + read-write + + + Timer_Modifier_for_Ack_Nak_Latency_Timer + no description available + 19 + 5 + read-write + + + Timer_Modifier_for_Flow_Control_Watchdog_Timer + no description available + 24 + 5 + read-write + + + Configuration_Requests + no description available + 29 + 3 + read-write + + + + + STRFM1 + Symbol Timer Register and Filter Mask Register 1 + 0x71C + 32 + read-write + 0x640 + 0xFFFFFFFF + + + SKP_Interval_Value + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 4 + read-only + + + Disable_FC_Watchdog_Timer + no description available + 15 + 1 + read-write + + + Mask_RADM_Filtering_and_Error_Handling_Rules + no description available + 16 + 16 + read-write + + + + + STRFM2 + Filter Mask Register 2 + 0x720 + 32 + read-write + 0 + 0xFFFFFFFF + + + Mask_RADM_Filtering_and_Error_Handling_Rules + no description available + 0 + 32 + read-write + + + + + AMODNPSR + AMBA Multiple Outbound Decomposed NP Sub-Requests Control Register + 0x724 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + Enable_AMBA_Multiple_Outbound_Decomposed_NP_SubRequests + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + DEBUG0 + Debug Register 0 + 0x728 + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUE + no description available + 0 + 32 + read-only + + + + + DEBUG1 + Debug Register 1 + 0x72C + 32 + read-only + 0 + 0xFFFFFFFF + + + VALUE + no description available + 0 + 32 + read-only + + + + + TPFCSR + Transmit Posted FC Credit Status Register + 0x730 + 32 + read-only + 0 + 0xFFFFFFFF + + + Transmit_Posted_Data_FC_Credits + no description available + 0 + 12 + read-only + + + Transmit_Posted_Header_FC_Credits + no description available + 12 + 8 + read-only + + + RESERVED + no description available + 20 + 12 + read-only + + + + + TNFCSR + Transmit Non-Posted FC Credit Status Register + 0x734 + 32 + read-only + 0 + 0xFFFFFFFF + + + Transmit_Non_Posted_Data_FC_Credits + no description available + 0 + 12 + read-only + + + Transmit_Non_Posted_Header_FC_Credits + no description available + 12 + 8 + read-only + + + RESERVED + no description available + 20 + 12 + read-only + + + + + TCFCSR + Transmit Completion FC Credit Status Register + 0x738 + 32 + read-only + 0 + 0xFFFFFFFF + + + Transmit_Completion_Data_FC_Credits + no description available + 0 + 12 + read-only + + + Transmit_Completion_Header_FC_Credits + no description available + 12 + 8 + read-only + + + RESERVED + no description available + 20 + 12 + read-only + + + + + QSR + Queue Status Register + 0x73C + 32 + read-only + 0 + 0xFFFFFFFF + + + Received_TLP_FC_Credits_Not_Returned + no description available + 0 + 1 + read-only + + + Transmit_Retry_Buffer_Not_Empty + no description available + 1 + 1 + read-only + + + Received_Queue_Not_Empty + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 29 + read-only + + + + + VCTAR1 + VC Transmit Arbitration Register 1 + 0x740 + 32 + read-only + 0xF + 0xFFFFFFFF + + + WRR_Weight_for_VC0 + no description available + 0 + 8 + read-only + + + WRR_Weight_for_VC1 + no description available + 8 + 8 + read-only + + + WRR_Weight_for_VC2 + no description available + 16 + 8 + read-only + + + WRR_Weight_for_VC3 + no description available + 24 + 8 + read-only + + + + + VCTAR2 + VC Transmit Arbitration Register 2 + 0x744 + 32 + read-only + 0 + 0xFFFFFFFF + + + WRR_Weight_for_VC4 + no description available + 0 + 8 + read-only + + + WRR_Weight_for_VC5 + no description available + 8 + 8 + read-only + + + WRR_Weight_for_VC6 + no description available + 16 + 8 + read-only + + + WRR_Weight_for_VC7 + no description available + 24 + 8 + read-only + + + + + VC0PRQC + VC0 Posted Receive Queue Control + 0x748 + 32 + read-write + 0x10C019 + 0xFFFFFFFF + + + VC0_Posted_Data_Credits + no description available + 0 + 12 + read-write + + + VC0_Posted_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC0_Posted_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 6 + read-only + + + TLP_Type_Ordering_for_VC0 + no description available + 30 + 1 + read-write + + + 1 + Ordering of received TLPs follows the rules in PCI Express 3.0 Specification. + #1 + + + 0 + Strict ordering for received TLPs: Posted, then Completion, then Non-Posted + #0 + + + + + VC_Ordering_for_Receive_Queues + no description available + 31 + 1 + read-write + + + 1 + Strict ordering, higher numbered VCs have higher priority + #1 + + + 0 + Round robin + #0 + + + + + + + VC0NRQC + VC0 Non-Posted Receive Queue Control + 0x74C + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + VC0_Non_Posted_Data_Credits + no description available + 0 + 12 + read-write + + + VC0_Non_Posted_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC0_Non_Posted_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + VC0CRQC + VC0 Completion Receive Queue Control + 0x750 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + VC0_Completion_Data_Credits + no description available + 0 + 12 + read-write + + + VC0_Completion_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC0_Completion_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + VCnPRQC + VCn Posted Receive Queue Control + 0x754 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + VC1_Posted_Data_Credits + no description available + 0 + 12 + read-write + + + VC1_Posted_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC1_Posted_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 6 + read-only + + + TLP_Type_Ordering_for_VC1 + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + VCnNRQC + VCn Non-Posted Receive Queue Control + 0x758 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + VC1_Non_Posted_Data_Credits + no description available + 0 + 12 + read-write + + + VC1_Non_Posted_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC1_Non_Posted_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + VCnCRQC + VCn Completion Receive Queue Control + 0x75C + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + VC1_Completion_Data_Credits + no description available + 0 + 12 + read-write + + + VC1_Completion_Header_Credits + no description available + 12 + 8 + read-write + + + RESERVED + no description available + 20 + 1 + read-only + + + VC1_Completion_TLP_Queue_Mode + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + VC0PBD + VC0 Posted Buffer Depth + 0x7A8 + 32 + read-only + 0xD0065 + 0xFFFFFFFF + + + VC0_Posted_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC0_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VC0NPBD + VC0 Non-Posted Buffer Depth + 0x7AC + 32 + read-only + 0xD000D + 0xFFFFFFFF + + + VC0_Non_Posted_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC0_Non_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VC0CBD + VC0 Completion Buffer Depth + 0x7B0 + 32 + read-only + 0x30003 + 0xFFFFFFFF + + + VC0_Completion_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC0_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VC1PBD + VCn Posted Buffer Depth + 0x7B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + VC1_Posted_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC1_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VC1NPBD + VCn Non-Posted Buffer Depth + 0x7B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + VC1_Non_Posted_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC1_Non_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VC1CBD + VCnCompletion Buffer Depth + 0x7BC + 32 + read-only + 0 + 0xFFFFFFFF + + + VC1_Completion_Data_Queue_Depth + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + VC1_Posted_Header_Queue_Depth + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + G2CR + Gen2 Control Register + 0x80C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + N_FTS + no description available + 0 + 8 + read-write + + + Predetermined_Number_of_Lanes + no description available + 8 + 9 + read-write + + + Directed_Speed_Change + no description available + 17 + 1 + read-write + + + Config_PHY_Tx_Swing + no description available + 18 + 1 + read-write + + + Config_Tx_Compliance_Receive_Bit + no description available + 19 + 1 + read-write + + + De_emphasis_level + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + PHY_STATUS + PHY Status + 0x810 + 32 + read-only + 0 + 0xFFFFFFFF + + + PHY_Status + no description available + 0 + 32 + read-only + + + + + PHY_CTRL + PHY Control + 0x814 + 32 + read-write + 0 + 0xFFFFFFFF + + + PHY_Control + no description available + 0 + 32 + read-write + + + + + MRCCR0 + Master Response Composer Control Register 0 + 0x818 + 32 + read-write + 0x302 + 0xFFFFFFFF + + + Remote_Read_Request_Size + no description available + 0 + 3 + read-write + + + 000 + 128 + #000 + + + 001 + 256 + #001 + + + 010 + 512 + #010 + + + 011 + 1024 + #011 + + + 100 + 2048 + #100 + + + 101 + 4096 default: 128 + #101 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + Remote_Max_Bridge_Tag + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + MRCCR1 + Master Response Composer Control Register 1 + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + Segmented_Buffer_Controller_Initialize + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + MSICA + MSI Controller Address + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_Controller_Address + no description available + 0 + 32 + read-write + + + + + MSICUA + MSI Controller Upper Address + 0x824 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_Controller_Upper_Address + no description available + 0 + 32 + read-write + + + + + MSICIn_ENB + MSI Controller Interrupt n Enable + 0x828 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_Interrupt0_Enable + no description available + 0 + 32 + read-write + + + + + MSICIn_MASK + MSI Controller Interrupt n Mask + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_Interrupt0_Mask + no description available + 0 + 32 + read-write + + + + + MSICIn_STATUS + MSI Controller Interrupt nStatus + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_Interrupt0_Status + no description available + 0 + 32 + read-write + + + + + MSICGPIO + MSI Controller General Purpose IO Register + 0x888 + 32 + read-write + 0 + 0xFFFFFFFF + + + MSI_GPIO_Register + no description available + 0 + 32 + read-write + + + + + iATUVR + iATU Viewport Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + Region_Index + no description available + 0 + 4 + read-write + + + RESERVED + no description available + 4 + 27 + read-only + + + Region_Direction + no description available + 31 + 1 + read-write + + + 0 + Outbound + #0 + + + 1 + Inbound + #1 + + + + + + + iATURC1 + iATU Region Control 1 Register + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + TYPE + no description available + 0 + 5 + read-write + + + TC + no description available + 5 + 3 + read-write + + + TD + no description available + 8 + 1 + read-write + + + ATTR + no description available + 9 + 2 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + AT + no description available + 16 + 2 + read-write + + + RESERVED + no description available + 18 + 2 + read-only + + + Function_Number + no description available + 20 + 3 + read-write + + + RESERVED + no description available + 23 + 9 + read-only + + + + + iATURC2 + iATU Region Control 2 Register + 0x908 + 32 + read-write + 0 + 0xFFFFFFFF + + + Message_Code + no description available + 0 + 8 + read-write + + + BAR_Number + no description available + 8 + 3 + read-write + + + 000 + - BAR#0 + #000 + + + 001 + - BAR#1 + #001 + + + 010 + - BAR#2 + #010 + + + 011 + - BAR#3 + #011 + + + 100 + - BAR#4 + #100 + + + 101 + - BAR#5 + #101 + + + 110 + - ROM + #110 + + + 111 + - reserved + #111 + + + + + RESERVED + no description available + 11 + 3 + read-only + + + TC_Match_Enable + no description available + 14 + 1 + read-write + + + TD_Match_Enable + no description available + 15 + 1 + read-write + + + ATTR_Match_Enable + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + AT_Match_Enable + no description available + 18 + 1 + read-write + + + Function_Number_Match_Enable + no description available + 19 + 1 + read-write + + + Virtual_Function_Number_Match_Enable + no description available + 20 + 1 + read-write + + + Message_Code_Match_Enable + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 2 + read-only + + + Response_Code + no description available + 24 + 2 + read-write + + + 00 + - Normal RADM filter response is used. + #00 + + + 01 + - Unsupported Request (UR) + #01 + + + 10 + - Completer Abort (CA) + #10 + + + 11 + - Not used / undefined / reserved. + #11 + + + + + RESERVED + no description available + 26 + 1 + read-only + + + Fuzzy_Type_Match_Mode + no description available + 27 + 1 + read-write + + + CFG_Shift_Mode + no description available + 28 + 1 + read-write + + + Invert_Mode + no description available + 29 + 1 + read-write + + + Match_Mode + no description available + 30 + 1 + read-write + + + Region_Enable + no description available + 31 + 1 + read-write + + + + + iATURLBA + iATU Region Lower Base Address Register + 0x90C + 32 + read-write + 0 + 0xFFFFFFFF + + + Address_lower + no description available + 0 + 16 + read-write + + + Address_upper + no description available + 16 + 16 + read-write + + + + + iATURUBA + iATU Region Upper Base Address Register + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + Address + no description available + 0 + 32 + read-write + + + + + iATURLA + iATU Region Limit Address Register + 0x914 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + Address_lower + no description available + 0 + 16 + read-write + + + Address_upper + no description available + 16 + 16 + read-write + + + + + iATURLTA + iATU Region Lower Target Address Register + 0x918 + 32 + read-write + 0 + 0xFFFFFFFF + + + Address_lower + no description available + 0 + 16 + read-write + + + Address_upper + no description available + 16 + 16 + read-write + + + + + iATURUTA + iATU Region Upper Target Address Register + 0x91C + 32 + read-write + 0 + 0xFFFFFFFF + + + Address + no description available + 0 + 32 + read-write + + + + + + + PCIE_RC + PCIeRC + PCIE_RC_ + 0x1FFC000 + + 0 + 0x15C + registers + + + + DeviceID + Device ID and Vendor ID Register + 0 + 32 + read-only + 0xABCD16C3 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + Command + Command and Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + I_O_Space_Enable + no description available + 0 + 1 + read-write + + + Memory_Space_Enable + no description available + 1 + 1 + read-write + + + Bus_Master_Enable + no description available + 2 + 1 + read-write + + + Special_Cycle_Enable + no description available + 3 + 1 + read-write + + + Memory_Write_and_Invalidate + no description available + 4 + 1 + read-write + + + VGA_Palette_Snoop + no description available + 5 + 1 + read-write + + + Parity_Error_Response + no description available + 6 + 1 + read-write + + + IDSEL_Stepping + no description available + 7 + 1 + read-write + + + SERR_Enable + no description available + 8 + 1 + read-write + + + Fast_Back_to_Back_Enable + no description available + 9 + 1 + read-write + + + INTx_Assertion_Disable + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + RESERVED + no description available + 16 + 3 + read-only + + + INTx_Status + no description available + 19 + 1 + read-write + + + Capabilities_List + no description available + 20 + 1 + read-write + + + SixtySix_MHz_Capable + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + Fast_Back_to_Back_Capable + no description available + 23 + 1 + read-write + + + Master_Data_Parity_Error + no description available + 24 + 1 + read-write + + + DEVSEL_Timing + no description available + 25 + 2 + read-write + + + Signaled_Target_Abort + no description available + 27 + 1 + read-write + + + Received_Target_Abort + no description available + 28 + 1 + read-write + + + Received_Master_Abort + no description available + 29 + 1 + read-write + + + Detected_Parity_Error + no description available + 30 + 1 + read-write + + + Signaled_System_Error + no description available + 31 + 1 + read-write + + + + + RevID + Revision ID and Class Code Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + CX_REVISION_ID_N + no description available + 0 + 8 + read-only + + + IF_CODE_N + no description available + 8 + 8 + read-only + + + SUB_CLASS_CODE_N + no description available + 16 + 8 + read-only + + + BASE_CLASS_CODE_N + no description available + 24 + 8 + read-only + + + + + BIST + BIST Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + Cache_Line_Size + no description available + 0 + 8 + read-write + + + Master_Latency_Timer + no description available + 8 + 8 + read-write + + + Configuration_Header_Format + no description available + 16 + 7 + read-write + + + Multi_Function_Device + no description available + 23 + 1 + read-write + + + Not_supported_by__core + no description available + 24 + 8 + read-write + + + + + BAR0 + Base Address 0 + 0x10 + 32 + read-only + 0xC + 0xFFFFFFFF + + + Mem_I_O + no description available + 0 + 1 + read-only + + + 0 + = BAR 0 is a memory BAR + #0 + + + 1 + = BAR 0 is an I/O BAR + #1 + + + + + TYPE + no description available + 1 + 2 + read-only + + + 00 + = 32-bit BAR + #00 + + + 10 + = 64-bit BAR + #10 + + + + + PREF + no description available + 3 + 1 + read-only + + + 0 + = Non-prefetchable + #0 + + + 1 + = Prefetchable + #1 + + + + + ADDRESS + no description available + 4 + 28 + read-only + + + + + BAR1 + Base Address 1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDRESS + no description available + 0 + 32 + read-only + + + + + BNR + Bus Number Registers + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRIMARY_BUS_NUM + no description available + 0 + 8 + read-write + + + SECONDARY_BUS_NUM + no description available + 8 + 8 + read-write + + + SUBORD_BUS_NUM + no description available + 16 + 8 + read-write + + + SECONDARY_LAT_TMR + no description available + 24 + 8 + read-only + + + + + IOBLSSR + I/O Base Limit Secondary Status Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + IO_SB + no description available + 4 + 4 + read-write + + + RESERVED + no description available + 8 + 4 + read-only + + + IO_SL + no description available + 12 + 4 + read-write + + + RESERVED + no description available + 16 + 5 + read-only + + + 66M_CAP + no description available + 21 + 1 + read-only + + + RESERVED + no description available + 22 + 1 + read-only + + + FAST_B2B_CAP + no description available + 23 + 1 + read-only + + + MSTR_DAT_PARITY_ERR + no description available + 24 + 1 + read-write + + + RESERVED + no description available + 25 + 2 + read-only + + + SIG_TARGET_ABORT + no description available + 27 + 1 + read-write + + + RX_TARGET_ABORT + no description available + 28 + 1 + read-write + + + RX_MASTER_ABORT + no description available + 29 + 1 + read-write + + + RX_SYS_ERR + no description available + 30 + 1 + read-write + + + DET_PARITY_ERR + no description available + 31 + 1 + read-write + + + + + MEM_BLR + Memory Base and Memory Limit Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + MEM_BASE_ADD + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + MEM_LIM_ADD + no description available + 24 + 8 + read-write + + + + + PREF_MEM_BLR + Prefetchable Memory Base and Limit Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + UPPER12_START_ADD + no description available + 4 + 12 + read-write + + + RESERVED + no description available + 16 + 4 + read-only + + + UPPER12_END_ADD + no description available + 20 + 12 + read-write + + + + + PREF_BASE_U32 + Prefetchable Base Upper 32 Bits Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + UPPER32_BASE_PREF_MEM_ADD + no description available + 0 + 32 + read-write + + + + + PREF_LIM_U32 + Prefetchable Limit Upper 32 Bits Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + UPPER32_LIM_PREF_MEM_ADD + no description available + 0 + 32 + read-write + + + + + IO_BASE_LIM_U16 + I/O Base and Limit Upper 16 Bits Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + UPPER16_IO_BASE + no description available + 0 + 16 + read-write + + + UPPER16_IO_LIM + no description available + 16 + 16 + read-write + + + + + CAPPR + Capability Pointer Register + 0x34 + 32 + read-only + 0x40 + 0xFFFFFFFF + + + CFG_NEXT_PTR + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 24 + read-only + + + + + EROMBAR + Expansion ROM Base Address Register + PCIE_RC + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 10 + read-only + + + ADDRESS + no description available + 11 + 21 + read-write + + + + + EROMMASK + Expansion ROM BAR Mask Register + PCIE_RC + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROM_BAR_ENABLED_N + no description available + 0 + 1 + read-write + + + 0 + Expansion ROM BAR is disabled + #0 + + + 1 + Expansion ROM BAR is enabled + #1 + + + + + ROM_MASK_N + no description available + 1 + 31 + read-write + + + + + PMCR + Power Management Capability Register + 0x40 + 32 + read-only + 0xDBC35001 + 0xFFFFFFFF + + + Power_Management_Capability_ID + no description available + 0 + 8 + read-only + + + Next_Capability_Pointer + no description available + 8 + 8 + read-only + + + Power_Management_specification_version + no description available + 16 + 3 + read-only + + + PME_Clock + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + DSI + no description available + 21 + 1 + read-only + + + AUX_Current + no description available + 22 + 3 + read-only + + + D1_Support + no description available + 25 + 1 + read-only + + + D2_Support + no description available + 26 + 1 + read-only + + + PME_Support + no description available + 27 + 5 + read-only + + + + + PMCSR + Power Management Control and Status Register + 0x44 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + Power_State + no description available + 0 + 2 + read-write + + + 00 + D0 + #00 + + + 01 + D1 + #01 + + + 10 + D2 + #10 + + + 11 + D3 + #11 + + + + + RESERVED + no description available + 2 + 1 + read-only + + + No_Soft_Reset + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 4 + read-only + + + PME_Enable + no description available + 8 + 1 + read-write + + + Data_Select + no description available + 9 + 4 + read-write + + + Data_Scale + no description available + 13 + 2 + read-write + + + PME_Status + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 6 + read-only + + + B2_B3_Support + no description available + 22 + 1 + read-write + + + Bus_Power_Clock_Control_Enable + no description available + 23 + 1 + read-write + + + Data_register_for_additional_information + no description available + 24 + 8 + read-write + + + + + CIDR + PCI Express Capability ID Register + 0x70 + 32 + read-only + 0 + 0xFFFFFFFF + + + PCI_Express_Capability_ID + no description available + 0 + 8 + read-only + + + Next_Capability_Pointer + no description available + 8 + 8 + read-only + + + PCI_Express_Capability_Version + no description available + 16 + 4 + read-only + + + Device_Port_Type + no description available + 20 + 4 + read-only + + + Slot_Implemented + no description available + 24 + 1 + read-only + + + Interrupt_Message_Number + no description available + 25 + 5 + read-only + + + RESERVED + no description available + 30 + 2 + read-only + + + + + DCR + Device Capabilities Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + Max_Payload_Size_Supported + no description available + 0 + 3 + read-write + + + Phantom_Function_Supported + no description available + 3 + 2 + read-write + + + Extended_Tag_Field_Supported + no description available + 5 + 1 + read-write + + + Endpoint_L0s_Acceptable_Latency + no description available + 6 + 3 + read-write + + + Endpoint_L1_Acceptable_Latency + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 1 + read-only + + + RESERVED + no description available + 13 + 1 + read-only + + + RESERVED + no description available + 14 + 1 + read-only + + + Role_Based_Error_Reporting + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 2 + read-only + + + Captured_Slot_Power_Limit_Value + no description available + 18 + 8 + read-write + + + Captured_Slot_Power_Limit_Scale + no description available + 26 + 2 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DConR + Device Control Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + Correctable_Error_Reporting_Enable + no description available + 0 + 1 + read-write + + + Non_Fatal_Error_Reporting_Enable + no description available + 1 + 1 + read-write + + + Fatal_Error_Reporting_Enable + no description available + 2 + 1 + read-write + + + Unsupported_Request_Reporting_Enable + no description available + 3 + 1 + read-write + + + Enable_Relaxed_Ordering + no description available + 4 + 1 + read-write + + + Max_Payload_Size + no description available + 5 + 3 + read-write + + + Extended_Tag_Field_Enable + no description available + 8 + 1 + read-write + + + Phantom_Function_Enable + no description available + 9 + 1 + read-write + + + AUX_Power_PM_Enable + no description available + 10 + 1 + read-write + + + Enable_No_Snoop + no description available + 11 + 1 + read-write + + + Max_Read_Request_Size + no description available + 12 + 3 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + Correctable_Error_Detected + no description available + 16 + 1 + read-write + + + Non_Fatal_Error_detected + no description available + 17 + 1 + read-write + + + Fatal_Error_Detected + no description available + 18 + 1 + read-write + + + Unsupported_Request_Detected + no description available + 19 + 1 + read-write + + + Aux_Power_Detected + no description available + 20 + 1 + read-write + + + Transaction_Pending + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + LCR + Link Capabilities Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + Max_Link_Speeds + no description available + 0 + 4 + read-only + + + Maximum_Link_Width + no description available + 4 + 6 + read-only + + + Active_State_Link_PM_Support + no description available + 10 + 2 + read-only + + + L0s_Exit_Latency + no description available + 12 + 3 + read-only + + + L1_Exit_Latency + no description available + 15 + 3 + read-only + + + Clock_Power_Management + no description available + 18 + 1 + read-only + + + Surprise_Down_Error_Reporting_Capable + no description available + 19 + 1 + read-only + + + Data_Link_Layer_Active_Reporting_Capable + no description available + 20 + 1 + read-only + + + Link_Bandwidth_Notification_Capability + no description available + 21 + 1 + read-only + + + RESERVED + no description available + 22 + 2 + read-only + + + Port_Number + no description available + 24 + 8 + read-only + + + + + LCSR + Link Control and Status Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + Active_State_Link_PM_Control + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 1 + read-only + + + RCB + no description available + 3 + 1 + read-write + + + Link_Disable + no description available + 4 + 1 + read-write + + + Retrain_Link + no description available + 5 + 1 + read-write + + + Common_Clock_Configuration + no description available + 6 + 1 + read-write + + + Extended_Synch + no description available + 7 + 1 + read-write + + + Enable_Clock_Power_Management + no description available + 8 + 1 + read-write + + + Hardware_Autonomous_Width_Disable + no description available + 9 + 1 + read-write + + + Link_Bandwidth_Management_Interrupt_Enable + no description available + 10 + 1 + read-write + + + Link_Autonomous_Bandwidth_Interrupt_Enable + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + Link_Speed + no description available + 16 + 4 + read-write + + + 0001 + Gen1 2.5 GT/s + #0001 + + + 0010 + Gen2 5.0 GT/s + #0010 + + + + + Negotiated_Link_Width + no description available + 20 + 6 + read-write + + + RESERVED + no description available + 26 + 1 + read-only + + + Link_Training + no description available + 27 + 1 + read-write + + + Slot_Clock_Configuration + no description available + 28 + 1 + read-write + + + Data_Link_Layer_Active + no description available + 29 + 1 + read-write + + + Link_Bandwidth_Management_Status + no description available + 30 + 1 + read-write + + + Link_Autonomous_Bandwidth_Status + no description available + 31 + 1 + read-write + + + + + SCR + Slot Capabilities Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + Attention_Indicator_Present + no description available + 0 + 1 + read-only + + + Power_Controller_Present_0 + no description available + 1 + 1 + read-only + + + MRL_Sensor_Present + no description available + 2 + 1 + read-only + + + Attention_Indicator_Present_1 + no description available + 3 + 1 + read-only + + + Power_Indicator_Present + no description available + 4 + 1 + read-only + + + Hot_Plug_Surprise + no description available + 5 + 1 + read-only + + + Hot_Plug_Capable + no description available + 6 + 1 + read-only + + + Slot_Power_Limit_Value + no description available + 7 + 8 + read-only + + + Slot_Power_Limit_Scale + no description available + 15 + 2 + read-only + + + Electromechanical_Interlock_Present + no description available + 17 + 1 + read-only + + + No_Command_Complete_Support + no description available + 18 + 1 + read-only + + + Physical_Slot_Number + no description available + 19 + 13 + read-only + + + + + SCSR + Slot Control and Status Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + Attention_Button_Pressed_Enable + no description available + 0 + 1 + read-write + + + Power_Fault_Detected_Enable + no description available + 1 + 1 + read-write + + + MRL_Sensor_Changed_Enable + no description available + 2 + 1 + read-write + + + Presence_Detect_Changed_Enable + no description available + 3 + 1 + read-write + + + Command_Completed_Interrupt_Enable + no description available + 4 + 1 + read-write + + + Hot_Plug_Interrupt_Enable + no description available + 5 + 1 + read-write + + + Attention_Indicator_Control + no description available + 6 + 2 + read-write + + + Power_Indicator_Control + no description available + 8 + 2 + read-write + + + Power_Controller_Control + no description available + 10 + 1 + read-write + + + Electromechanical_Interlock_Control + no description available + 11 + 1 + read-write + + + Data_Link_Layer_State_Changed_Enable + no description available + 12 + 1 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + Attention_Button_Pressed + no description available + 16 + 1 + read-write + + + Power_Fault_Detected + no description available + 17 + 1 + read-write + + + MRL_Sensor_Changed + no description available + 18 + 1 + read-write + + + Presence_Detect_Changed + no description available + 19 + 1 + read-write + + + Command_Completed + no description available + 20 + 1 + read-write + + + MRL_Sensor_State + no description available + 21 + 1 + read-write + + + Presence_Detect_State + no description available + 22 + 1 + read-write + + + Electromechanical_Interlock_Status + no description available + 23 + 1 + read-write + + + Data_Link_Layer_State_Changed + no description available + 24 + 1 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + RCCR + Root Control and Capabilities Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + System_Error_on_Correctable_Error_Enable + no description available + 0 + 1 + read-write + + + System_Error_on_Non_fatal_Error_Enable + no description available + 1 + 1 + read-write + + + System_Error_on_Fatal_Error_Enable + no description available + 2 + 1 + read-write + + + PME_Interrupt_Enable + no description available + 3 + 1 + read-write + + + CRS_Software_Visibility_Enable + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 11 + read-only + + + CRS_Software_Visibility + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 15 + read-only + + + + + RSR + Root Status Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + PME_Requester_ID + no description available + 0 + 16 + read-write + + + PME_Status + no description available + 16 + 1 + read-write + + + PME_Pending + no description available + 17 + 1 + read-write + + + RESERVED + no description available + 18 + 14 + read-only + + + + + DCR2 + Device Capabilities 2 Register + 0x94 + 32 + read-only + 0x1F + 0xFFFFFFFF + + + Completion_Timeout_Ranges_Supported + no description available + 0 + 4 + read-only + + + Completion_Timeout_Disable_Supported + no description available + 4 + 1 + read-only + + + RESERVED + no description available + 5 + 27 + read-only + + + + + DCSR2 + Device Control and Status 2 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + Completion_Timeout_Value + no description available + 0 + 4 + read-write + + + 0000 + Default range: 50 ìs to 50 ms + #0000 + + + 0001 + 50 ìs to 100 ìs + #0001 + + + 0010 + 1 ms to 10 ms + #0010 + + + 0101 + 16 ms to 55 ms + #0101 + + + 0110 + 65 ms to 210 ms + #0110 + + + 1001 + 260 ms to 900 ms + #1001 + + + 1010 + 1 s to 3.5 s + #1010 + + + 1101 + 4 s to 13 s + #1101 + + + 1110 + 17 s to 64 s + #1110 + + + + + Completion_Timeout_Disable + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 27 + read-only + + + + + LCR2 + Link Capabilities 2 Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + Supported_Link_Speeds_Vector + no description available + 1 + 7 + read-only + + + Crosslink_Supported + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + LCSR2 + Link Control and Status 2 Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Target_Link_Speed + no description available + 0 + 4 + read-write + + + Enter_Compliance + no description available + 4 + 1 + read-write + + + Hardware_Autonomous_Speed_Disable + no description available + 5 + 1 + read-write + + + Selectable_Deemphasis + no description available + 6 + 1 + read-write + + + 1 + -3.5 dB + #1 + + + 0 + -6 dB + #0 + + + + + Transmit_Margin + no description available + 7 + 3 + read-write + + + 000 + 800-1200 mV for full swing 400-600 mV for half- swing + #000 + + + 011 + 200-400 mV for full-swing and 100-200 mV for halfswing + #011 + + + + + Enter_Modified_Compliance + no description available + 10 + 1 + read-write + + + Compliance_SOS + no description available + 11 + 1 + read-write + + + Compliance_Pre_set_Deemphasis + no description available + 12 + 4 + read-write + + + Current_Deemphasis_Level + no description available + 16 + 1 + read-write + + + Equalization_Complete + no description available + 17 + 1 + read-write + + + Equalization_Phase_1_Successful + no description available + 18 + 1 + read-write + + + Equalization_Phase_2_Successful + no description available + 19 + 1 + read-write + + + Equalization_Phase_3_Successful + no description available + 20 + 1 + read-write + + + Link_Equalization_Request + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + AER + AER Capability Header + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCI_Express_Extended_Capability_ID + no description available + 0 + 16 + read-write + + + Capability_Version + no description available + 16 + 4 + read-write + + + Next_Capability_Offset + no description available + 20 + 12 + read-write + + + + + UESR + Uncorrectable Error Status Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Status + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Status_ + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Status + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Status + no description available + 13 + 1 + read-write + + + Completion_Timeout_Status + no description available + 14 + 1 + read-write + + + Completer_Abort_Status + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Status + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Status + no description available + 17 + 1 + read-write + + + Malformed_TLP_Status + no description available + 18 + 1 + read-write + + + ECRC_Error_Status + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Status + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + UEMR + Uncorrectable Error Mask Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Mask + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Mask + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Mask + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Mask + no description available + 13 + 1 + read-write + + + Completion_Timeout_Mask + no description available + 14 + 1 + read-write + + + Completer_Abort_Mask + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Mask + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Mask + no description available + 17 + 1 + read-write + + + Malformed_TLP_Mask + no description available + 18 + 1 + read-write + + + ECRC_Error_Mask + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Mask + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + UESevR + Uncorrectable Error Severity Register + 0x10C + 32 + read-write + 0xC2031 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Severity + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Severity + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Severity + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Severity + no description available + 13 + 1 + read-write + + + Completion_Timeout_Severity + no description available + 14 + 1 + read-write + + + Completer_Abort_Severity + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Severity + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Severity + no description available + 17 + 1 + read-write + + + Malformed_TLP_Severity + no description available + 18 + 1 + read-write + + + ECRC_Error_Severity + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Severity + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + CESR + Correctable Error Status Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + Receiver_Error_Status + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 5 + read-only + + + Bad_TLP_Status + no description available + 6 + 1 + read-write + + + Bad_DLLP_Status + no description available + 7 + 1 + read-write + + + REPLAY_NUM_Rollover_Status + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 3 + read-only + + + Reply_Timer_Timeout_Status + no description available + 12 + 1 + read-write + + + Advisory_Non_Fatal_Error_Status + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + CEMR + Correctable Error Mask Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + Receiver_Error_Mask + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 5 + read-only + + + Bad_TLP_Mask + no description available + 6 + 1 + read-write + + + Bad_DLLP_Mask + no description available + 7 + 1 + read-write + + + REPLAY_NUM_Rollover_Mask + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 3 + read-only + + + Reply_Timer_Timeout_Mask + no description available + 12 + 1 + read-write + + + Advisory_Non_Fatal_Error_Mask + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + ACCR + Advanced Capabilities and Control Register + 0x118 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + First_Error_Pointer + no description available + 0 + 5 + read-write + + + ECRC_Generation_Capability + no description available + 5 + 1 + read-write + + + ECRC_Generation_Enable + no description available + 6 + 1 + read-write + + + ECRC_Check_Capable + no description available + 7 + 1 + read-write + + + ECRC_Check_Enable + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + HLR + Header Log Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + RECR + Root Error Command Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + Correctable_Error_Reporting_Enable + no description available + 0 + 1 + read-write + + + Non_Fatal_Error_Reporting_Enable + no description available + 1 + 1 + read-write + + + Fatal_Error_Reporting_Enable + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 29 + read-only + + + + + RESR + Root Error Status Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR_COR_Received + no description available + 0 + 1 + read-write + + + Multiple_ERR_COR_Received + no description available + 1 + 1 + read-write + + + ERR_FATAL_NONFATAL_Received + no description available + 2 + 1 + read-write + + + Multiple_ERR_FATAL_NONFATAL_Received + no description available + 3 + 1 + read-write + + + First_Uncorrectable_Fatal + no description available + 4 + 1 + read-write + + + Non_Fatal_Error_Messages_Received + no description available + 5 + 1 + read-write + + + Fatal_Error_Messages_Received + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 20 + read-only + + + Advanced_Error_Interrupt_Message_Number + no description available + 27 + 5 + read-write + + + + + ESIR + Error Source Identification Register + 0x134 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERR_COR_SID + no description available + 0 + 16 + read-only + + + ERR_FATAL_NONFATAL_SID + no description available + 16 + 16 + read-only + + + + + VCECHR + VC Extended Capability Header + 0x140 + 32 + read-only + 0x12 + 0xFFFFFFFF + + + Extended_Capability + no description available + 0 + 16 + read-only + + + Capability_Version + no description available + 16 + 4 + read-only + + + Next_Capability_Offset + no description available + 20 + 12 + read-only + + + + + PVCCR1 + Port VC Capability Register 1 + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + Extended_VC_Count + no description available + 0 + 3 + read-only + + + RESERVED + no description available + 3 + 1 + read-only + + + Low_Priority_Extended_VC_Count + no description available + 4 + 3 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + Reference_Clock + no description available + 8 + 2 + read-only + + + Port_Arbitration_Table_Entry_Size + no description available + 10 + 2 + read-only + + + RESERVED + no description available + 12 + 20 + read-only + + + + + PVCCR2 + Port VC Capability Register 2 + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + VC_Arbitration_Capability + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 16 + read-only + + + VC_Arbitration_Table_Offset + no description available + 24 + 8 + read-only + + + + + PVCCSR + Port VC Control and Status Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + Load_VC_Arbitration_Table + no description available + 0 + 1 + read-write + + + VC_Arbitration_Select + no description available + 1 + 3 + read-write + + + RESERVED + no description available + 4 + 12 + read-only + + + Arbitration_Table_Status + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 15 + read-only + + + + + VCRCR + VC Resource Capability Register n + 0x150 + 32 + read-only + 0 + 0xFFFFFFFF + + + Port_Arbitration_Capability + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 6 + read-only + + + Undefined + no description available + 14 + 1 + read-only + + + Reject_Snoop_Transactions + no description available + 15 + 1 + read-only + + + Maximum_Time_Slots + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + Port_Arbitration_Table_Offset + no description available + 24 + 8 + read-only + + + + + VCRConR + VC Resource Control Register n + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_VC_Map + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + Load_Port_Arbitration_Table + no description available + 16 + 1 + read-write + + + Port_Arbitration_Select + no description available + 17 + 3 + read-write + + + RESERVED + no description available + 20 + 4 + read-only + + + VC_ID + no description available + 24 + 3 + read-write + + + RESERVED + no description available + 27 + 4 + read-only + + + VC_Enable + no description available + 31 + 1 + read-write + + + + + VCRSR + VC Resource Status Register n + 0x158 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + Port_Arbitration_Table_Status + no description available + 16 + 1 + read-only + + + VC_Negotiation_Pending + no description available + 17 + 1 + read-only + + + RESERVED + no description available + 18 + 14 + read-only + + + + + + + PCIE_EP + PCIeEP + PCIE_EP_ + 0x1FFC000 + + 0 + 0x15C + registers + + + + DeviceID + Device ID and Vendor ID Register + 0 + 32 + read-only + 0xABCD16C3 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + Command + Command and Status Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + I_O_Space_Enable + no description available + 0 + 1 + read-write + + + Memory_Space_Enable + no description available + 1 + 1 + read-write + + + Bus_Master_Enable + no description available + 2 + 1 + read-write + + + Special_Cycle_Enable + no description available + 3 + 1 + read-write + + + Memory_Write_and_Invalidate + no description available + 4 + 1 + read-write + + + VGA_Palette_Snoop + no description available + 5 + 1 + read-write + + + Parity_Error_Response + no description available + 6 + 1 + read-write + + + IDSEL_Stepping + no description available + 7 + 1 + read-write + + + SERR_Enable + no description available + 8 + 1 + read-write + + + Fast_Back_to_Back_Enable + no description available + 9 + 1 + read-write + + + INTx_Assertion_Disable + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + RESERVED + no description available + 16 + 3 + read-only + + + INTx_Status + no description available + 19 + 1 + read-write + + + Capabilities_List + no description available + 20 + 1 + read-write + + + SixtySix_MHz_Capable + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + Fast_Back_to_Back_Capable + no description available + 23 + 1 + read-write + + + Master_Data_Parity_Error + no description available + 24 + 1 + read-write + + + DEVSEL_Timing + no description available + 25 + 2 + read-write + + + Signaled_Target_Abort + no description available + 27 + 1 + read-write + + + Received_Target_Abort + no description available + 28 + 1 + read-write + + + Received_Master_Abort + no description available + 29 + 1 + read-write + + + Detected_Parity_Error + no description available + 30 + 1 + read-write + + + Signaled_System_Error + no description available + 31 + 1 + read-write + + + + + BIST + BIST Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + Cache_Line_Size + no description available + 0 + 8 + read-write + + + Master_Latency_Timer + no description available + 8 + 8 + read-write + + + Configuration_Header_Format + no description available + 16 + 7 + read-write + + + Multi_Function_Device + no description available + 23 + 1 + read-write + + + Not_supported_by__core + no description available + 24 + 8 + read-write + + + + + MASK0 + BAR 0 Mask Register + PCIE_EP + 0x10 + 32 + read-only + 0xC + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-only + + + 0 + BAR 0 is disabled + #0 + + + 1 + BAR 0 is enabled + #1 + + + + + MASK + no description available + 1 + 31 + read-only + + + + + BAR0 + Base Address 0 + PCIE_EP + 0x10 + 32 + read-only + 0xC + 0xFFFFFFFF + + + Mem_I_O + no description available + 0 + 1 + read-only + + + 0 + = BAR 0 is a memory BAR + #0 + + + 1 + = BAR 0 is an I/O BAR + #1 + + + + + TYPE + no description available + 1 + 2 + read-only + + + 00 + = 32-bit BAR + #00 + + + 10 + = 64-bit BAR + #10 + + + + + PREF + no description available + 3 + 1 + read-only + + + 0 + = Non-prefetchable + #0 + + + 1 + = Prefetchable + #1 + + + + + ADDRESS + no description available + 4 + 28 + read-only + + + + + MASK1 + BAR 1 Mask Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + MASK + no description available + 0 + 32 + read-only + + + + + MASK2 + BAR 2 Mask Register + 0x18 + 32 + read-only + 0x8 + 0xFFFFFFFF + + + BAR2_ENABLED_N + no description available + 0 + 1 + read-only + + + 0 + BAR 2 is disabled + #0 + + + 1 + BAR 2 is enabled + #1 + + + + + BAR2_MASK_N + no description available + 1 + 31 + read-only + + + + + MASK3 + BAR 3 Mask Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + MASK + no description available + 0 + 32 + read-only + + + + + CISP + CardBus CIS Pointer Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CARDBUS_CIS_PTR_N + no description available + 0 + 32 + read-only + + + + + SSID + Subsystem ID and Subsystem Vendor ID Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + SUBSYS_VENDOR_ID_N + no description available + 0 + 16 + read-only + + + SUBSYS_DEV_ID_N + no description available + 16 + 16 + read-only + + + + + EROMBAR + Expansion ROM Base Address Register + PCIE_EP + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 10 + read-only + + + ADDRESS + no description available + 11 + 21 + read-write + + + + + EROMMASK + Expansion ROM BAR Mask Register + PCIE_EP + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROM_BAR_ENABLED_N + no description available + 0 + 1 + read-write + + + 0 + Expansion ROM BAR is disabled + #0 + + + 1 + Expansion ROM BAR is enabled + #1 + + + + + ROM_MASK_N + no description available + 1 + 31 + read-write + + + + + CAPPR + Capability Pointer Register + 0x34 + 32 + read-only + 0x40 + 0xFFFFFFFF + + + CFG_NEXT_PTR + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 24 + read-only + + + + + ILR + Interrupt Line and Pin Register + 0x3C + 32 + read-write + 0x1FF + 0xFFFFFFFF + + + INTERRUPT_LINE + no description available + 0 + 8 + read-write + + + INT_PIN_MAPPING_N + no description available + 8 + 8 + read-write + + + 0 + The device (or function) does not use legacy interrupt + #0 + + + 1 + The device (or function) uses INTA + #1 + + + 10 + The device (or function) uses INTB + #10 + + + 11 + The device (or function) uses INTC + #11 + + + 100 + The device (or function) uses INTD + #100 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + AER + AER Capability Header + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCI_Express_Extended_Capability_ID + no description available + 0 + 16 + read-write + + + Capability_Version + no description available + 16 + 4 + read-write + + + Next_Capability_Offset + no description available + 20 + 12 + read-write + + + + + UESR + Uncorrectable Error Status Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Status + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Status_ + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Status + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Status + no description available + 13 + 1 + read-write + + + Completion_Timeout_Status + no description available + 14 + 1 + read-write + + + Completer_Abort_Status + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Status + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Status + no description available + 17 + 1 + read-write + + + Malformed_TLP_Status + no description available + 18 + 1 + read-write + + + ECRC_Error_Status + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Status + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + UEMR + Uncorrectable Error Mask Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Mask + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Mask + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Mask + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Mask + no description available + 13 + 1 + read-write + + + Completion_Timeout_Mask + no description available + 14 + 1 + read-write + + + Completer_Abort_Mask + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Mask + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Mask + no description available + 17 + 1 + read-write + + + Malformed_TLP_Mask + no description available + 18 + 1 + read-write + + + ECRC_Error_Mask + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Mask + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + UESevR + Uncorrectable Error Severity Register + 0x10C + 32 + read-write + 0xC2031 + 0xFFFFFFFF + + + Undefined + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 3 + read-only + + + Data_Link_Protocol_Error_Severity + no description available + 4 + 1 + read-write + + + Surprise_Down_Error_Severity + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 6 + read-only + + + Poisoned_TLP_Severity + no description available + 12 + 1 + read-write + + + Flow_Control_Protocol_Error_Severity + no description available + 13 + 1 + read-write + + + Completion_Timeout_Severity + no description available + 14 + 1 + read-write + + + Completer_Abort_Severity + no description available + 15 + 1 + read-write + + + Unexpected_Completion_Severity + no description available + 16 + 1 + read-write + + + Receiver_Overflow_Severity + no description available + 17 + 1 + read-write + + + Malformed_TLP_Severity + no description available + 18 + 1 + read-write + + + ECRC_Error_Severity + no description available + 19 + 1 + read-write + + + Unsupported_Request_Error_Severity + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + CESR + Correctable Error Status Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + Receiver_Error_Status + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 5 + read-only + + + Bad_TLP_Status + no description available + 6 + 1 + read-write + + + Bad_DLLP_Status + no description available + 7 + 1 + read-write + + + REPLAY_NUM_Rollover_Status + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 3 + read-only + + + Reply_Timer_Timeout_Status + no description available + 12 + 1 + read-write + + + Advisory_Non_Fatal_Error_Status + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + CEMR + Correctable Error Mask Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + Receiver_Error_Mask + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 5 + read-only + + + Bad_TLP_Mask + no description available + 6 + 1 + read-write + + + Bad_DLLP_Mask + no description available + 7 + 1 + read-write + + + REPLAY_NUM_Rollover_Mask + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 3 + read-only + + + Reply_Timer_Timeout_Mask + no description available + 12 + 1 + read-write + + + Advisory_Non_Fatal_Error_Mask + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + ACCR + Advanced Capabilities and Control Register + 0x118 + 32 + read-write + 0xA0 + 0xFFFFFFFF + + + First_Error_Pointer + no description available + 0 + 5 + read-write + + + ECRC_Generation_Capability + no description available + 5 + 1 + read-write + + + ECRC_Generation_Enable + no description available + 6 + 1 + read-write + + + ECRC_Check_Capable + no description available + 7 + 1 + read-write + + + ECRC_Check_Enable + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + HLR + Header Log Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + VCECHR + VC Extended Capability Header + 0x140 + 32 + read-only + 0x12 + 0xFFFFFFFF + + + Extended_Capability + no description available + 0 + 16 + read-only + + + Capability_Version + no description available + 16 + 4 + read-only + + + Next_Capability_Offset + no description available + 20 + 12 + read-only + + + + + PVCCR1 + Port VC Capability Register 1 + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + Extended_VC_Count + no description available + 0 + 3 + read-only + + + RESERVED + no description available + 3 + 1 + read-only + + + Low_Priority_Extended_VC_Count + no description available + 4 + 3 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + Reference_Clock + no description available + 8 + 2 + read-only + + + Port_Arbitration_Table_Entry_Size + no description available + 10 + 2 + read-only + + + RESERVED + no description available + 12 + 20 + read-only + + + + + PVCCR2 + Port VC Capability Register 2 + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + VC_Arbitration_Capability + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 16 + read-only + + + VC_Arbitration_Table_Offset + no description available + 24 + 8 + read-only + + + + + PVCCSR + Port VC Control and Status Register + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + Load_VC_Arbitration_Table + no description available + 0 + 1 + read-write + + + VC_Arbitration_Select + no description available + 1 + 3 + read-write + + + RESERVED + no description available + 4 + 12 + read-only + + + Arbitration_Table_Status + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 15 + read-only + + + + + VCRCR + VC Resource Capability Register n + 0x150 + 32 + read-only + 0 + 0xFFFFFFFF + + + Port_Arbitration_Capability + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 6 + read-only + + + Undefined + no description available + 14 + 1 + read-only + + + Reject_Snoop_Transactions + no description available + 15 + 1 + read-only + + + Maximum_Time_Slots + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + Port_Arbitration_Table_Offset + no description available + 24 + 8 + read-only + + + + + VCRConR + VC Resource Control Register n + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TC_VC_Map + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + Load_Port_Arbitration_Table + no description available + 16 + 1 + read-write + + + Port_Arbitration_Select + no description available + 17 + 3 + read-write + + + RESERVED + no description available + 20 + 4 + read-only + + + VC_ID + no description available + 24 + 3 + read-write + + + RESERVED + no description available + 27 + 4 + read-only + + + VC_Enable + no description available + 31 + 1 + read-write + + + + + VCRSR + VC Resource Status Register n + 0x158 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + Port_Arbitration_Table_Status + no description available + 16 + 1 + read-only + + + VC_Negotiation_Pending + no description available + 17 + 1 + read-only + + + RESERVED + no description available + 18 + 14 + read-only + + + + + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + 0x2000000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x496ED40 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MPROT3 + no description available + 16 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT2 + no description available + 20 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT1 + no description available + 24 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT0 + no description available + 28 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC6 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC5 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC4 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC3 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC2 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC1 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC0 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC14 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC13 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC12 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC11 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC10 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC9 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC8 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC22 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC21 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC20 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC19 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC18 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC17 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC16 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC30 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC29 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC28 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC27 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC26 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC25 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC24 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + OPAC33 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC32 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x2100000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x496ED40 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MPROT3 + no description available + 16 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT2 + no description available + 20 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT1 + no description available + 24 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + MPROT0 + no description available + 28 + 4 + read-write + + + xxx0 + MPL + #xxx0 + + + xxx1 + MPL + #xxx1 + + + xx0x + MTW + #xx0x + + + xx1x + MTW + #xx1x + + + x0xx + MTR + #x0xx + + + x1xx + MTR + #x1xx + + + 1xxx + MBW + #1xxx + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC6 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC5 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC4 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC3 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC2 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC1 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC0 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC14 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC13 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC12 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC11 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC10 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC9 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC8 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC22 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC21 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC20 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC19 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC18 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC17 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC16 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + no description available + 0 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC30 + no description available + 4 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC29 + no description available + 8 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC28 + no description available + 12 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC27 + no description available + 16 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC26 + no description available + 20 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC25 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC24 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + OPAC33 + no description available + 24 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + OPAC32 + no description available + 28 + 4 + read-write + + + xxx0 + TP + #xxx0 + + + xxx1 + TP + #xxx1 + + + xx0x + WP + #xx0x + + + xx1x + WP + #xx1x + + + x0xx + SP + #x0xx + + + x1xx + SP + #x1xx + + + 1xxx + BW + #1xxx + + + + + + + + + SPDIF + SPDIF + SPDIF_ + 0x2004000 + + 0 + 0x54 + registers + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + 00 + No embedded U channel + #00 + + + 01 + U channel from SPDIF receive block (CD mode) + #01 + + + 10 + Reserved + #10 + + + 11 + U channel from on chip transmitter + #11 + + + + + TxSel + no description available + 2 + 3 + read-write + + + 000 + Off and output 0 + #000 + + + 001 + Feed-through SPDIFIN + #001 + + + 101 + Tx Normal operation + #101 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + 0 + Outgoing Validity always set + #0 + + + 1 + Outgoing Validity always clear + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + DMA_TX_En + no description available + 8 + 1 + read-write + + + DMA_Rx_En + no description available + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + 00 + Send out digital zero on SPDIF Tx + #00 + + + 01 + Tx Normal operation + #01 + + + 10 + Reset to 1 sample remaining + #10 + + + 11 + Reserved + #11 + + + + + soft_reset + no description available + 12 + 1 + read-write + + + LOW_POWER + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + 00 + Empty interrupt if 0 sample in Tx left and right FIFOs + #00 + + + 01 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + #01 + + + 10 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + #10 + + + 11 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + #11 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + 0 + Tx FIFO auto sync off + #0 + + + 1 + Tx FIFO auto sync on + #1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + 0 + Rx FIFO auto sync off + #0 + + + 1 + RxFIFO auto sync on + #1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + 00 + Full interrupt if at least 1 sample in Rx left and right FIFOs + #00 + + + 01 + Full interrupt if at least 4 sample in Rx left and right FIFOs + #01 + + + 10 + Full interrupt if at least 8 sample in Rx left and right FIFOs + #10 + + + 11 + Full interrupt if at least 16 sample in Rx left and right FIFO + #11 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Reset register to 1 sample remaining + #1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + 0 + SPDIF Rx FIFO is on + #0 + + + 1 + SPDIF Rx FIFO is off. Does not accept data from interface + #1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + 0 + Normal operation + #0 + + + 1 + Always read zero from Rx data register + #1 + + + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + USyncMode + no description available + 1 + 1 + read-write + + + 0 + Non-CD data + #0 + + + 1 + CD user channel subcode + #1 + + + + + RESERVED + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 5 + read-only + + + RESERVED + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 9 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + GainSel + no description available + 3 + 3 + read-write + + + 000 + 24*(2**10) + #000 + + + 001 + 16*(2**10) + #001 + + + 010 + 12*(2**10) + #010 + + + 011 + 8*(2**10) + #011 + + + 100 + 6*(2**10) + #100 + + + 101 + 4*(2**10) + #101 + + + 110 + 3*(2**10) + #110 + + + + + LOCK + no description available + 6 + 1 + read-only + + + ClkSrc_Sel + no description available + 7 + 4 + read-write + + + 0000 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + #0000 + + + 0001 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + #0001 + + + 0010 + if (DPLL Locked) SPDIF_RxClk else ASRC_EXT_CLK + #0010 + + + 0011 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + #0011 + + + 0100 + if (DPLL Locked) SPDIF_Rxclk else ESAI_HCKT + #0100 + + + 0101 + REF_CLK_32K (XTALOSC) + #0101 + + + 0110 + tx_clk (SPDIF0_CLK_ROOT) + #0110 + + + 0111 + ASRC_CLK + #0111 + + + 1000 + SPDIF_EXT_CLK + #1000 + + + 1001 + ESAI_HCKT + #1001 + + + 1010 + if (DPLL Locked) SPDIF_RxClk else MLB Clock + #1010 + + + 1011 + if (DPLL Locked) SPDIF_RxClk else MLB PHY Clock + #1011 + + + 1100 + MLB Clock + #1100 + + + 1101 + MLB PHY Clock + #1101 + + + + + RESERVED + no description available + 11 + 13 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + no description available + 0 + 1 + read-write + + + TxEm + no description available + 1 + 1 + read-write + + + LockLoss + no description available + 2 + 1 + read-write + + + RxFIFOResyn + no description available + 3 + 1 + read-write + + + RxFIFOUnOv + no description available + 4 + 1 + read-write + + + UQErr + no description available + 5 + 1 + read-write + + + UQSync + no description available + 6 + 1 + read-write + + + QRxOv + no description available + 7 + 1 + read-write + + + QRxFul + no description available + 8 + 1 + read-write + + + URxOv + no description available + 9 + 1 + read-write + + + URxFul + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 3 + read-only + + + BitErr + no description available + 14 + 1 + read-write + + + SymErr + no description available + 15 + 1 + read-write + + + ValNoGood + no description available + 16 + 1 + read-write + + + CNew + no description available + 17 + 1 + read-write + + + TxResyn + no description available + 18 + 1 + read-write + + + TxUnOv + no description available + 19 + 1 + read-write + + + Lock + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SIC + InterruptClear Register + SPDIF + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + LockLoss + no description available + 2 + 1 + write-only + + + RxFIFOResyn + no description available + 3 + 1 + write-only + + + RxFIFOUnOv + no description available + 4 + 1 + write-only + + + UQErr + no description available + 5 + 1 + write-only + + + UQSync + no description available + 6 + 1 + write-only + + + QRxOv + no description available + 7 + 1 + write-only + + + RESERVED + no description available + 8 + 1 + write-only + + + URxOv + no description available + 9 + 1 + write-only + + + RESERVED + no description available + 10 + 4 + read-only + + + BitErr + no description available + 14 + 1 + write-only + + + SymErr + no description available + 15 + 1 + write-only + + + ValNoGood + no description available + 16 + 1 + write-only + + + CNew + no description available + 17 + 1 + write-only + + + TxResyn + no description available + 18 + 1 + write-only + + + TxUnOv + no description available + 19 + 1 + write-only + + + Lock + no description available + 20 + 1 + write-only + + + RESERVED + no description available + 21 + 3 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SIS + InterruptStat Register + SPDIF + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + no description available + 0 + 1 + read-only + + + TxEm + no description available + 1 + 1 + read-only + + + LockLoss + no description available + 2 + 1 + read-only + + + RxFIFOResyn + no description available + 3 + 1 + read-only + + + RxFIFOUnOv + no description available + 4 + 1 + read-only + + + UQErr + no description available + 5 + 1 + read-only + + + UQSync + no description available + 6 + 1 + read-only + + + QRxOv + no description available + 7 + 1 + read-only + + + QRxFul + no description available + 8 + 1 + read-only + + + URxOv + no description available + 9 + 1 + read-only + + + URxFul + no description available + 10 + 1 + read-only + + + RESERVED + no description available + 11 + 3 + read-only + + + BitErr + no description available + 14 + 1 + read-only + + + SymErr + no description available + 15 + 1 + read-only + + + ValNoGood + no description available + 16 + 1 + read-only + + + CNew + no description available + 17 + 1 + read-only + + + TxResyn + no description available + 18 + 1 + read-only + + + TxUnOv + no description available + 19 + 1 + read-only + + + Lock + no description available + 20 + 1 + read-only + + + RESERVED + no description available + 21 + 3 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + no description available + 0 + 24 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + no description available + 0 + 24 + write-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + no description available + 0 + 24 + write-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + no description available + 0 + 7 + read-write + + + 0 + divider factor is 1 + #0 + + + 1 + divider factor is 2 + #1 + + + + + tx_all_clk_en + no description available + 7 + 1 + read-write + + + 0 + disable transfer clock. + #0 + + + 1 + enable transfer clock. + #1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + 000 + REF_CLK_32K input (XTALOSC 32kHz clock) + #000 + + + 001 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + #001 + + + 010 + ASRC_EXT_CLK input + #010 + + + 011 + SPDIF_EXT_CLK, from pads + #011 + + + 100 + ESAI_HCKT input + #100 + + + 101 + ipg_clk input (frequency divided) + #101 + + + 110 + MLB clock input + #110 + + + 111 + MLB PHY clock input + #111 + + + + + SYSCLK_DF + no description available + 11 + 9 + read-write + + + 0 + no clock signal + #0 + + + 1 + divider factor is 2 + #1 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + + + ECSPI1 + ECSPI + ECSPI + ECSPI1_ + 0x2008000 + + 0 + 0x44 + registers + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + no description available + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + no description available + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + Disable the block. + #0 + + + 1 + Enable the block. + #1 + + + + + HT + no description available + 1 + 1 + read-write + + + 0 + Disable HT mode. + #0 + + + 1 + Enable HT mode. + #1 + + + + + XCH + no description available + 2 + 1 + read-write + + + 0 + Idle. + #0 + + + 1 + Initiates exchange (write) or busy (read). + #1 + + + + + SMC + no description available + 3 + 1 + read-write + + + 0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + #0 + + + 1 + Immediately starts a SPI burst when data is written in TXFIFO. + #1 + + + + + CHANNEL_MODE + no description available + 4 + 4 + read-write + + + 0 + Slave mode. + #0 + + + 1 + Master mode. + #1 + + + + + POST_DIVIDER + no description available + 8 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 4. + #0010 + + + 1110 + Divide by 2 14 . + #1110 + + + 1111 + Divide by 2 15 . + #1111 + + + + + PRE_DIVIDER + no description available + 12 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 3. + #0010 + + + 1101 + Divide by 14. + #1101 + + + 1110 + Divide by 15. + #1110 + + + 1111 + Divide by 16. + #1111 + + + + + DRCTL + no description available + 16 + 2 + read-write + + + 00 + The SPI_RDY signal is a don't care. + #00 + + + 01 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + #01 + + + 10 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + #10 + + + 11 + Reserved. + #11 + + + + + CHANNEL_SELECT + no description available + 18 + 2 + read-write + + + 00 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + #00 + + + 01 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + #01 + + + 10 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + #10 + + + 11 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + #11 + + + + + BURST_LENGTH + no description available + 20 + 12 + read-write + + + 0 + A SPI burst contains the 1 LSB in a word. + #0 + + + 1 + A SPI burst contains the 2 LSB in a word. + #1 + + + 10 + A SPI burst contains the 3 LSB in a word. + #10 + + + 11111 + A SPI burst contains all 32 bits in a word. + #11111 + + + 100000 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + #100000 + + + 100001 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + #100001 + + + 111111111110 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + #111111111110 + + + 111111111111 + A SPI burst contains 2^7 words. + #111111111111 + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + no description available + 0 + 4 + read-write + + + 0 + Phase 0 operation. + #0 + + + 1 + Phase 1 operation. + #1 + + + + + SCLK_POL + no description available + 4 + 4 + read-write + + + 0 + Active high polarity (0 = Idle). + #0 + + + 1 + Active low polarity (1 = Idle). + #1 + + + + + SS_CTL + no description available + 8 + 4 + read-write + + + 0 + In master mode - only one SPI burst will be transmitted. + #0 + + + 1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + #1 + + + 0 + In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid. + #0 + + + 1 + In slave mode - an SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift register contains 32-bits of valid data. + #1 + + + + + SS_POL + no description available + 12 + 4 + read-write + + + 0 + Active low. + #0 + + + 1 + Active high. + #1 + + + + + DATA_CTL + no description available + 16 + 4 + read-write + + + 0 + Stay high. + #0 + + + 1 + Stay low. + #1 + + + + + SCLK_CTL + no description available + 20 + 4 + read-write + + + 0 + Stay low. + #0 + + + 1 + Stay high. + #1 + + + + + HT_LENGTH + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + no description available + 0 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TDREN + no description available + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TFEN + no description available + 2 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RREN + no description available + 3 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RDREN + no description available + 4 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RFEN + no description available + 5 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + ROEN + no description available + 6 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TCEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + TEDEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + RX_THRESHOLD + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + RXDEN + no description available + 23 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RX_DMA_LENGTH + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 1 + read-only + + + RXTDEN + no description available + 31 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + no description available + 0 + 1 + read-only + + + 0 + TXFIFO contains one or more words. + #0 + + + 1 + TXFIFO is empty. + #1 + + + + + TDR + no description available + 1 + 1 + read-only + + + 0 + Number of empty slots in TXFIFO is greater than TX_THRESHOLD. + #0 + + + 1 + Number of empty slots in TXFIFO is not greater than TX_THRESHOLD. + #1 + + + + + TF + no description available + 2 + 1 + read-only + + + 0 + TXFIFO is not Full. + #0 + + + 1 + TXFIFO is Full. + #1 + + + + + RR + no description available + 3 + 1 + read-only + + + 0 + No valid data in RXFIFO. + #0 + + + 1 + More than 1 word in RXFIFO. + #1 + + + + + RDR + no description available + 4 + 1 + read-only + + + 0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + #1 + + + 0 + When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + #1 + + + + + RF + no description available + 5 + 1 + read-only + + + 0 + Not Full. + #0 + + + 1 + Full. + #1 + + + + + RO + no description available + 6 + 1 + read-write + + + 0 + RXFIFO has no overflow. + #0 + + + 1 + RXFIFO has overflowed. + #1 + + + + + TC + no description available + 7 + 1 + read-write + + + 0 + Transfer in progress. + #0 + + + 1 + Transfer completed. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + no description available + 0 + 15 + read-write + + + 0 + 0 wait states inserted + #0 + + + 1 + 1 wait state inserted + #1 + + + 111111111111110 + 32766 wait states inserted + #111111111111110 + + + 111111111111111 + 32767 wait states inserted + #111111111111111 + + + + + CSRC + no description available + 15 + 1 + read-write + + + 0 + SPI Clock (SCLK) + #0 + + + 1 + Low-Frequency Reference Clock (32.768 KHz) + #1 + + + + + CSD_CTL + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RXCNT + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 13 + read-only + + + RESERVED + no description available + 28 + 3 + read-only + + + LBC + no description available + 31 + 1 + read-write + + + 0 + Not connected. + #0 + + + 1 + Transmitter and receiver sections internally connected for Loopback. + #1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + no description available + 0 + 32 + write-only + + + + + + + ECSPI2 + ECSPI + ECSPI + ECSPI2_ + 0x200C000 + + 0 + 0x44 + registers + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + no description available + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + no description available + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + Disable the block. + #0 + + + 1 + Enable the block. + #1 + + + + + HT + no description available + 1 + 1 + read-write + + + 0 + Disable HT mode. + #0 + + + 1 + Enable HT mode. + #1 + + + + + XCH + no description available + 2 + 1 + read-write + + + 0 + Idle. + #0 + + + 1 + Initiates exchange (write) or busy (read). + #1 + + + + + SMC + no description available + 3 + 1 + read-write + + + 0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + #0 + + + 1 + Immediately starts a SPI burst when data is written in TXFIFO. + #1 + + + + + CHANNEL_MODE + no description available + 4 + 4 + read-write + + + 0 + Slave mode. + #0 + + + 1 + Master mode. + #1 + + + + + POST_DIVIDER + no description available + 8 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 4. + #0010 + + + 1110 + Divide by 2 14 . + #1110 + + + 1111 + Divide by 2 15 . + #1111 + + + + + PRE_DIVIDER + no description available + 12 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 3. + #0010 + + + 1101 + Divide by 14. + #1101 + + + 1110 + Divide by 15. + #1110 + + + 1111 + Divide by 16. + #1111 + + + + + DRCTL + no description available + 16 + 2 + read-write + + + 00 + The SPI_RDY signal is a don't care. + #00 + + + 01 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + #01 + + + 10 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + #10 + + + 11 + Reserved. + #11 + + + + + CHANNEL_SELECT + no description available + 18 + 2 + read-write + + + 00 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + #00 + + + 01 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + #01 + + + 10 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + #10 + + + 11 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + #11 + + + + + BURST_LENGTH + no description available + 20 + 12 + read-write + + + 0 + A SPI burst contains the 1 LSB in a word. + #0 + + + 1 + A SPI burst contains the 2 LSB in a word. + #1 + + + 10 + A SPI burst contains the 3 LSB in a word. + #10 + + + 11111 + A SPI burst contains all 32 bits in a word. + #11111 + + + 100000 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + #100000 + + + 100001 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + #100001 + + + 111111111110 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + #111111111110 + + + 111111111111 + A SPI burst contains 2^7 words. + #111111111111 + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + no description available + 0 + 4 + read-write + + + 0 + Phase 0 operation. + #0 + + + 1 + Phase 1 operation. + #1 + + + + + SCLK_POL + no description available + 4 + 4 + read-write + + + 0 + Active high polarity (0 = Idle). + #0 + + + 1 + Active low polarity (1 = Idle). + #1 + + + + + SS_CTL + no description available + 8 + 4 + read-write + + + 0 + In master mode - only one SPI burst will be transmitted. + #0 + + + 1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + #1 + + + 0 + In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid. + #0 + + + 1 + In slave mode - an SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift register contains 32-bits of valid data. + #1 + + + + + SS_POL + no description available + 12 + 4 + read-write + + + 0 + Active low. + #0 + + + 1 + Active high. + #1 + + + + + DATA_CTL + no description available + 16 + 4 + read-write + + + 0 + Stay high. + #0 + + + 1 + Stay low. + #1 + + + + + SCLK_CTL + no description available + 20 + 4 + read-write + + + 0 + Stay low. + #0 + + + 1 + Stay high. + #1 + + + + + HT_LENGTH + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + no description available + 0 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TDREN + no description available + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TFEN + no description available + 2 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RREN + no description available + 3 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RDREN + no description available + 4 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RFEN + no description available + 5 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + ROEN + no description available + 6 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TCEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + TEDEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + RX_THRESHOLD + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + RXDEN + no description available + 23 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RX_DMA_LENGTH + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 1 + read-only + + + RXTDEN + no description available + 31 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + no description available + 0 + 1 + read-only + + + 0 + TXFIFO contains one or more words. + #0 + + + 1 + TXFIFO is empty. + #1 + + + + + TDR + no description available + 1 + 1 + read-only + + + 0 + Number of empty slots in TXFIFO is greater than TX_THRESHOLD. + #0 + + + 1 + Number of empty slots in TXFIFO is not greater than TX_THRESHOLD. + #1 + + + + + TF + no description available + 2 + 1 + read-only + + + 0 + TXFIFO is not Full. + #0 + + + 1 + TXFIFO is Full. + #1 + + + + + RR + no description available + 3 + 1 + read-only + + + 0 + No valid data in RXFIFO. + #0 + + + 1 + More than 1 word in RXFIFO. + #1 + + + + + RDR + no description available + 4 + 1 + read-only + + + 0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + #1 + + + 0 + When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + #1 + + + + + RF + no description available + 5 + 1 + read-only + + + 0 + Not Full. + #0 + + + 1 + Full. + #1 + + + + + RO + no description available + 6 + 1 + read-write + + + 0 + RXFIFO has no overflow. + #0 + + + 1 + RXFIFO has overflowed. + #1 + + + + + TC + no description available + 7 + 1 + read-write + + + 0 + Transfer in progress. + #0 + + + 1 + Transfer completed. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + no description available + 0 + 15 + read-write + + + 0 + 0 wait states inserted + #0 + + + 1 + 1 wait state inserted + #1 + + + 111111111111110 + 32766 wait states inserted + #111111111111110 + + + 111111111111111 + 32767 wait states inserted + #111111111111111 + + + + + CSRC + no description available + 15 + 1 + read-write + + + 0 + SPI Clock (SCLK) + #0 + + + 1 + Low-Frequency Reference Clock (32.768 KHz) + #1 + + + + + CSD_CTL + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RXCNT + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 13 + read-only + + + RESERVED + no description available + 28 + 3 + read-only + + + LBC + no description available + 31 + 1 + read-write + + + 0 + Not connected. + #0 + + + 1 + Transmitter and receiver sections internally connected for Loopback. + #1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + no description available + 0 + 32 + write-only + + + + + + + ECSPI3 + ECSPI + ECSPI + ECSPI3_ + 0x2010000 + + 0 + 0x44 + registers + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + no description available + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + no description available + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + Disable the block. + #0 + + + 1 + Enable the block. + #1 + + + + + HT + no description available + 1 + 1 + read-write + + + 0 + Disable HT mode. + #0 + + + 1 + Enable HT mode. + #1 + + + + + XCH + no description available + 2 + 1 + read-write + + + 0 + Idle. + #0 + + + 1 + Initiates exchange (write) or busy (read). + #1 + + + + + SMC + no description available + 3 + 1 + read-write + + + 0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + #0 + + + 1 + Immediately starts a SPI burst when data is written in TXFIFO. + #1 + + + + + CHANNEL_MODE + no description available + 4 + 4 + read-write + + + 0 + Slave mode. + #0 + + + 1 + Master mode. + #1 + + + + + POST_DIVIDER + no description available + 8 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 4. + #0010 + + + 1110 + Divide by 2 14 . + #1110 + + + 1111 + Divide by 2 15 . + #1111 + + + + + PRE_DIVIDER + no description available + 12 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 3. + #0010 + + + 1101 + Divide by 14. + #1101 + + + 1110 + Divide by 15. + #1110 + + + 1111 + Divide by 16. + #1111 + + + + + DRCTL + no description available + 16 + 2 + read-write + + + 00 + The SPI_RDY signal is a don't care. + #00 + + + 01 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + #01 + + + 10 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + #10 + + + 11 + Reserved. + #11 + + + + + CHANNEL_SELECT + no description available + 18 + 2 + read-write + + + 00 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + #00 + + + 01 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + #01 + + + 10 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + #10 + + + 11 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + #11 + + + + + BURST_LENGTH + no description available + 20 + 12 + read-write + + + 0 + A SPI burst contains the 1 LSB in a word. + #0 + + + 1 + A SPI burst contains the 2 LSB in a word. + #1 + + + 10 + A SPI burst contains the 3 LSB in a word. + #10 + + + 11111 + A SPI burst contains all 32 bits in a word. + #11111 + + + 100000 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + #100000 + + + 100001 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + #100001 + + + 111111111110 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + #111111111110 + + + 111111111111 + A SPI burst contains 2^7 words. + #111111111111 + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + no description available + 0 + 4 + read-write + + + 0 + Phase 0 operation. + #0 + + + 1 + Phase 1 operation. + #1 + + + + + SCLK_POL + no description available + 4 + 4 + read-write + + + 0 + Active high polarity (0 = Idle). + #0 + + + 1 + Active low polarity (1 = Idle). + #1 + + + + + SS_CTL + no description available + 8 + 4 + read-write + + + 0 + In master mode - only one SPI burst will be transmitted. + #0 + + + 1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + #1 + + + 0 + In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid. + #0 + + + 1 + In slave mode - an SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift register contains 32-bits of valid data. + #1 + + + + + SS_POL + no description available + 12 + 4 + read-write + + + 0 + Active low. + #0 + + + 1 + Active high. + #1 + + + + + DATA_CTL + no description available + 16 + 4 + read-write + + + 0 + Stay high. + #0 + + + 1 + Stay low. + #1 + + + + + SCLK_CTL + no description available + 20 + 4 + read-write + + + 0 + Stay low. + #0 + + + 1 + Stay high. + #1 + + + + + HT_LENGTH + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + no description available + 0 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TDREN + no description available + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TFEN + no description available + 2 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RREN + no description available + 3 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RDREN + no description available + 4 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RFEN + no description available + 5 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + ROEN + no description available + 6 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TCEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + TEDEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + RX_THRESHOLD + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + RXDEN + no description available + 23 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RX_DMA_LENGTH + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 1 + read-only + + + RXTDEN + no description available + 31 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + no description available + 0 + 1 + read-only + + + 0 + TXFIFO contains one or more words. + #0 + + + 1 + TXFIFO is empty. + #1 + + + + + TDR + no description available + 1 + 1 + read-only + + + 0 + Number of empty slots in TXFIFO is greater than TX_THRESHOLD. + #0 + + + 1 + Number of empty slots in TXFIFO is not greater than TX_THRESHOLD. + #1 + + + + + TF + no description available + 2 + 1 + read-only + + + 0 + TXFIFO is not Full. + #0 + + + 1 + TXFIFO is Full. + #1 + + + + + RR + no description available + 3 + 1 + read-only + + + 0 + No valid data in RXFIFO. + #0 + + + 1 + More than 1 word in RXFIFO. + #1 + + + + + RDR + no description available + 4 + 1 + read-only + + + 0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + #1 + + + 0 + When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + #1 + + + + + RF + no description available + 5 + 1 + read-only + + + 0 + Not Full. + #0 + + + 1 + Full. + #1 + + + + + RO + no description available + 6 + 1 + read-write + + + 0 + RXFIFO has no overflow. + #0 + + + 1 + RXFIFO has overflowed. + #1 + + + + + TC + no description available + 7 + 1 + read-write + + + 0 + Transfer in progress. + #0 + + + 1 + Transfer completed. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + no description available + 0 + 15 + read-write + + + 0 + 0 wait states inserted + #0 + + + 1 + 1 wait state inserted + #1 + + + 111111111111110 + 32766 wait states inserted + #111111111111110 + + + 111111111111111 + 32767 wait states inserted + #111111111111111 + + + + + CSRC + no description available + 15 + 1 + read-write + + + 0 + SPI Clock (SCLK) + #0 + + + 1 + Low-Frequency Reference Clock (32.768 KHz) + #1 + + + + + CSD_CTL + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RXCNT + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 13 + read-only + + + RESERVED + no description available + 28 + 3 + read-only + + + LBC + no description available + 31 + 1 + read-write + + + 0 + Not connected. + #0 + + + 1 + Transmitter and receiver sections internally connected for Loopback. + #1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + no description available + 0 + 32 + write-only + + + + + + + ECSPI4 + ECSPI + ECSPI + ECSPI4_ + 0x2014000 + + 0 + 0x44 + registers + + + + RXDATA + Receive Data Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ECSPI_RXDATA + no description available + 0 + 32 + read-only + + + + + TXDATA + Transmit Data Register + 0x4 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_TXDATA + no description available + 0 + 32 + write-only + + + + + CONREG + Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + Disable the block. + #0 + + + 1 + Enable the block. + #1 + + + + + HT + no description available + 1 + 1 + read-write + + + 0 + Disable HT mode. + #0 + + + 1 + Enable HT mode. + #1 + + + + + XCH + no description available + 2 + 1 + read-write + + + 0 + Idle. + #0 + + + 1 + Initiates exchange (write) or busy (read). + #1 + + + + + SMC + no description available + 3 + 1 + read-write + + + 0 + SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions. + #0 + + + 1 + Immediately starts a SPI burst when data is written in TXFIFO. + #1 + + + + + CHANNEL_MODE + no description available + 4 + 4 + read-write + + + 0 + Slave mode. + #0 + + + 1 + Master mode. + #1 + + + + + POST_DIVIDER + no description available + 8 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 4. + #0010 + + + 1110 + Divide by 2 14 . + #1110 + + + 1111 + Divide by 2 15 . + #1111 + + + + + PRE_DIVIDER + no description available + 12 + 4 + read-write + + + 0000 + Divide by 1. + #0000 + + + 0001 + Divide by 2. + #0001 + + + 0010 + Divide by 3. + #0010 + + + 1101 + Divide by 14. + #1101 + + + 1110 + Divide by 15. + #1110 + + + 1111 + Divide by 16. + #1111 + + + + + DRCTL + no description available + 16 + 2 + read-write + + + 00 + The SPI_RDY signal is a don't care. + #00 + + + 01 + Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered). + #01 + + + 10 + Burst will be triggered by a low level of the SPI_RDY signal (level-triggered). + #10 + + + 11 + Reserved. + #11 + + + + + CHANNEL_SELECT + no description available + 18 + 2 + read-write + + + 00 + Channel 0 is selected. Chip Select 0 (SS0) will be asserted. + #00 + + + 01 + Channel 1 is selected. Chip Select 1 (SS1) will be asserted. + #01 + + + 10 + Channel 2 is selected. Chip Select 2 (SS2) will be asserted. + #10 + + + 11 + Channel 3 is selected. Chip Select 3 (SS3) will be asserted. + #11 + + + + + BURST_LENGTH + no description available + 20 + 12 + read-write + + + 0 + A SPI burst contains the 1 LSB in a word. + #0 + + + 1 + A SPI burst contains the 2 LSB in a word. + #1 + + + 10 + A SPI burst contains the 3 LSB in a word. + #10 + + + 11111 + A SPI burst contains all 32 bits in a word. + #11111 + + + 100000 + A SPI burst contains the 1 LSB in first word and all 32 bits in second word. + #100000 + + + 100001 + A SPI burst contains the 2 LSB in first word and all 32 bits in second word. + #100001 + + + 111111111110 + A SPI burst contains the 31 LSB in first word and 2^7 -1 words. + #111111111110 + + + 111111111111 + A SPI burst contains 2^7 words. + #111111111111 + + + + + + + CONFIGREG + Config Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SCLK_PHA + no description available + 0 + 4 + read-write + + + 0 + Phase 0 operation. + #0 + + + 1 + Phase 1 operation. + #1 + + + + + SCLK_POL + no description available + 4 + 4 + read-write + + + 0 + Active high polarity (0 = Idle). + #0 + + + 1 + Active low polarity (1 = Idle). + #1 + + + + + SS_CTL + no description available + 8 + 4 + read-write + + + 0 + In master mode - only one SPI burst will be transmitted. + #0 + + + 1 + In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty. + #1 + + + 0 + In slave mode - an SPI burst is completed when the number of bits received in the shift register is equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first received word are valid. All bits subsequent to the first received word in RXFIFO are valid. + #0 + + + 1 + In slave mode - an SPI burst is completed by the Chip Select (SS) signal edges. (SSPOL = 0: rising edge; SSPOL = 1: falling edge) The RXFIFO is advanced whenever a Chip Select (SS) signal edge is detected or the shift register contains 32-bits of valid data. + #1 + + + + + SS_POL + no description available + 12 + 4 + read-write + + + 0 + Active low. + #0 + + + 1 + Active high. + #1 + + + + + DATA_CTL + no description available + 16 + 4 + read-write + + + 0 + Stay high. + #0 + + + 1 + Stay low. + #1 + + + + + SCLK_CTL + no description available + 20 + 4 + read-write + + + 0 + Stay low. + #0 + + + 1 + Stay high. + #1 + + + + + HT_LENGTH + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INTREG + Interrupt Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEEN + no description available + 0 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TDREN + no description available + 1 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TFEN + no description available + 2 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RREN + no description available + 3 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RDREN + no description available + 4 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RFEN + no description available + 5 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + ROEN + no description available + 6 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + TCEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DMAREG + DMA Control Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_THRESHOLD + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + TEDEN + no description available + 7 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + RX_THRESHOLD + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 1 + read-only + + + RXDEN + no description available + 23 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + RX_DMA_LENGTH + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 1 + read-only + + + RXTDEN + no description available + 31 + 1 + read-write + + + 0 + Disable + #0 + + + 1 + Enable + #1 + + + + + + + STATREG + Status Register + 0x18 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + TE + no description available + 0 + 1 + read-only + + + 0 + TXFIFO contains one or more words. + #0 + + + 1 + TXFIFO is empty. + #1 + + + + + TDR + no description available + 1 + 1 + read-only + + + 0 + Number of empty slots in TXFIFO is greater than TX_THRESHOLD. + #0 + + + 1 + Number of empty slots in TXFIFO is not greater than TX_THRESHOLD. + #1 + + + + + TF + no description available + 2 + 1 + read-only + + + 0 + TXFIFO is not Full. + #0 + + + 1 + TXFIFO is Full. + #1 + + + + + RR + no description available + 3 + 1 + read-only + + + 0 + No valid data in RXFIFO. + #0 + + + 1 + More than 1 word in RXFIFO. + #1 + + + + + RDR + no description available + 4 + 1 + read-only + + + 0 + When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists. + #1 + + + 0 + When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD. + #0 + + + 1 + When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD. + #1 + + + + + RF + no description available + 5 + 1 + read-only + + + 0 + Not Full. + #0 + + + 1 + Full. + #1 + + + + + RO + no description available + 6 + 1 + read-write + + + 0 + RXFIFO has no overflow. + #0 + + + 1 + RXFIFO has overflowed. + #1 + + + + + TC + no description available + 7 + 1 + read-write + + + 0 + Transfer in progress. + #0 + + + 1 + Transfer completed. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + PERIODREG + Sample Period Control Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE_PERIOD + no description available + 0 + 15 + read-write + + + 0 + 0 wait states inserted + #0 + + + 1 + 1 wait state inserted + #1 + + + 111111111111110 + 32766 wait states inserted + #111111111111110 + + + 111111111111111 + 32767 wait states inserted + #111111111111111 + + + + + CSRC + no description available + 15 + 1 + read-write + + + 0 + SPI Clock (SCLK) + #0 + + + 1 + Low-Frequency Reference Clock (32.768 KHz) + #1 + + + + + CSD_CTL + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + TESTREG + Test Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCNT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RXCNT + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 13 + read-only + + + RESERVED + no description available + 28 + 3 + read-only + + + LBC + no description available + 31 + 1 + read-write + + + 0 + Not connected. + #0 + + + 1 + Transmitter and receiver sections internally connected for Loopback. + #1 + + + + + + + MSGDATA + Message Data Register + 0x40 + 32 + write-only + 0 + 0xFFFFFFFF + + + ECSPI_MSGDATA + no description available + 0 + 32 + write-only + + + + + + + UART1 + UARTv2 + UART + UART1_ + 0x2020000 + + 0 + 0xBC + registers + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 2 + read-only + + + PRERR + no description available + 10 + 1 + read-only + + + 0 + = No parity error was detected for data in the RX_DATA field + #0 + + + 1 + = A parity error was detected for data in the RX_DATA field + #1 + + + + + BRK + no description available + 11 + 1 + read-only + + + 0 + The current character is not a BREAK character + #0 + + + 1 + The current character is a BREAK character + #1 + + + + + FRMERR + no description available + 12 + 1 + read-only + + + 0 + The current character has no framing error + #0 + + + 1 + The current character has a framing error + #1 + + + + + OVRRUN + no description available + 13 + 1 + read-only + + + 0 + No RxFIFO overrun was detected + #0 + + + 1 + A RxFIFO overrun was detected + #1 + + + + + ERR + no description available + 14 + 1 + read-only + + + 0 + No error status was detected + #0 + + + 1 + An error status was detected + #1 + + + + + CHARRDY + no description available + 15 + 1 + read-only + + + 0 + Character in RX_DATA field and associated flags are invalid. + #0 + + + 1 + Character in RX_DATA field and associated flags valid and ready for reading. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + no description available + 0 + 8 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + no description available + 0 + 1 + read-write + + + 0 + Disable the UART + #0 + + + 1 + Enable the UART + #1 + + + + + DOZE + no description available + 1 + 1 + read-write + + + 0 + The UART is enabled when in DOZE state + #0 + + + 1 + The UART is disabled when in DOZE state + #1 + + + + + ATDMAEN + no description available + 2 + 1 + read-write + + + 0 + Disable AGTIM DMA request + #0 + + + 1 + Enable AGTIM DMA request + #1 + + + + + TXDMAEN + no description available + 3 + 1 + read-write + + + 0 + Disable transmit DMA request + #0 + + + 1 + Enable transmit DMA request + #1 + + + + + SNDBRK + no description available + 4 + 1 + read-write + + + 0 + Do not send a BREAK character + #0 + + + 1 + Send a BREAK character (continuous 0s) + #1 + + + + + RTSDEN + no description available + 5 + 1 + read-write + + + 0 + Disable RTSD interrupt + #0 + + + 1 + Enable RTSD interrupt + #1 + + + + + TXMPTYEN + no description available + 6 + 1 + read-write + + + 0 + Disable the transmitter FIFO empty interrupt + #0 + + + 1 + Enable the transmitter FIFO empty interrupt + #1 + + + + + IREN + no description available + 7 + 1 + read-write + + + 0 + Disable the IR interface + #0 + + + 1 + Enable the IR interface + #1 + + + + + RXDMAEN + no description available + 8 + 1 + read-write + + + 0 + Disable DMA request + #0 + + + 1 + Enable DMA request + #1 + + + + + RRDYEN + no description available + 9 + 1 + read-write + + + 0 + Disables the RRDY interrupt + #0 + + + 1 + Enables the RRDY interrupt + #1 + + + + + ICD + no description available + 10 + 2 + read-write + + + 00 + Idle for more than 4 frames + #00 + + + 01 + Idle for more than 8 frames + #01 + + + 10 + Idle for more than 16 frames + #10 + + + 11 + Idle for more than 32 frames + #11 + + + + + IDEN + no description available + 12 + 1 + read-write + + + 0 + Disable the IDLE interrupt + #0 + + + 1 + Enable the IDLE interrupt + #1 + + + + + TRDYEN + no description available + 13 + 1 + read-write + + + 0 + Disable the transmitter ready interrupt + #0 + + + 1 + Enable the transmitter ready interrupt + #1 + + + + + ADBR + no description available + 14 + 1 + read-write + + + 0 + Disable automatic detection of baud rate + #0 + + + 1 + Enable automatic detection of baud rate + #1 + + + + + ADEN + no description available + 15 + 1 + read-write + + + 0 + Disable the automatic baud rate detection interrupt + #0 + + + 1 + Enable the automatic baud rate detection interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + no description available + 0 + 1 + read-write + + + 0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + #0 + + + 1 + No reset + #1 + + + + + RXEN + no description available + 1 + 1 + read-write + + + 0 + Disable the receiver + #0 + + + 1 + Enable the receiver + #1 + + + + + TXEN + no description available + 2 + 1 + read-write + + + 0 + Disable the transmitter + #0 + + + 1 + Enable the transmitter + #1 + + + + + ATEN + no description available + 3 + 1 + read-write + + + 0 + AGTIM interrupt disabled + #0 + + + 1 + AGTIM interrupt enabled + #1 + + + + + RTSEN + no description available + 4 + 1 + read-write + + + 0 + Disable request to send interrupt + #0 + + + 1 + Enable request to send interrupt + #1 + + + + + WS + no description available + 5 + 1 + read-write + + + 0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + #0 + + + 1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + #1 + + + + + STPB + no description available + 6 + 1 + read-write + + + 0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + #0 + + + 1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + #1 + + + + + PROE + no description available + 7 + 1 + read-write + + + 0 + Even parity + #0 + + + 1 + Odd parity + #1 + + + + + PREN + no description available + 8 + 1 + read-write + + + 0 + Disable parity generator and checker + #0 + + + 1 + Enable parity generator and checker + #1 + + + + + RTEC + no description available + 9 + 2 + read-write + + + 00 + Trigger interrupt on a rising edge + #00 + + + 01 + Trigger interrupt on a falling edge + #01 + + + + + ESCEN + no description available + 11 + 1 + read-write + + + 0 + Disable escape sequence detection + #0 + + + 1 + Enable escape sequence detection + #1 + + + + + CTS + no description available + 12 + 1 + read-write + + + 0 + The CTS_B pin is high (inactive) + #0 + + + 1 + The CTS_B pin is low (active) + #1 + + + + + CTSC + no description available + 13 + 1 + read-write + + + 0 + The CTS_B pin is controlled by the CTS bit + #0 + + + 1 + The CTS_B pin is controlled by the receiver + #1 + + + + + IRTS + no description available + 14 + 1 + read-write + + + 0 + Transmit only when the RTS pin is asserted + #0 + + + 1 + Ignore the RTS pin + #1 + + + + + ESCI + no description available + 15 + 1 + read-write + + + 0 + Disable the escape sequence interrupt + #0 + + + 1 + Enable the escape sequence interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + no description available + 0 + 1 + read-write + + + 0 + ACST interrupt disabled + #0 + + + 1 + ACST interrupt enabled + #1 + + + + + INVT + no description available + 1 + 1 + read-write + + + 0 + TXD is not inverted + #0 + + + 1 + TXD is inverted + #1 + + + 0 + TXD Active low transmission + #0 + + + 1 + TXD Active high transmission + #1 + + + + + RXDMUXSEL + no description available + 2 + 1 + read-write + + + DTRDEN + no description available + 3 + 1 + read-write + + + 0 + Disable DTRD interrupt + #0 + + + 1 + Enable DTRD interrupt + #1 + + + + + AWAKEN + no description available + 4 + 1 + read-write + + + 0 + Disable the AWAKE interrupt + #0 + + + 1 + Enable the AWAKE interrupt + #1 + + + + + AIRINTEN + no description available + 5 + 1 + read-write + + + 0 + Disable the AIRINT interrupt + #0 + + + 1 + Enable the AIRINT interrupt + #1 + + + + + RXDSEN + no description available + 6 + 1 + read-write + + + 0 + Disable the RXDS interrupt + #0 + + + 1 + Enable the RXDS interrupt + #1 + + + + + ADNIMP + no description available + 7 + 1 + read-write + + + 0 + Autobaud detection new features selected + #0 + + + 1 + Keep old autobaud detection mechanism + #1 + + + + + RI + no description available + 8 + 1 + read-write + + + 0 + RI_B pin is logic zero (DCE mode) + #0 + + + 1 + RI_B pin is logic one (DCE mode) + #1 + + + 0 + RIDELT interrupt disabled (DTE mode) + #0 + + + 1 + RIDELT interrupt enabled (DTE mode) + #1 + + + + + DCD + no description available + 9 + 1 + read-write + + + 0 + DCD_B pin is logic zero (DCE mode) + #0 + + + 1 + DCD_B pin is logic one (DCE mode) + #1 + + + 0 + DCDDELT interrupt disabled (DTE mode) + #0 + + + 1 + DCDDELT interrupt enabled (DTE mode) + #1 + + + + + DSR + no description available + 10 + 1 + read-write + + + 0 + DSR/ DTR pin is logic zero + #0 + + + 1 + DSR/ DTR pin is logic one + #1 + + + + + FRAERREN + no description available + 11 + 1 + read-write + + + 0 + Disable the frame error interrupt + #0 + + + 1 + Enable the frame error interrupt + #1 + + + + + PARERREN + no description available + 12 + 1 + read-write + + + 0 + Disable the parity error interrupt + #0 + + + 1 + Enable the parity error interrupt + #1 + + + + + DTREN + no description available + 13 + 1 + read-write + + + 0 + Data Terminal Ready Interrupt Disabled + #0 + + + 1 + Data Terminal Ready Interrupt Enabled + #1 + + + + + DPEC + no description available + 14 + 2 + read-write + + + 00 + interrupt generated on rising edge + #00 + + + 01 + interrupt generated on falling edge + #01 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + no description available + 0 + 1 + read-write + + + 0 + Disable RDR interrupt + #0 + + + 1 + Enable RDR interrupt + #1 + + + + + OREN + no description available + 1 + 1 + read-write + + + 0 + Disable ORE interrupt + #0 + + + 1 + Enable ORE interrupt + #1 + + + + + BKEN + no description available + 2 + 1 + read-write + + + 0 + Disable the BRCD interrupt + #0 + + + 1 + Enable the BRCD interrupt + #1 + + + + + TCEN + no description available + 3 + 1 + read-write + + + 0 + Disable TXDC interrupt + #0 + + + 1 + Enable TXDC interrupt + #1 + + + + + LPBYP + no description available + 4 + 1 + read-write + + + 0 + Low power features enabled + #0 + + + 1 + Low power features disabled + #1 + + + + + IRSC + no description available + 5 + 1 + read-write + + + 0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + #0 + + + 1 + The vote logic uses the UART reference clock + #1 + + + + + IDDMAEN + no description available + 6 + 1 + read-write + + + 0 + DMA IDLE interrupt disabled + #0 + + + 1 + DMA IDLE interrupt enabled + #1 + + + + + WKEN + no description available + 7 + 1 + read-write + + + 0 + Disable the WAKE interrupt + #0 + + + 1 + Enable the WAKE interrupt + #1 + + + + + ENIRI + no description available + 8 + 1 + read-write + + + 0 + Serial infrared Interrupt disabled + #0 + + + 1 + Serial infrared Interrupt enabled + #1 + + + + + INVR + no description available + 9 + 1 + read-write + + + 0 + RXD input is not inverted + #0 + + + 1 + RXD input is inverted + #1 + + + 0 + RXD active low detection + #0 + + + 1 + RXD active high detection + #1 + + + + + CTSTL + no description available + 10 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + 1 characters in the RxFIFO + #000001 + + + 100000 + 32 characters in the RxFIFO (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + no description available + 0 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + RxFIFO has 1 character + #000001 + + + 011111 + RxFIFO has 31 characters + #011111 + + + 100000 + RxFIFO has 32 characters (maximum) + #100000 + + + + + DCEDTE + no description available + 6 + 1 + read-write + + + 0 + DCE mode selected + #0 + + + 1 + DTE mode selected + #1 + + + + + RFDIV + no description available + 7 + 3 + read-write + + + 000 + Divide input clock by 6 + #000 + + + 001 + Divide input clock by 5 + #001 + + + 010 + Divide input clock by 4 + #010 + + + 011 + Divide input clock by 3 + #011 + + + 100 + Divide input clock by 2 + #100 + + + 101 + Divide input clock by 1 + #101 + + + 110 + Divide input clock by 7 + #110 + + + 111 + Reserved + #111 + + + + + TXTL + no description available + 10 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + Reserved + #000001 + + + 000010 + TxFIFO has 2 or fewer characters + #000010 + + + 011111 + TxFIFO has 31 or fewer characters + #011111 + + + 100000 + TxFIFO has 32 characters (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + SAD + no description available + 3 + 1 + read-write + + + 0 + No slave address detected + #0 + + + 1 + Slave address detected + #1 + + + + + AWAKE + no description available + 4 + 1 + read-write + + + 0 + No falling edge was detected on the RXD Serial pin + #0 + + + 1 + A falling edge was detected on the RXD Serial pin + #1 + + + + + AIRINT + no description available + 5 + 1 + read-write + + + 0 + No pulse was detected on the RXD IrDA pin + #0 + + + 1 + A pulse was detected on the RXD IrDA pin + #1 + + + + + RXDS + no description available + 6 + 1 + read-only + + + 0 + Receive in progress + #0 + + + 1 + Receiver is IDLE + #1 + + + + + DTRD + no description available + 7 + 1 + read-write + + + 0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + #0 + + + 1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + #1 + + + + + AGTIM + no description available + 8 + 1 + read-write + + + 0 + AGTIM is not active + #0 + + + 1 + AGTIM is active (write 1 to clear) + #1 + + + + + RRDY + no description available + 9 + 1 + read-only + + + 0 + No character ready + #0 + + + 1 + Character(s) ready (interrupt posted) + #1 + + + + + FRAMERR + no description available + 10 + 1 + read-write + + + 0 + No frame error detected + #0 + + + 1 + Frame error detected (write 1 to clear) + #1 + + + + + ESCF + no description available + 11 + 1 + read-write + + + 0 + No escape sequence detected + #0 + + + 1 + Escape sequence detected (write 1 to clear). + #1 + + + + + RTSD + no description available + 12 + 1 + read-write + + + 0 + RTS_B pin did not change state since last cleared + #0 + + + 1 + RTS_B pin changed state (write 1 to clear) + #1 + + + + + TRDY + no description available + 13 + 1 + read-only + + + 0 + The transmitter does not require data + #0 + + + 1 + The transmitter requires data (interrupt posted) + #1 + + + + + RTSS + no description available + 14 + 1 + read-only + + + 0 + The RTS_B pin is high (inactive) + #0 + + + 1 + The RTS_B pin is low (active) + #1 + + + + + PARITYERR + no description available + 15 + 1 + read-write + + + 0 + No parity error detected + #0 + + + 1 + Parity error detected (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + no description available + 0 + 1 + read-only + + + 0 + No receive data ready + #0 + + + 1 + Receive data ready + #1 + + + + + ORE + no description available + 1 + 1 + read-write + + + 0 + No overrun error + #0 + + + 1 + Overrun error (write 1 to clear) + #1 + + + + + BRCD + no description available + 2 + 1 + read-write + + + 0 + No BREAK condition was detected + #0 + + + 1 + A BREAK condition was detected (write 1 to clear) + #1 + + + + + TXDC + no description available + 3 + 1 + read-only + + + 0 + Transmit is incomplete + #0 + + + 1 + Transmit is complete + #1 + + + + + RTSF + no description available + 4 + 1 + read-write + + + 0 + Programmed edge not detected on RTS_B + #0 + + + 1 + Programmed edge detected on RTS_B (write 1 to clear) + #1 + + + + + DCDIN + no description available + 5 + 1 + read-only + + + 0 + Carrier signal Detected + #0 + + + 1 + No Carrier signal Detected + #1 + + + + + DCDDELT + no description available + 6 + 1 + read-write + + + 0 + Data Carrier Detect input has not changed state + #0 + + + 1 + Data Carrier Detect input has changed state (write 1 to clear) + #1 + + + + + WAKE + no description available + 7 + 1 + read-write + + + 0 + start bit not detected + #0 + + + 1 + start bit detected (write 1 to clear) + #1 + + + + + IRINT + no description available + 8 + 1 + read-write + + + 0 + no edge detected + #0 + + + 1 + valid edge detected (write 1 to clear) + #1 + + + + + RIIN + no description available + 9 + 1 + read-only + + + 0 + Ring Detected + #0 + + + 1 + No Ring Detected + #1 + + + + + RIDELT + no description available + 10 + 1 + read-write + + + 0 + Ring Indicator input has not changed state + #0 + + + 1 + Ring Indicator input has changed state (write 1 to clear) + #1 + + + + + ACST + no description available + 11 + 1 + read-write + + + 0 + Measurement of bit length not finished (in autobaud) + #0 + + + 1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + #1 + + + + + IDLE + no description available + 12 + 1 + read-write + + + 0 + No idle condition detected + #0 + + + 1 + Idle condition detected (write 1 to clear) + #1 + + + + + DTRF + no description available + 13 + 1 + read-write + + + 0 + Programmed edge not detected on DTR/DSR + #0 + + + 1 + Programmed edge detected on DTR/DSR (write 1 to clear) + #1 + + + + + TXFE + no description available + 14 + 1 + read-only + + + 0 + The transmit buffer (TxFIFO) is not empty + #0 + + + 1 + The transmit buffer (TxFIFO) is empty + #1 + + + + + ADET + no description available + 15 + 1 + read-write + + + 0 + ASCII "A" or "a" was not received + #0 + + + 1 + ASCII "A" or "a" was received (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + no description available + 0 + 1 + read-write + + + 0 + Software reset inactive + #0 + + + 1 + Software reset active + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + RXFULL + no description available + 3 + 1 + read-write + + + 0 + The RxFIFO is not full + #0 + + + 1 + The RxFIFO is full + #1 + + + + + TXFULL + no description available + 4 + 1 + read-write + + + 0 + The TxFIFO is not full + #0 + + + 1 + The TxFIFO is full + #1 + + + + + RXEMPTY + no description available + 5 + 1 + read-write + + + 0 + The RxFIFO is not empty + #0 + + + 1 + The RxFIFO is empty + #1 + + + + + TXEMPTY + no description available + 6 + 1 + read-write + + + 0 + The TxFIFO is not empty + #0 + + + 1 + The TxFIFO is empty + #1 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + RXDBG + no description available + 9 + 1 + read-write + + + 0 + rx fifo read pointer does not increment + #0 + + + 1 + rx_fifo read pointer increments as normal + #1 + + + + + LOOPIR + no description available + 10 + 1 + read-write + + + 0 + No IR loop + #0 + + + 1 + Connect IR transmitter to IR receiver + #1 + + + + + DBGEN + no description available + 11 + 1 + read-write + + + 0 + UART will go into debug mode when debug_req is HIGH + #0 + + + 1 + UART will not go into debug mode even if debug_req is HIGH + #1 + + + + + LOOP + no description available + 12 + 1 + read-write + + + 0 + Normal receiver operation + #0 + + + 1 + Internally connect the transmitter output to the receiver input + #1 + + + + + FRCPERR + no description available + 13 + 1 + read-write + + + 0 + Generate normal parity + #0 + + + 1 + Generate inverted parity (error) + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + no description available + 0 + 1 + read-write + + + 0 + Normal RS-232 or IrDA mode, see for detail. + #0 + + + 1 + Enable RS-485 mode, see for detail + #1 + + + + + SLAM + no description available + 1 + 1 + read-write + + + 0 + Select Normal Address Detect mode + #0 + + + 1 + Select Automatic Address Detect mode + #1 + + + + + TXB8 + no description available + 2 + 1 + read-write + + + 0 + 0 will be transmitted as the RS485 9th data bit + #0 + + + 1 + 1 will be transmitted as the RS485 9th data bit + #1 + + + + + SADEN + no description available + 3 + 1 + read-write + + + 0 + Disable RS-485 Slave Address Detected Interrupt + #0 + + + 1 + Enable RS-485 Slave Address Detected Interrupt + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SLADDR + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + UART2 + UARTv2 + UART + UART2_ + 0x21E8000 + + 0 + 0xBC + registers + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 2 + read-only + + + PRERR + no description available + 10 + 1 + read-only + + + 0 + = No parity error was detected for data in the RX_DATA field + #0 + + + 1 + = A parity error was detected for data in the RX_DATA field + #1 + + + + + BRK + no description available + 11 + 1 + read-only + + + 0 + The current character is not a BREAK character + #0 + + + 1 + The current character is a BREAK character + #1 + + + + + FRMERR + no description available + 12 + 1 + read-only + + + 0 + The current character has no framing error + #0 + + + 1 + The current character has a framing error + #1 + + + + + OVRRUN + no description available + 13 + 1 + read-only + + + 0 + No RxFIFO overrun was detected + #0 + + + 1 + A RxFIFO overrun was detected + #1 + + + + + ERR + no description available + 14 + 1 + read-only + + + 0 + No error status was detected + #0 + + + 1 + An error status was detected + #1 + + + + + CHARRDY + no description available + 15 + 1 + read-only + + + 0 + Character in RX_DATA field and associated flags are invalid. + #0 + + + 1 + Character in RX_DATA field and associated flags valid and ready for reading. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + no description available + 0 + 8 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + no description available + 0 + 1 + read-write + + + 0 + Disable the UART + #0 + + + 1 + Enable the UART + #1 + + + + + DOZE + no description available + 1 + 1 + read-write + + + 0 + The UART is enabled when in DOZE state + #0 + + + 1 + The UART is disabled when in DOZE state + #1 + + + + + ATDMAEN + no description available + 2 + 1 + read-write + + + 0 + Disable AGTIM DMA request + #0 + + + 1 + Enable AGTIM DMA request + #1 + + + + + TXDMAEN + no description available + 3 + 1 + read-write + + + 0 + Disable transmit DMA request + #0 + + + 1 + Enable transmit DMA request + #1 + + + + + SNDBRK + no description available + 4 + 1 + read-write + + + 0 + Do not send a BREAK character + #0 + + + 1 + Send a BREAK character (continuous 0s) + #1 + + + + + RTSDEN + no description available + 5 + 1 + read-write + + + 0 + Disable RTSD interrupt + #0 + + + 1 + Enable RTSD interrupt + #1 + + + + + TXMPTYEN + no description available + 6 + 1 + read-write + + + 0 + Disable the transmitter FIFO empty interrupt + #0 + + + 1 + Enable the transmitter FIFO empty interrupt + #1 + + + + + IREN + no description available + 7 + 1 + read-write + + + 0 + Disable the IR interface + #0 + + + 1 + Enable the IR interface + #1 + + + + + RXDMAEN + no description available + 8 + 1 + read-write + + + 0 + Disable DMA request + #0 + + + 1 + Enable DMA request + #1 + + + + + RRDYEN + no description available + 9 + 1 + read-write + + + 0 + Disables the RRDY interrupt + #0 + + + 1 + Enables the RRDY interrupt + #1 + + + + + ICD + no description available + 10 + 2 + read-write + + + 00 + Idle for more than 4 frames + #00 + + + 01 + Idle for more than 8 frames + #01 + + + 10 + Idle for more than 16 frames + #10 + + + 11 + Idle for more than 32 frames + #11 + + + + + IDEN + no description available + 12 + 1 + read-write + + + 0 + Disable the IDLE interrupt + #0 + + + 1 + Enable the IDLE interrupt + #1 + + + + + TRDYEN + no description available + 13 + 1 + read-write + + + 0 + Disable the transmitter ready interrupt + #0 + + + 1 + Enable the transmitter ready interrupt + #1 + + + + + ADBR + no description available + 14 + 1 + read-write + + + 0 + Disable automatic detection of baud rate + #0 + + + 1 + Enable automatic detection of baud rate + #1 + + + + + ADEN + no description available + 15 + 1 + read-write + + + 0 + Disable the automatic baud rate detection interrupt + #0 + + + 1 + Enable the automatic baud rate detection interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + no description available + 0 + 1 + read-write + + + 0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + #0 + + + 1 + No reset + #1 + + + + + RXEN + no description available + 1 + 1 + read-write + + + 0 + Disable the receiver + #0 + + + 1 + Enable the receiver + #1 + + + + + TXEN + no description available + 2 + 1 + read-write + + + 0 + Disable the transmitter + #0 + + + 1 + Enable the transmitter + #1 + + + + + ATEN + no description available + 3 + 1 + read-write + + + 0 + AGTIM interrupt disabled + #0 + + + 1 + AGTIM interrupt enabled + #1 + + + + + RTSEN + no description available + 4 + 1 + read-write + + + 0 + Disable request to send interrupt + #0 + + + 1 + Enable request to send interrupt + #1 + + + + + WS + no description available + 5 + 1 + read-write + + + 0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + #0 + + + 1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + #1 + + + + + STPB + no description available + 6 + 1 + read-write + + + 0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + #0 + + + 1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + #1 + + + + + PROE + no description available + 7 + 1 + read-write + + + 0 + Even parity + #0 + + + 1 + Odd parity + #1 + + + + + PREN + no description available + 8 + 1 + read-write + + + 0 + Disable parity generator and checker + #0 + + + 1 + Enable parity generator and checker + #1 + + + + + RTEC + no description available + 9 + 2 + read-write + + + 00 + Trigger interrupt on a rising edge + #00 + + + 01 + Trigger interrupt on a falling edge + #01 + + + + + ESCEN + no description available + 11 + 1 + read-write + + + 0 + Disable escape sequence detection + #0 + + + 1 + Enable escape sequence detection + #1 + + + + + CTS + no description available + 12 + 1 + read-write + + + 0 + The CTS_B pin is high (inactive) + #0 + + + 1 + The CTS_B pin is low (active) + #1 + + + + + CTSC + no description available + 13 + 1 + read-write + + + 0 + The CTS_B pin is controlled by the CTS bit + #0 + + + 1 + The CTS_B pin is controlled by the receiver + #1 + + + + + IRTS + no description available + 14 + 1 + read-write + + + 0 + Transmit only when the RTS pin is asserted + #0 + + + 1 + Ignore the RTS pin + #1 + + + + + ESCI + no description available + 15 + 1 + read-write + + + 0 + Disable the escape sequence interrupt + #0 + + + 1 + Enable the escape sequence interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + no description available + 0 + 1 + read-write + + + 0 + ACST interrupt disabled + #0 + + + 1 + ACST interrupt enabled + #1 + + + + + INVT + no description available + 1 + 1 + read-write + + + 0 + TXD is not inverted + #0 + + + 1 + TXD is inverted + #1 + + + 0 + TXD Active low transmission + #0 + + + 1 + TXD Active high transmission + #1 + + + + + RXDMUXSEL + no description available + 2 + 1 + read-write + + + DTRDEN + no description available + 3 + 1 + read-write + + + 0 + Disable DTRD interrupt + #0 + + + 1 + Enable DTRD interrupt + #1 + + + + + AWAKEN + no description available + 4 + 1 + read-write + + + 0 + Disable the AWAKE interrupt + #0 + + + 1 + Enable the AWAKE interrupt + #1 + + + + + AIRINTEN + no description available + 5 + 1 + read-write + + + 0 + Disable the AIRINT interrupt + #0 + + + 1 + Enable the AIRINT interrupt + #1 + + + + + RXDSEN + no description available + 6 + 1 + read-write + + + 0 + Disable the RXDS interrupt + #0 + + + 1 + Enable the RXDS interrupt + #1 + + + + + ADNIMP + no description available + 7 + 1 + read-write + + + 0 + Autobaud detection new features selected + #0 + + + 1 + Keep old autobaud detection mechanism + #1 + + + + + RI + no description available + 8 + 1 + read-write + + + 0 + RI_B pin is logic zero (DCE mode) + #0 + + + 1 + RI_B pin is logic one (DCE mode) + #1 + + + 0 + RIDELT interrupt disabled (DTE mode) + #0 + + + 1 + RIDELT interrupt enabled (DTE mode) + #1 + + + + + DCD + no description available + 9 + 1 + read-write + + + 0 + DCD_B pin is logic zero (DCE mode) + #0 + + + 1 + DCD_B pin is logic one (DCE mode) + #1 + + + 0 + DCDDELT interrupt disabled (DTE mode) + #0 + + + 1 + DCDDELT interrupt enabled (DTE mode) + #1 + + + + + DSR + no description available + 10 + 1 + read-write + + + 0 + DSR/ DTR pin is logic zero + #0 + + + 1 + DSR/ DTR pin is logic one + #1 + + + + + FRAERREN + no description available + 11 + 1 + read-write + + + 0 + Disable the frame error interrupt + #0 + + + 1 + Enable the frame error interrupt + #1 + + + + + PARERREN + no description available + 12 + 1 + read-write + + + 0 + Disable the parity error interrupt + #0 + + + 1 + Enable the parity error interrupt + #1 + + + + + DTREN + no description available + 13 + 1 + read-write + + + 0 + Data Terminal Ready Interrupt Disabled + #0 + + + 1 + Data Terminal Ready Interrupt Enabled + #1 + + + + + DPEC + no description available + 14 + 2 + read-write + + + 00 + interrupt generated on rising edge + #00 + + + 01 + interrupt generated on falling edge + #01 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + no description available + 0 + 1 + read-write + + + 0 + Disable RDR interrupt + #0 + + + 1 + Enable RDR interrupt + #1 + + + + + OREN + no description available + 1 + 1 + read-write + + + 0 + Disable ORE interrupt + #0 + + + 1 + Enable ORE interrupt + #1 + + + + + BKEN + no description available + 2 + 1 + read-write + + + 0 + Disable the BRCD interrupt + #0 + + + 1 + Enable the BRCD interrupt + #1 + + + + + TCEN + no description available + 3 + 1 + read-write + + + 0 + Disable TXDC interrupt + #0 + + + 1 + Enable TXDC interrupt + #1 + + + + + LPBYP + no description available + 4 + 1 + read-write + + + 0 + Low power features enabled + #0 + + + 1 + Low power features disabled + #1 + + + + + IRSC + no description available + 5 + 1 + read-write + + + 0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + #0 + + + 1 + The vote logic uses the UART reference clock + #1 + + + + + IDDMAEN + no description available + 6 + 1 + read-write + + + 0 + DMA IDLE interrupt disabled + #0 + + + 1 + DMA IDLE interrupt enabled + #1 + + + + + WKEN + no description available + 7 + 1 + read-write + + + 0 + Disable the WAKE interrupt + #0 + + + 1 + Enable the WAKE interrupt + #1 + + + + + ENIRI + no description available + 8 + 1 + read-write + + + 0 + Serial infrared Interrupt disabled + #0 + + + 1 + Serial infrared Interrupt enabled + #1 + + + + + INVR + no description available + 9 + 1 + read-write + + + 0 + RXD input is not inverted + #0 + + + 1 + RXD input is inverted + #1 + + + 0 + RXD active low detection + #0 + + + 1 + RXD active high detection + #1 + + + + + CTSTL + no description available + 10 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + 1 characters in the RxFIFO + #000001 + + + 100000 + 32 characters in the RxFIFO (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + no description available + 0 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + RxFIFO has 1 character + #000001 + + + 011111 + RxFIFO has 31 characters + #011111 + + + 100000 + RxFIFO has 32 characters (maximum) + #100000 + + + + + DCEDTE + no description available + 6 + 1 + read-write + + + 0 + DCE mode selected + #0 + + + 1 + DTE mode selected + #1 + + + + + RFDIV + no description available + 7 + 3 + read-write + + + 000 + Divide input clock by 6 + #000 + + + 001 + Divide input clock by 5 + #001 + + + 010 + Divide input clock by 4 + #010 + + + 011 + Divide input clock by 3 + #011 + + + 100 + Divide input clock by 2 + #100 + + + 101 + Divide input clock by 1 + #101 + + + 110 + Divide input clock by 7 + #110 + + + 111 + Reserved + #111 + + + + + TXTL + no description available + 10 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + Reserved + #000001 + + + 000010 + TxFIFO has 2 or fewer characters + #000010 + + + 011111 + TxFIFO has 31 or fewer characters + #011111 + + + 100000 + TxFIFO has 32 characters (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + SAD + no description available + 3 + 1 + read-write + + + 0 + No slave address detected + #0 + + + 1 + Slave address detected + #1 + + + + + AWAKE + no description available + 4 + 1 + read-write + + + 0 + No falling edge was detected on the RXD Serial pin + #0 + + + 1 + A falling edge was detected on the RXD Serial pin + #1 + + + + + AIRINT + no description available + 5 + 1 + read-write + + + 0 + No pulse was detected on the RXD IrDA pin + #0 + + + 1 + A pulse was detected on the RXD IrDA pin + #1 + + + + + RXDS + no description available + 6 + 1 + read-only + + + 0 + Receive in progress + #0 + + + 1 + Receiver is IDLE + #1 + + + + + DTRD + no description available + 7 + 1 + read-write + + + 0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + #0 + + + 1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + #1 + + + + + AGTIM + no description available + 8 + 1 + read-write + + + 0 + AGTIM is not active + #0 + + + 1 + AGTIM is active (write 1 to clear) + #1 + + + + + RRDY + no description available + 9 + 1 + read-only + + + 0 + No character ready + #0 + + + 1 + Character(s) ready (interrupt posted) + #1 + + + + + FRAMERR + no description available + 10 + 1 + read-write + + + 0 + No frame error detected + #0 + + + 1 + Frame error detected (write 1 to clear) + #1 + + + + + ESCF + no description available + 11 + 1 + read-write + + + 0 + No escape sequence detected + #0 + + + 1 + Escape sequence detected (write 1 to clear). + #1 + + + + + RTSD + no description available + 12 + 1 + read-write + + + 0 + RTS_B pin did not change state since last cleared + #0 + + + 1 + RTS_B pin changed state (write 1 to clear) + #1 + + + + + TRDY + no description available + 13 + 1 + read-only + + + 0 + The transmitter does not require data + #0 + + + 1 + The transmitter requires data (interrupt posted) + #1 + + + + + RTSS + no description available + 14 + 1 + read-only + + + 0 + The RTS_B pin is high (inactive) + #0 + + + 1 + The RTS_B pin is low (active) + #1 + + + + + PARITYERR + no description available + 15 + 1 + read-write + + + 0 + No parity error detected + #0 + + + 1 + Parity error detected (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + no description available + 0 + 1 + read-only + + + 0 + No receive data ready + #0 + + + 1 + Receive data ready + #1 + + + + + ORE + no description available + 1 + 1 + read-write + + + 0 + No overrun error + #0 + + + 1 + Overrun error (write 1 to clear) + #1 + + + + + BRCD + no description available + 2 + 1 + read-write + + + 0 + No BREAK condition was detected + #0 + + + 1 + A BREAK condition was detected (write 1 to clear) + #1 + + + + + TXDC + no description available + 3 + 1 + read-only + + + 0 + Transmit is incomplete + #0 + + + 1 + Transmit is complete + #1 + + + + + RTSF + no description available + 4 + 1 + read-write + + + 0 + Programmed edge not detected on RTS_B + #0 + + + 1 + Programmed edge detected on RTS_B (write 1 to clear) + #1 + + + + + DCDIN + no description available + 5 + 1 + read-only + + + 0 + Carrier signal Detected + #0 + + + 1 + No Carrier signal Detected + #1 + + + + + DCDDELT + no description available + 6 + 1 + read-write + + + 0 + Data Carrier Detect input has not changed state + #0 + + + 1 + Data Carrier Detect input has changed state (write 1 to clear) + #1 + + + + + WAKE + no description available + 7 + 1 + read-write + + + 0 + start bit not detected + #0 + + + 1 + start bit detected (write 1 to clear) + #1 + + + + + IRINT + no description available + 8 + 1 + read-write + + + 0 + no edge detected + #0 + + + 1 + valid edge detected (write 1 to clear) + #1 + + + + + RIIN + no description available + 9 + 1 + read-only + + + 0 + Ring Detected + #0 + + + 1 + No Ring Detected + #1 + + + + + RIDELT + no description available + 10 + 1 + read-write + + + 0 + Ring Indicator input has not changed state + #0 + + + 1 + Ring Indicator input has changed state (write 1 to clear) + #1 + + + + + ACST + no description available + 11 + 1 + read-write + + + 0 + Measurement of bit length not finished (in autobaud) + #0 + + + 1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + #1 + + + + + IDLE + no description available + 12 + 1 + read-write + + + 0 + No idle condition detected + #0 + + + 1 + Idle condition detected (write 1 to clear) + #1 + + + + + DTRF + no description available + 13 + 1 + read-write + + + 0 + Programmed edge not detected on DTR/DSR + #0 + + + 1 + Programmed edge detected on DTR/DSR (write 1 to clear) + #1 + + + + + TXFE + no description available + 14 + 1 + read-only + + + 0 + The transmit buffer (TxFIFO) is not empty + #0 + + + 1 + The transmit buffer (TxFIFO) is empty + #1 + + + + + ADET + no description available + 15 + 1 + read-write + + + 0 + ASCII "A" or "a" was not received + #0 + + + 1 + ASCII "A" or "a" was received (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + no description available + 0 + 1 + read-write + + + 0 + Software reset inactive + #0 + + + 1 + Software reset active + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + RXFULL + no description available + 3 + 1 + read-write + + + 0 + The RxFIFO is not full + #0 + + + 1 + The RxFIFO is full + #1 + + + + + TXFULL + no description available + 4 + 1 + read-write + + + 0 + The TxFIFO is not full + #0 + + + 1 + The TxFIFO is full + #1 + + + + + RXEMPTY + no description available + 5 + 1 + read-write + + + 0 + The RxFIFO is not empty + #0 + + + 1 + The RxFIFO is empty + #1 + + + + + TXEMPTY + no description available + 6 + 1 + read-write + + + 0 + The TxFIFO is not empty + #0 + + + 1 + The TxFIFO is empty + #1 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + RXDBG + no description available + 9 + 1 + read-write + + + 0 + rx fifo read pointer does not increment + #0 + + + 1 + rx_fifo read pointer increments as normal + #1 + + + + + LOOPIR + no description available + 10 + 1 + read-write + + + 0 + No IR loop + #0 + + + 1 + Connect IR transmitter to IR receiver + #1 + + + + + DBGEN + no description available + 11 + 1 + read-write + + + 0 + UART will go into debug mode when debug_req is HIGH + #0 + + + 1 + UART will not go into debug mode even if debug_req is HIGH + #1 + + + + + LOOP + no description available + 12 + 1 + read-write + + + 0 + Normal receiver operation + #0 + + + 1 + Internally connect the transmitter output to the receiver input + #1 + + + + + FRCPERR + no description available + 13 + 1 + read-write + + + 0 + Generate normal parity + #0 + + + 1 + Generate inverted parity (error) + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + no description available + 0 + 1 + read-write + + + 0 + Normal RS-232 or IrDA mode, see for detail. + #0 + + + 1 + Enable RS-485 mode, see for detail + #1 + + + + + SLAM + no description available + 1 + 1 + read-write + + + 0 + Select Normal Address Detect mode + #0 + + + 1 + Select Automatic Address Detect mode + #1 + + + + + TXB8 + no description available + 2 + 1 + read-write + + + 0 + 0 will be transmitted as the RS485 9th data bit + #0 + + + 1 + 1 will be transmitted as the RS485 9th data bit + #1 + + + + + SADEN + no description available + 3 + 1 + read-write + + + 0 + Disable RS-485 Slave Address Detected Interrupt + #0 + + + 1 + Enable RS-485 Slave Address Detected Interrupt + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SLADDR + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + UART3 + UARTv2 + UART + UART3_ + 0x21EC000 + + 0 + 0xBC + registers + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 2 + read-only + + + PRERR + no description available + 10 + 1 + read-only + + + 0 + = No parity error was detected for data in the RX_DATA field + #0 + + + 1 + = A parity error was detected for data in the RX_DATA field + #1 + + + + + BRK + no description available + 11 + 1 + read-only + + + 0 + The current character is not a BREAK character + #0 + + + 1 + The current character is a BREAK character + #1 + + + + + FRMERR + no description available + 12 + 1 + read-only + + + 0 + The current character has no framing error + #0 + + + 1 + The current character has a framing error + #1 + + + + + OVRRUN + no description available + 13 + 1 + read-only + + + 0 + No RxFIFO overrun was detected + #0 + + + 1 + A RxFIFO overrun was detected + #1 + + + + + ERR + no description available + 14 + 1 + read-only + + + 0 + No error status was detected + #0 + + + 1 + An error status was detected + #1 + + + + + CHARRDY + no description available + 15 + 1 + read-only + + + 0 + Character in RX_DATA field and associated flags are invalid. + #0 + + + 1 + Character in RX_DATA field and associated flags valid and ready for reading. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + no description available + 0 + 8 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + no description available + 0 + 1 + read-write + + + 0 + Disable the UART + #0 + + + 1 + Enable the UART + #1 + + + + + DOZE + no description available + 1 + 1 + read-write + + + 0 + The UART is enabled when in DOZE state + #0 + + + 1 + The UART is disabled when in DOZE state + #1 + + + + + ATDMAEN + no description available + 2 + 1 + read-write + + + 0 + Disable AGTIM DMA request + #0 + + + 1 + Enable AGTIM DMA request + #1 + + + + + TXDMAEN + no description available + 3 + 1 + read-write + + + 0 + Disable transmit DMA request + #0 + + + 1 + Enable transmit DMA request + #1 + + + + + SNDBRK + no description available + 4 + 1 + read-write + + + 0 + Do not send a BREAK character + #0 + + + 1 + Send a BREAK character (continuous 0s) + #1 + + + + + RTSDEN + no description available + 5 + 1 + read-write + + + 0 + Disable RTSD interrupt + #0 + + + 1 + Enable RTSD interrupt + #1 + + + + + TXMPTYEN + no description available + 6 + 1 + read-write + + + 0 + Disable the transmitter FIFO empty interrupt + #0 + + + 1 + Enable the transmitter FIFO empty interrupt + #1 + + + + + IREN + no description available + 7 + 1 + read-write + + + 0 + Disable the IR interface + #0 + + + 1 + Enable the IR interface + #1 + + + + + RXDMAEN + no description available + 8 + 1 + read-write + + + 0 + Disable DMA request + #0 + + + 1 + Enable DMA request + #1 + + + + + RRDYEN + no description available + 9 + 1 + read-write + + + 0 + Disables the RRDY interrupt + #0 + + + 1 + Enables the RRDY interrupt + #1 + + + + + ICD + no description available + 10 + 2 + read-write + + + 00 + Idle for more than 4 frames + #00 + + + 01 + Idle for more than 8 frames + #01 + + + 10 + Idle for more than 16 frames + #10 + + + 11 + Idle for more than 32 frames + #11 + + + + + IDEN + no description available + 12 + 1 + read-write + + + 0 + Disable the IDLE interrupt + #0 + + + 1 + Enable the IDLE interrupt + #1 + + + + + TRDYEN + no description available + 13 + 1 + read-write + + + 0 + Disable the transmitter ready interrupt + #0 + + + 1 + Enable the transmitter ready interrupt + #1 + + + + + ADBR + no description available + 14 + 1 + read-write + + + 0 + Disable automatic detection of baud rate + #0 + + + 1 + Enable automatic detection of baud rate + #1 + + + + + ADEN + no description available + 15 + 1 + read-write + + + 0 + Disable the automatic baud rate detection interrupt + #0 + + + 1 + Enable the automatic baud rate detection interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + no description available + 0 + 1 + read-write + + + 0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + #0 + + + 1 + No reset + #1 + + + + + RXEN + no description available + 1 + 1 + read-write + + + 0 + Disable the receiver + #0 + + + 1 + Enable the receiver + #1 + + + + + TXEN + no description available + 2 + 1 + read-write + + + 0 + Disable the transmitter + #0 + + + 1 + Enable the transmitter + #1 + + + + + ATEN + no description available + 3 + 1 + read-write + + + 0 + AGTIM interrupt disabled + #0 + + + 1 + AGTIM interrupt enabled + #1 + + + + + RTSEN + no description available + 4 + 1 + read-write + + + 0 + Disable request to send interrupt + #0 + + + 1 + Enable request to send interrupt + #1 + + + + + WS + no description available + 5 + 1 + read-write + + + 0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + #0 + + + 1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + #1 + + + + + STPB + no description available + 6 + 1 + read-write + + + 0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + #0 + + + 1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + #1 + + + + + PROE + no description available + 7 + 1 + read-write + + + 0 + Even parity + #0 + + + 1 + Odd parity + #1 + + + + + PREN + no description available + 8 + 1 + read-write + + + 0 + Disable parity generator and checker + #0 + + + 1 + Enable parity generator and checker + #1 + + + + + RTEC + no description available + 9 + 2 + read-write + + + 00 + Trigger interrupt on a rising edge + #00 + + + 01 + Trigger interrupt on a falling edge + #01 + + + + + ESCEN + no description available + 11 + 1 + read-write + + + 0 + Disable escape sequence detection + #0 + + + 1 + Enable escape sequence detection + #1 + + + + + CTS + no description available + 12 + 1 + read-write + + + 0 + The CTS_B pin is high (inactive) + #0 + + + 1 + The CTS_B pin is low (active) + #1 + + + + + CTSC + no description available + 13 + 1 + read-write + + + 0 + The CTS_B pin is controlled by the CTS bit + #0 + + + 1 + The CTS_B pin is controlled by the receiver + #1 + + + + + IRTS + no description available + 14 + 1 + read-write + + + 0 + Transmit only when the RTS pin is asserted + #0 + + + 1 + Ignore the RTS pin + #1 + + + + + ESCI + no description available + 15 + 1 + read-write + + + 0 + Disable the escape sequence interrupt + #0 + + + 1 + Enable the escape sequence interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + no description available + 0 + 1 + read-write + + + 0 + ACST interrupt disabled + #0 + + + 1 + ACST interrupt enabled + #1 + + + + + INVT + no description available + 1 + 1 + read-write + + + 0 + TXD is not inverted + #0 + + + 1 + TXD is inverted + #1 + + + 0 + TXD Active low transmission + #0 + + + 1 + TXD Active high transmission + #1 + + + + + RXDMUXSEL + no description available + 2 + 1 + read-write + + + DTRDEN + no description available + 3 + 1 + read-write + + + 0 + Disable DTRD interrupt + #0 + + + 1 + Enable DTRD interrupt + #1 + + + + + AWAKEN + no description available + 4 + 1 + read-write + + + 0 + Disable the AWAKE interrupt + #0 + + + 1 + Enable the AWAKE interrupt + #1 + + + + + AIRINTEN + no description available + 5 + 1 + read-write + + + 0 + Disable the AIRINT interrupt + #0 + + + 1 + Enable the AIRINT interrupt + #1 + + + + + RXDSEN + no description available + 6 + 1 + read-write + + + 0 + Disable the RXDS interrupt + #0 + + + 1 + Enable the RXDS interrupt + #1 + + + + + ADNIMP + no description available + 7 + 1 + read-write + + + 0 + Autobaud detection new features selected + #0 + + + 1 + Keep old autobaud detection mechanism + #1 + + + + + RI + no description available + 8 + 1 + read-write + + + 0 + RI_B pin is logic zero (DCE mode) + #0 + + + 1 + RI_B pin is logic one (DCE mode) + #1 + + + 0 + RIDELT interrupt disabled (DTE mode) + #0 + + + 1 + RIDELT interrupt enabled (DTE mode) + #1 + + + + + DCD + no description available + 9 + 1 + read-write + + + 0 + DCD_B pin is logic zero (DCE mode) + #0 + + + 1 + DCD_B pin is logic one (DCE mode) + #1 + + + 0 + DCDDELT interrupt disabled (DTE mode) + #0 + + + 1 + DCDDELT interrupt enabled (DTE mode) + #1 + + + + + DSR + no description available + 10 + 1 + read-write + + + 0 + DSR/ DTR pin is logic zero + #0 + + + 1 + DSR/ DTR pin is logic one + #1 + + + + + FRAERREN + no description available + 11 + 1 + read-write + + + 0 + Disable the frame error interrupt + #0 + + + 1 + Enable the frame error interrupt + #1 + + + + + PARERREN + no description available + 12 + 1 + read-write + + + 0 + Disable the parity error interrupt + #0 + + + 1 + Enable the parity error interrupt + #1 + + + + + DTREN + no description available + 13 + 1 + read-write + + + 0 + Data Terminal Ready Interrupt Disabled + #0 + + + 1 + Data Terminal Ready Interrupt Enabled + #1 + + + + + DPEC + no description available + 14 + 2 + read-write + + + 00 + interrupt generated on rising edge + #00 + + + 01 + interrupt generated on falling edge + #01 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + no description available + 0 + 1 + read-write + + + 0 + Disable RDR interrupt + #0 + + + 1 + Enable RDR interrupt + #1 + + + + + OREN + no description available + 1 + 1 + read-write + + + 0 + Disable ORE interrupt + #0 + + + 1 + Enable ORE interrupt + #1 + + + + + BKEN + no description available + 2 + 1 + read-write + + + 0 + Disable the BRCD interrupt + #0 + + + 1 + Enable the BRCD interrupt + #1 + + + + + TCEN + no description available + 3 + 1 + read-write + + + 0 + Disable TXDC interrupt + #0 + + + 1 + Enable TXDC interrupt + #1 + + + + + LPBYP + no description available + 4 + 1 + read-write + + + 0 + Low power features enabled + #0 + + + 1 + Low power features disabled + #1 + + + + + IRSC + no description available + 5 + 1 + read-write + + + 0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + #0 + + + 1 + The vote logic uses the UART reference clock + #1 + + + + + IDDMAEN + no description available + 6 + 1 + read-write + + + 0 + DMA IDLE interrupt disabled + #0 + + + 1 + DMA IDLE interrupt enabled + #1 + + + + + WKEN + no description available + 7 + 1 + read-write + + + 0 + Disable the WAKE interrupt + #0 + + + 1 + Enable the WAKE interrupt + #1 + + + + + ENIRI + no description available + 8 + 1 + read-write + + + 0 + Serial infrared Interrupt disabled + #0 + + + 1 + Serial infrared Interrupt enabled + #1 + + + + + INVR + no description available + 9 + 1 + read-write + + + 0 + RXD input is not inverted + #0 + + + 1 + RXD input is inverted + #1 + + + 0 + RXD active low detection + #0 + + + 1 + RXD active high detection + #1 + + + + + CTSTL + no description available + 10 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + 1 characters in the RxFIFO + #000001 + + + 100000 + 32 characters in the RxFIFO (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + no description available + 0 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + RxFIFO has 1 character + #000001 + + + 011111 + RxFIFO has 31 characters + #011111 + + + 100000 + RxFIFO has 32 characters (maximum) + #100000 + + + + + DCEDTE + no description available + 6 + 1 + read-write + + + 0 + DCE mode selected + #0 + + + 1 + DTE mode selected + #1 + + + + + RFDIV + no description available + 7 + 3 + read-write + + + 000 + Divide input clock by 6 + #000 + + + 001 + Divide input clock by 5 + #001 + + + 010 + Divide input clock by 4 + #010 + + + 011 + Divide input clock by 3 + #011 + + + 100 + Divide input clock by 2 + #100 + + + 101 + Divide input clock by 1 + #101 + + + 110 + Divide input clock by 7 + #110 + + + 111 + Reserved + #111 + + + + + TXTL + no description available + 10 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + Reserved + #000001 + + + 000010 + TxFIFO has 2 or fewer characters + #000010 + + + 011111 + TxFIFO has 31 or fewer characters + #011111 + + + 100000 + TxFIFO has 32 characters (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + SAD + no description available + 3 + 1 + read-write + + + 0 + No slave address detected + #0 + + + 1 + Slave address detected + #1 + + + + + AWAKE + no description available + 4 + 1 + read-write + + + 0 + No falling edge was detected on the RXD Serial pin + #0 + + + 1 + A falling edge was detected on the RXD Serial pin + #1 + + + + + AIRINT + no description available + 5 + 1 + read-write + + + 0 + No pulse was detected on the RXD IrDA pin + #0 + + + 1 + A pulse was detected on the RXD IrDA pin + #1 + + + + + RXDS + no description available + 6 + 1 + read-only + + + 0 + Receive in progress + #0 + + + 1 + Receiver is IDLE + #1 + + + + + DTRD + no description available + 7 + 1 + read-write + + + 0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + #0 + + + 1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + #1 + + + + + AGTIM + no description available + 8 + 1 + read-write + + + 0 + AGTIM is not active + #0 + + + 1 + AGTIM is active (write 1 to clear) + #1 + + + + + RRDY + no description available + 9 + 1 + read-only + + + 0 + No character ready + #0 + + + 1 + Character(s) ready (interrupt posted) + #1 + + + + + FRAMERR + no description available + 10 + 1 + read-write + + + 0 + No frame error detected + #0 + + + 1 + Frame error detected (write 1 to clear) + #1 + + + + + ESCF + no description available + 11 + 1 + read-write + + + 0 + No escape sequence detected + #0 + + + 1 + Escape sequence detected (write 1 to clear). + #1 + + + + + RTSD + no description available + 12 + 1 + read-write + + + 0 + RTS_B pin did not change state since last cleared + #0 + + + 1 + RTS_B pin changed state (write 1 to clear) + #1 + + + + + TRDY + no description available + 13 + 1 + read-only + + + 0 + The transmitter does not require data + #0 + + + 1 + The transmitter requires data (interrupt posted) + #1 + + + + + RTSS + no description available + 14 + 1 + read-only + + + 0 + The RTS_B pin is high (inactive) + #0 + + + 1 + The RTS_B pin is low (active) + #1 + + + + + PARITYERR + no description available + 15 + 1 + read-write + + + 0 + No parity error detected + #0 + + + 1 + Parity error detected (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + no description available + 0 + 1 + read-only + + + 0 + No receive data ready + #0 + + + 1 + Receive data ready + #1 + + + + + ORE + no description available + 1 + 1 + read-write + + + 0 + No overrun error + #0 + + + 1 + Overrun error (write 1 to clear) + #1 + + + + + BRCD + no description available + 2 + 1 + read-write + + + 0 + No BREAK condition was detected + #0 + + + 1 + A BREAK condition was detected (write 1 to clear) + #1 + + + + + TXDC + no description available + 3 + 1 + read-only + + + 0 + Transmit is incomplete + #0 + + + 1 + Transmit is complete + #1 + + + + + RTSF + no description available + 4 + 1 + read-write + + + 0 + Programmed edge not detected on RTS_B + #0 + + + 1 + Programmed edge detected on RTS_B (write 1 to clear) + #1 + + + + + DCDIN + no description available + 5 + 1 + read-only + + + 0 + Carrier signal Detected + #0 + + + 1 + No Carrier signal Detected + #1 + + + + + DCDDELT + no description available + 6 + 1 + read-write + + + 0 + Data Carrier Detect input has not changed state + #0 + + + 1 + Data Carrier Detect input has changed state (write 1 to clear) + #1 + + + + + WAKE + no description available + 7 + 1 + read-write + + + 0 + start bit not detected + #0 + + + 1 + start bit detected (write 1 to clear) + #1 + + + + + IRINT + no description available + 8 + 1 + read-write + + + 0 + no edge detected + #0 + + + 1 + valid edge detected (write 1 to clear) + #1 + + + + + RIIN + no description available + 9 + 1 + read-only + + + 0 + Ring Detected + #0 + + + 1 + No Ring Detected + #1 + + + + + RIDELT + no description available + 10 + 1 + read-write + + + 0 + Ring Indicator input has not changed state + #0 + + + 1 + Ring Indicator input has changed state (write 1 to clear) + #1 + + + + + ACST + no description available + 11 + 1 + read-write + + + 0 + Measurement of bit length not finished (in autobaud) + #0 + + + 1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + #1 + + + + + IDLE + no description available + 12 + 1 + read-write + + + 0 + No idle condition detected + #0 + + + 1 + Idle condition detected (write 1 to clear) + #1 + + + + + DTRF + no description available + 13 + 1 + read-write + + + 0 + Programmed edge not detected on DTR/DSR + #0 + + + 1 + Programmed edge detected on DTR/DSR (write 1 to clear) + #1 + + + + + TXFE + no description available + 14 + 1 + read-only + + + 0 + The transmit buffer (TxFIFO) is not empty + #0 + + + 1 + The transmit buffer (TxFIFO) is empty + #1 + + + + + ADET + no description available + 15 + 1 + read-write + + + 0 + ASCII "A" or "a" was not received + #0 + + + 1 + ASCII "A" or "a" was received (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + no description available + 0 + 1 + read-write + + + 0 + Software reset inactive + #0 + + + 1 + Software reset active + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + RXFULL + no description available + 3 + 1 + read-write + + + 0 + The RxFIFO is not full + #0 + + + 1 + The RxFIFO is full + #1 + + + + + TXFULL + no description available + 4 + 1 + read-write + + + 0 + The TxFIFO is not full + #0 + + + 1 + The TxFIFO is full + #1 + + + + + RXEMPTY + no description available + 5 + 1 + read-write + + + 0 + The RxFIFO is not empty + #0 + + + 1 + The RxFIFO is empty + #1 + + + + + TXEMPTY + no description available + 6 + 1 + read-write + + + 0 + The TxFIFO is not empty + #0 + + + 1 + The TxFIFO is empty + #1 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + RXDBG + no description available + 9 + 1 + read-write + + + 0 + rx fifo read pointer does not increment + #0 + + + 1 + rx_fifo read pointer increments as normal + #1 + + + + + LOOPIR + no description available + 10 + 1 + read-write + + + 0 + No IR loop + #0 + + + 1 + Connect IR transmitter to IR receiver + #1 + + + + + DBGEN + no description available + 11 + 1 + read-write + + + 0 + UART will go into debug mode when debug_req is HIGH + #0 + + + 1 + UART will not go into debug mode even if debug_req is HIGH + #1 + + + + + LOOP + no description available + 12 + 1 + read-write + + + 0 + Normal receiver operation + #0 + + + 1 + Internally connect the transmitter output to the receiver input + #1 + + + + + FRCPERR + no description available + 13 + 1 + read-write + + + 0 + Generate normal parity + #0 + + + 1 + Generate inverted parity (error) + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + no description available + 0 + 1 + read-write + + + 0 + Normal RS-232 or IrDA mode, see for detail. + #0 + + + 1 + Enable RS-485 mode, see for detail + #1 + + + + + SLAM + no description available + 1 + 1 + read-write + + + 0 + Select Normal Address Detect mode + #0 + + + 1 + Select Automatic Address Detect mode + #1 + + + + + TXB8 + no description available + 2 + 1 + read-write + + + 0 + 0 will be transmitted as the RS485 9th data bit + #0 + + + 1 + 1 will be transmitted as the RS485 9th data bit + #1 + + + + + SADEN + no description available + 3 + 1 + read-write + + + 0 + Disable RS-485 Slave Address Detected Interrupt + #0 + + + 1 + Enable RS-485 Slave Address Detected Interrupt + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SLADDR + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + UART4 + UARTv2 + UART + UART4_ + 0x21F0000 + + 0 + 0xBC + registers + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 2 + read-only + + + PRERR + no description available + 10 + 1 + read-only + + + 0 + = No parity error was detected for data in the RX_DATA field + #0 + + + 1 + = A parity error was detected for data in the RX_DATA field + #1 + + + + + BRK + no description available + 11 + 1 + read-only + + + 0 + The current character is not a BREAK character + #0 + + + 1 + The current character is a BREAK character + #1 + + + + + FRMERR + no description available + 12 + 1 + read-only + + + 0 + The current character has no framing error + #0 + + + 1 + The current character has a framing error + #1 + + + + + OVRRUN + no description available + 13 + 1 + read-only + + + 0 + No RxFIFO overrun was detected + #0 + + + 1 + A RxFIFO overrun was detected + #1 + + + + + ERR + no description available + 14 + 1 + read-only + + + 0 + No error status was detected + #0 + + + 1 + An error status was detected + #1 + + + + + CHARRDY + no description available + 15 + 1 + read-only + + + 0 + Character in RX_DATA field and associated flags are invalid. + #0 + + + 1 + Character in RX_DATA field and associated flags valid and ready for reading. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + no description available + 0 + 8 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + no description available + 0 + 1 + read-write + + + 0 + Disable the UART + #0 + + + 1 + Enable the UART + #1 + + + + + DOZE + no description available + 1 + 1 + read-write + + + 0 + The UART is enabled when in DOZE state + #0 + + + 1 + The UART is disabled when in DOZE state + #1 + + + + + ATDMAEN + no description available + 2 + 1 + read-write + + + 0 + Disable AGTIM DMA request + #0 + + + 1 + Enable AGTIM DMA request + #1 + + + + + TXDMAEN + no description available + 3 + 1 + read-write + + + 0 + Disable transmit DMA request + #0 + + + 1 + Enable transmit DMA request + #1 + + + + + SNDBRK + no description available + 4 + 1 + read-write + + + 0 + Do not send a BREAK character + #0 + + + 1 + Send a BREAK character (continuous 0s) + #1 + + + + + RTSDEN + no description available + 5 + 1 + read-write + + + 0 + Disable RTSD interrupt + #0 + + + 1 + Enable RTSD interrupt + #1 + + + + + TXMPTYEN + no description available + 6 + 1 + read-write + + + 0 + Disable the transmitter FIFO empty interrupt + #0 + + + 1 + Enable the transmitter FIFO empty interrupt + #1 + + + + + IREN + no description available + 7 + 1 + read-write + + + 0 + Disable the IR interface + #0 + + + 1 + Enable the IR interface + #1 + + + + + RXDMAEN + no description available + 8 + 1 + read-write + + + 0 + Disable DMA request + #0 + + + 1 + Enable DMA request + #1 + + + + + RRDYEN + no description available + 9 + 1 + read-write + + + 0 + Disables the RRDY interrupt + #0 + + + 1 + Enables the RRDY interrupt + #1 + + + + + ICD + no description available + 10 + 2 + read-write + + + 00 + Idle for more than 4 frames + #00 + + + 01 + Idle for more than 8 frames + #01 + + + 10 + Idle for more than 16 frames + #10 + + + 11 + Idle for more than 32 frames + #11 + + + + + IDEN + no description available + 12 + 1 + read-write + + + 0 + Disable the IDLE interrupt + #0 + + + 1 + Enable the IDLE interrupt + #1 + + + + + TRDYEN + no description available + 13 + 1 + read-write + + + 0 + Disable the transmitter ready interrupt + #0 + + + 1 + Enable the transmitter ready interrupt + #1 + + + + + ADBR + no description available + 14 + 1 + read-write + + + 0 + Disable automatic detection of baud rate + #0 + + + 1 + Enable automatic detection of baud rate + #1 + + + + + ADEN + no description available + 15 + 1 + read-write + + + 0 + Disable the automatic baud rate detection interrupt + #0 + + + 1 + Enable the automatic baud rate detection interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + no description available + 0 + 1 + read-write + + + 0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + #0 + + + 1 + No reset + #1 + + + + + RXEN + no description available + 1 + 1 + read-write + + + 0 + Disable the receiver + #0 + + + 1 + Enable the receiver + #1 + + + + + TXEN + no description available + 2 + 1 + read-write + + + 0 + Disable the transmitter + #0 + + + 1 + Enable the transmitter + #1 + + + + + ATEN + no description available + 3 + 1 + read-write + + + 0 + AGTIM interrupt disabled + #0 + + + 1 + AGTIM interrupt enabled + #1 + + + + + RTSEN + no description available + 4 + 1 + read-write + + + 0 + Disable request to send interrupt + #0 + + + 1 + Enable request to send interrupt + #1 + + + + + WS + no description available + 5 + 1 + read-write + + + 0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + #0 + + + 1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + #1 + + + + + STPB + no description available + 6 + 1 + read-write + + + 0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + #0 + + + 1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + #1 + + + + + PROE + no description available + 7 + 1 + read-write + + + 0 + Even parity + #0 + + + 1 + Odd parity + #1 + + + + + PREN + no description available + 8 + 1 + read-write + + + 0 + Disable parity generator and checker + #0 + + + 1 + Enable parity generator and checker + #1 + + + + + RTEC + no description available + 9 + 2 + read-write + + + 00 + Trigger interrupt on a rising edge + #00 + + + 01 + Trigger interrupt on a falling edge + #01 + + + + + ESCEN + no description available + 11 + 1 + read-write + + + 0 + Disable escape sequence detection + #0 + + + 1 + Enable escape sequence detection + #1 + + + + + CTS + no description available + 12 + 1 + read-write + + + 0 + The CTS_B pin is high (inactive) + #0 + + + 1 + The CTS_B pin is low (active) + #1 + + + + + CTSC + no description available + 13 + 1 + read-write + + + 0 + The CTS_B pin is controlled by the CTS bit + #0 + + + 1 + The CTS_B pin is controlled by the receiver + #1 + + + + + IRTS + no description available + 14 + 1 + read-write + + + 0 + Transmit only when the RTS pin is asserted + #0 + + + 1 + Ignore the RTS pin + #1 + + + + + ESCI + no description available + 15 + 1 + read-write + + + 0 + Disable the escape sequence interrupt + #0 + + + 1 + Enable the escape sequence interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + no description available + 0 + 1 + read-write + + + 0 + ACST interrupt disabled + #0 + + + 1 + ACST interrupt enabled + #1 + + + + + INVT + no description available + 1 + 1 + read-write + + + 0 + TXD is not inverted + #0 + + + 1 + TXD is inverted + #1 + + + 0 + TXD Active low transmission + #0 + + + 1 + TXD Active high transmission + #1 + + + + + RXDMUXSEL + no description available + 2 + 1 + read-write + + + DTRDEN + no description available + 3 + 1 + read-write + + + 0 + Disable DTRD interrupt + #0 + + + 1 + Enable DTRD interrupt + #1 + + + + + AWAKEN + no description available + 4 + 1 + read-write + + + 0 + Disable the AWAKE interrupt + #0 + + + 1 + Enable the AWAKE interrupt + #1 + + + + + AIRINTEN + no description available + 5 + 1 + read-write + + + 0 + Disable the AIRINT interrupt + #0 + + + 1 + Enable the AIRINT interrupt + #1 + + + + + RXDSEN + no description available + 6 + 1 + read-write + + + 0 + Disable the RXDS interrupt + #0 + + + 1 + Enable the RXDS interrupt + #1 + + + + + ADNIMP + no description available + 7 + 1 + read-write + + + 0 + Autobaud detection new features selected + #0 + + + 1 + Keep old autobaud detection mechanism + #1 + + + + + RI + no description available + 8 + 1 + read-write + + + 0 + RI_B pin is logic zero (DCE mode) + #0 + + + 1 + RI_B pin is logic one (DCE mode) + #1 + + + 0 + RIDELT interrupt disabled (DTE mode) + #0 + + + 1 + RIDELT interrupt enabled (DTE mode) + #1 + + + + + DCD + no description available + 9 + 1 + read-write + + + 0 + DCD_B pin is logic zero (DCE mode) + #0 + + + 1 + DCD_B pin is logic one (DCE mode) + #1 + + + 0 + DCDDELT interrupt disabled (DTE mode) + #0 + + + 1 + DCDDELT interrupt enabled (DTE mode) + #1 + + + + + DSR + no description available + 10 + 1 + read-write + + + 0 + DSR/ DTR pin is logic zero + #0 + + + 1 + DSR/ DTR pin is logic one + #1 + + + + + FRAERREN + no description available + 11 + 1 + read-write + + + 0 + Disable the frame error interrupt + #0 + + + 1 + Enable the frame error interrupt + #1 + + + + + PARERREN + no description available + 12 + 1 + read-write + + + 0 + Disable the parity error interrupt + #0 + + + 1 + Enable the parity error interrupt + #1 + + + + + DTREN + no description available + 13 + 1 + read-write + + + 0 + Data Terminal Ready Interrupt Disabled + #0 + + + 1 + Data Terminal Ready Interrupt Enabled + #1 + + + + + DPEC + no description available + 14 + 2 + read-write + + + 00 + interrupt generated on rising edge + #00 + + + 01 + interrupt generated on falling edge + #01 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + no description available + 0 + 1 + read-write + + + 0 + Disable RDR interrupt + #0 + + + 1 + Enable RDR interrupt + #1 + + + + + OREN + no description available + 1 + 1 + read-write + + + 0 + Disable ORE interrupt + #0 + + + 1 + Enable ORE interrupt + #1 + + + + + BKEN + no description available + 2 + 1 + read-write + + + 0 + Disable the BRCD interrupt + #0 + + + 1 + Enable the BRCD interrupt + #1 + + + + + TCEN + no description available + 3 + 1 + read-write + + + 0 + Disable TXDC interrupt + #0 + + + 1 + Enable TXDC interrupt + #1 + + + + + LPBYP + no description available + 4 + 1 + read-write + + + 0 + Low power features enabled + #0 + + + 1 + Low power features disabled + #1 + + + + + IRSC + no description available + 5 + 1 + read-write + + + 0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + #0 + + + 1 + The vote logic uses the UART reference clock + #1 + + + + + IDDMAEN + no description available + 6 + 1 + read-write + + + 0 + DMA IDLE interrupt disabled + #0 + + + 1 + DMA IDLE interrupt enabled + #1 + + + + + WKEN + no description available + 7 + 1 + read-write + + + 0 + Disable the WAKE interrupt + #0 + + + 1 + Enable the WAKE interrupt + #1 + + + + + ENIRI + no description available + 8 + 1 + read-write + + + 0 + Serial infrared Interrupt disabled + #0 + + + 1 + Serial infrared Interrupt enabled + #1 + + + + + INVR + no description available + 9 + 1 + read-write + + + 0 + RXD input is not inverted + #0 + + + 1 + RXD input is inverted + #1 + + + 0 + RXD active low detection + #0 + + + 1 + RXD active high detection + #1 + + + + + CTSTL + no description available + 10 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + 1 characters in the RxFIFO + #000001 + + + 100000 + 32 characters in the RxFIFO (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + no description available + 0 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + RxFIFO has 1 character + #000001 + + + 011111 + RxFIFO has 31 characters + #011111 + + + 100000 + RxFIFO has 32 characters (maximum) + #100000 + + + + + DCEDTE + no description available + 6 + 1 + read-write + + + 0 + DCE mode selected + #0 + + + 1 + DTE mode selected + #1 + + + + + RFDIV + no description available + 7 + 3 + read-write + + + 000 + Divide input clock by 6 + #000 + + + 001 + Divide input clock by 5 + #001 + + + 010 + Divide input clock by 4 + #010 + + + 011 + Divide input clock by 3 + #011 + + + 100 + Divide input clock by 2 + #100 + + + 101 + Divide input clock by 1 + #101 + + + 110 + Divide input clock by 7 + #110 + + + 111 + Reserved + #111 + + + + + TXTL + no description available + 10 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + Reserved + #000001 + + + 000010 + TxFIFO has 2 or fewer characters + #000010 + + + 011111 + TxFIFO has 31 or fewer characters + #011111 + + + 100000 + TxFIFO has 32 characters (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + SAD + no description available + 3 + 1 + read-write + + + 0 + No slave address detected + #0 + + + 1 + Slave address detected + #1 + + + + + AWAKE + no description available + 4 + 1 + read-write + + + 0 + No falling edge was detected on the RXD Serial pin + #0 + + + 1 + A falling edge was detected on the RXD Serial pin + #1 + + + + + AIRINT + no description available + 5 + 1 + read-write + + + 0 + No pulse was detected on the RXD IrDA pin + #0 + + + 1 + A pulse was detected on the RXD IrDA pin + #1 + + + + + RXDS + no description available + 6 + 1 + read-only + + + 0 + Receive in progress + #0 + + + 1 + Receiver is IDLE + #1 + + + + + DTRD + no description available + 7 + 1 + read-write + + + 0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + #0 + + + 1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + #1 + + + + + AGTIM + no description available + 8 + 1 + read-write + + + 0 + AGTIM is not active + #0 + + + 1 + AGTIM is active (write 1 to clear) + #1 + + + + + RRDY + no description available + 9 + 1 + read-only + + + 0 + No character ready + #0 + + + 1 + Character(s) ready (interrupt posted) + #1 + + + + + FRAMERR + no description available + 10 + 1 + read-write + + + 0 + No frame error detected + #0 + + + 1 + Frame error detected (write 1 to clear) + #1 + + + + + ESCF + no description available + 11 + 1 + read-write + + + 0 + No escape sequence detected + #0 + + + 1 + Escape sequence detected (write 1 to clear). + #1 + + + + + RTSD + no description available + 12 + 1 + read-write + + + 0 + RTS_B pin did not change state since last cleared + #0 + + + 1 + RTS_B pin changed state (write 1 to clear) + #1 + + + + + TRDY + no description available + 13 + 1 + read-only + + + 0 + The transmitter does not require data + #0 + + + 1 + The transmitter requires data (interrupt posted) + #1 + + + + + RTSS + no description available + 14 + 1 + read-only + + + 0 + The RTS_B pin is high (inactive) + #0 + + + 1 + The RTS_B pin is low (active) + #1 + + + + + PARITYERR + no description available + 15 + 1 + read-write + + + 0 + No parity error detected + #0 + + + 1 + Parity error detected (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + no description available + 0 + 1 + read-only + + + 0 + No receive data ready + #0 + + + 1 + Receive data ready + #1 + + + + + ORE + no description available + 1 + 1 + read-write + + + 0 + No overrun error + #0 + + + 1 + Overrun error (write 1 to clear) + #1 + + + + + BRCD + no description available + 2 + 1 + read-write + + + 0 + No BREAK condition was detected + #0 + + + 1 + A BREAK condition was detected (write 1 to clear) + #1 + + + + + TXDC + no description available + 3 + 1 + read-only + + + 0 + Transmit is incomplete + #0 + + + 1 + Transmit is complete + #1 + + + + + RTSF + no description available + 4 + 1 + read-write + + + 0 + Programmed edge not detected on RTS_B + #0 + + + 1 + Programmed edge detected on RTS_B (write 1 to clear) + #1 + + + + + DCDIN + no description available + 5 + 1 + read-only + + + 0 + Carrier signal Detected + #0 + + + 1 + No Carrier signal Detected + #1 + + + + + DCDDELT + no description available + 6 + 1 + read-write + + + 0 + Data Carrier Detect input has not changed state + #0 + + + 1 + Data Carrier Detect input has changed state (write 1 to clear) + #1 + + + + + WAKE + no description available + 7 + 1 + read-write + + + 0 + start bit not detected + #0 + + + 1 + start bit detected (write 1 to clear) + #1 + + + + + IRINT + no description available + 8 + 1 + read-write + + + 0 + no edge detected + #0 + + + 1 + valid edge detected (write 1 to clear) + #1 + + + + + RIIN + no description available + 9 + 1 + read-only + + + 0 + Ring Detected + #0 + + + 1 + No Ring Detected + #1 + + + + + RIDELT + no description available + 10 + 1 + read-write + + + 0 + Ring Indicator input has not changed state + #0 + + + 1 + Ring Indicator input has changed state (write 1 to clear) + #1 + + + + + ACST + no description available + 11 + 1 + read-write + + + 0 + Measurement of bit length not finished (in autobaud) + #0 + + + 1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + #1 + + + + + IDLE + no description available + 12 + 1 + read-write + + + 0 + No idle condition detected + #0 + + + 1 + Idle condition detected (write 1 to clear) + #1 + + + + + DTRF + no description available + 13 + 1 + read-write + + + 0 + Programmed edge not detected on DTR/DSR + #0 + + + 1 + Programmed edge detected on DTR/DSR (write 1 to clear) + #1 + + + + + TXFE + no description available + 14 + 1 + read-only + + + 0 + The transmit buffer (TxFIFO) is not empty + #0 + + + 1 + The transmit buffer (TxFIFO) is empty + #1 + + + + + ADET + no description available + 15 + 1 + read-write + + + 0 + ASCII "A" or "a" was not received + #0 + + + 1 + ASCII "A" or "a" was received (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + no description available + 0 + 1 + read-write + + + 0 + Software reset inactive + #0 + + + 1 + Software reset active + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + RXFULL + no description available + 3 + 1 + read-write + + + 0 + The RxFIFO is not full + #0 + + + 1 + The RxFIFO is full + #1 + + + + + TXFULL + no description available + 4 + 1 + read-write + + + 0 + The TxFIFO is not full + #0 + + + 1 + The TxFIFO is full + #1 + + + + + RXEMPTY + no description available + 5 + 1 + read-write + + + 0 + The RxFIFO is not empty + #0 + + + 1 + The RxFIFO is empty + #1 + + + + + TXEMPTY + no description available + 6 + 1 + read-write + + + 0 + The TxFIFO is not empty + #0 + + + 1 + The TxFIFO is empty + #1 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + RXDBG + no description available + 9 + 1 + read-write + + + 0 + rx fifo read pointer does not increment + #0 + + + 1 + rx_fifo read pointer increments as normal + #1 + + + + + LOOPIR + no description available + 10 + 1 + read-write + + + 0 + No IR loop + #0 + + + 1 + Connect IR transmitter to IR receiver + #1 + + + + + DBGEN + no description available + 11 + 1 + read-write + + + 0 + UART will go into debug mode when debug_req is HIGH + #0 + + + 1 + UART will not go into debug mode even if debug_req is HIGH + #1 + + + + + LOOP + no description available + 12 + 1 + read-write + + + 0 + Normal receiver operation + #0 + + + 1 + Internally connect the transmitter output to the receiver input + #1 + + + + + FRCPERR + no description available + 13 + 1 + read-write + + + 0 + Generate normal parity + #0 + + + 1 + Generate inverted parity (error) + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + no description available + 0 + 1 + read-write + + + 0 + Normal RS-232 or IrDA mode, see for detail. + #0 + + + 1 + Enable RS-485 mode, see for detail + #1 + + + + + SLAM + no description available + 1 + 1 + read-write + + + 0 + Select Normal Address Detect mode + #0 + + + 1 + Select Automatic Address Detect mode + #1 + + + + + TXB8 + no description available + 2 + 1 + read-write + + + 0 + 0 will be transmitted as the RS485 9th data bit + #0 + + + 1 + 1 will be transmitted as the RS485 9th data bit + #1 + + + + + SADEN + no description available + 3 + 1 + read-write + + + 0 + Disable RS-485 Slave Address Detected Interrupt + #0 + + + 1 + Enable RS-485 Slave Address Detected Interrupt + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SLADDR + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + UART5 + UARTv2 + UART + UART5_ + 0x21F4000 + + 0 + 0xBC + registers + + + + URXD + UART Receiver Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RX_DATA + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 2 + read-only + + + PRERR + no description available + 10 + 1 + read-only + + + 0 + = No parity error was detected for data in the RX_DATA field + #0 + + + 1 + = A parity error was detected for data in the RX_DATA field + #1 + + + + + BRK + no description available + 11 + 1 + read-only + + + 0 + The current character is not a BREAK character + #0 + + + 1 + The current character is a BREAK character + #1 + + + + + FRMERR + no description available + 12 + 1 + read-only + + + 0 + The current character has no framing error + #0 + + + 1 + The current character has a framing error + #1 + + + + + OVRRUN + no description available + 13 + 1 + read-only + + + 0 + No RxFIFO overrun was detected + #0 + + + 1 + A RxFIFO overrun was detected + #1 + + + + + ERR + no description available + 14 + 1 + read-only + + + 0 + No error status was detected + #0 + + + 1 + An error status was detected + #1 + + + + + CHARRDY + no description available + 15 + 1 + read-only + + + 0 + Character in RX_DATA field and associated flags are invalid. + #0 + + + 1 + Character in RX_DATA field and associated flags valid and ready for reading. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UTXD + UART Transmitter Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_DATA + no description available + 0 + 8 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR1 + UART Control Register 1 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + UARTEN + no description available + 0 + 1 + read-write + + + 0 + Disable the UART + #0 + + + 1 + Enable the UART + #1 + + + + + DOZE + no description available + 1 + 1 + read-write + + + 0 + The UART is enabled when in DOZE state + #0 + + + 1 + The UART is disabled when in DOZE state + #1 + + + + + ATDMAEN + no description available + 2 + 1 + read-write + + + 0 + Disable AGTIM DMA request + #0 + + + 1 + Enable AGTIM DMA request + #1 + + + + + TXDMAEN + no description available + 3 + 1 + read-write + + + 0 + Disable transmit DMA request + #0 + + + 1 + Enable transmit DMA request + #1 + + + + + SNDBRK + no description available + 4 + 1 + read-write + + + 0 + Do not send a BREAK character + #0 + + + 1 + Send a BREAK character (continuous 0s) + #1 + + + + + RTSDEN + no description available + 5 + 1 + read-write + + + 0 + Disable RTSD interrupt + #0 + + + 1 + Enable RTSD interrupt + #1 + + + + + TXMPTYEN + no description available + 6 + 1 + read-write + + + 0 + Disable the transmitter FIFO empty interrupt + #0 + + + 1 + Enable the transmitter FIFO empty interrupt + #1 + + + + + IREN + no description available + 7 + 1 + read-write + + + 0 + Disable the IR interface + #0 + + + 1 + Enable the IR interface + #1 + + + + + RXDMAEN + no description available + 8 + 1 + read-write + + + 0 + Disable DMA request + #0 + + + 1 + Enable DMA request + #1 + + + + + RRDYEN + no description available + 9 + 1 + read-write + + + 0 + Disables the RRDY interrupt + #0 + + + 1 + Enables the RRDY interrupt + #1 + + + + + ICD + no description available + 10 + 2 + read-write + + + 00 + Idle for more than 4 frames + #00 + + + 01 + Idle for more than 8 frames + #01 + + + 10 + Idle for more than 16 frames + #10 + + + 11 + Idle for more than 32 frames + #11 + + + + + IDEN + no description available + 12 + 1 + read-write + + + 0 + Disable the IDLE interrupt + #0 + + + 1 + Enable the IDLE interrupt + #1 + + + + + TRDYEN + no description available + 13 + 1 + read-write + + + 0 + Disable the transmitter ready interrupt + #0 + + + 1 + Enable the transmitter ready interrupt + #1 + + + + + ADBR + no description available + 14 + 1 + read-write + + + 0 + Disable automatic detection of baud rate + #0 + + + 1 + Enable automatic detection of baud rate + #1 + + + + + ADEN + no description available + 15 + 1 + read-write + + + 0 + Disable the automatic baud rate detection interrupt + #0 + + + 1 + Enable the automatic baud rate detection interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR2 + UART Control Register 2 + 0x84 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + SRST + no description available + 0 + 1 + read-write + + + 0 + Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3]. + #0 + + + 1 + No reset + #1 + + + + + RXEN + no description available + 1 + 1 + read-write + + + 0 + Disable the receiver + #0 + + + 1 + Enable the receiver + #1 + + + + + TXEN + no description available + 2 + 1 + read-write + + + 0 + Disable the transmitter + #0 + + + 1 + Enable the transmitter + #1 + + + + + ATEN + no description available + 3 + 1 + read-write + + + 0 + AGTIM interrupt disabled + #0 + + + 1 + AGTIM interrupt enabled + #1 + + + + + RTSEN + no description available + 4 + 1 + read-write + + + 0 + Disable request to send interrupt + #0 + + + 1 + Enable request to send interrupt + #1 + + + + + WS + no description available + 5 + 1 + read-write + + + 0 + 7-bit transmit and receive character length (not including START, STOP or PARITY bits) + #0 + + + 1 + 8-bit transmit and receive character length (not including START, STOP or PARITY bits) + #1 + + + + + STPB + no description available + 6 + 1 + read-write + + + 0 + The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits. + #0 + + + 1 + The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits. + #1 + + + + + PROE + no description available + 7 + 1 + read-write + + + 0 + Even parity + #0 + + + 1 + Odd parity + #1 + + + + + PREN + no description available + 8 + 1 + read-write + + + 0 + Disable parity generator and checker + #0 + + + 1 + Enable parity generator and checker + #1 + + + + + RTEC + no description available + 9 + 2 + read-write + + + 00 + Trigger interrupt on a rising edge + #00 + + + 01 + Trigger interrupt on a falling edge + #01 + + + + + ESCEN + no description available + 11 + 1 + read-write + + + 0 + Disable escape sequence detection + #0 + + + 1 + Enable escape sequence detection + #1 + + + + + CTS + no description available + 12 + 1 + read-write + + + 0 + The CTS_B pin is high (inactive) + #0 + + + 1 + The CTS_B pin is low (active) + #1 + + + + + CTSC + no description available + 13 + 1 + read-write + + + 0 + The CTS_B pin is controlled by the CTS bit + #0 + + + 1 + The CTS_B pin is controlled by the receiver + #1 + + + + + IRTS + no description available + 14 + 1 + read-write + + + 0 + Transmit only when the RTS pin is asserted + #0 + + + 1 + Ignore the RTS pin + #1 + + + + + ESCI + no description available + 15 + 1 + read-write + + + 0 + Disable the escape sequence interrupt + #0 + + + 1 + Enable the escape sequence interrupt + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR3 + UART Control Register 3 + 0x88 + 32 + read-write + 0x700 + 0xFFFFFFFF + + + ACIEN + no description available + 0 + 1 + read-write + + + 0 + ACST interrupt disabled + #0 + + + 1 + ACST interrupt enabled + #1 + + + + + INVT + no description available + 1 + 1 + read-write + + + 0 + TXD is not inverted + #0 + + + 1 + TXD is inverted + #1 + + + 0 + TXD Active low transmission + #0 + + + 1 + TXD Active high transmission + #1 + + + + + RXDMUXSEL + no description available + 2 + 1 + read-write + + + DTRDEN + no description available + 3 + 1 + read-write + + + 0 + Disable DTRD interrupt + #0 + + + 1 + Enable DTRD interrupt + #1 + + + + + AWAKEN + no description available + 4 + 1 + read-write + + + 0 + Disable the AWAKE interrupt + #0 + + + 1 + Enable the AWAKE interrupt + #1 + + + + + AIRINTEN + no description available + 5 + 1 + read-write + + + 0 + Disable the AIRINT interrupt + #0 + + + 1 + Enable the AIRINT interrupt + #1 + + + + + RXDSEN + no description available + 6 + 1 + read-write + + + 0 + Disable the RXDS interrupt + #0 + + + 1 + Enable the RXDS interrupt + #1 + + + + + ADNIMP + no description available + 7 + 1 + read-write + + + 0 + Autobaud detection new features selected + #0 + + + 1 + Keep old autobaud detection mechanism + #1 + + + + + RI + no description available + 8 + 1 + read-write + + + 0 + RI_B pin is logic zero (DCE mode) + #0 + + + 1 + RI_B pin is logic one (DCE mode) + #1 + + + 0 + RIDELT interrupt disabled (DTE mode) + #0 + + + 1 + RIDELT interrupt enabled (DTE mode) + #1 + + + + + DCD + no description available + 9 + 1 + read-write + + + 0 + DCD_B pin is logic zero (DCE mode) + #0 + + + 1 + DCD_B pin is logic one (DCE mode) + #1 + + + 0 + DCDDELT interrupt disabled (DTE mode) + #0 + + + 1 + DCDDELT interrupt enabled (DTE mode) + #1 + + + + + DSR + no description available + 10 + 1 + read-write + + + 0 + DSR/ DTR pin is logic zero + #0 + + + 1 + DSR/ DTR pin is logic one + #1 + + + + + FRAERREN + no description available + 11 + 1 + read-write + + + 0 + Disable the frame error interrupt + #0 + + + 1 + Enable the frame error interrupt + #1 + + + + + PARERREN + no description available + 12 + 1 + read-write + + + 0 + Disable the parity error interrupt + #0 + + + 1 + Enable the parity error interrupt + #1 + + + + + DTREN + no description available + 13 + 1 + read-write + + + 0 + Data Terminal Ready Interrupt Disabled + #0 + + + 1 + Data Terminal Ready Interrupt Enabled + #1 + + + + + DPEC + no description available + 14 + 2 + read-write + + + 00 + interrupt generated on rising edge + #00 + + + 01 + interrupt generated on falling edge + #01 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UCR4 + UART Control Register 4 + 0x8C + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + DREN + no description available + 0 + 1 + read-write + + + 0 + Disable RDR interrupt + #0 + + + 1 + Enable RDR interrupt + #1 + + + + + OREN + no description available + 1 + 1 + read-write + + + 0 + Disable ORE interrupt + #0 + + + 1 + Enable ORE interrupt + #1 + + + + + BKEN + no description available + 2 + 1 + read-write + + + 0 + Disable the BRCD interrupt + #0 + + + 1 + Enable the BRCD interrupt + #1 + + + + + TCEN + no description available + 3 + 1 + read-write + + + 0 + Disable TXDC interrupt + #0 + + + 1 + Enable TXDC interrupt + #1 + + + + + LPBYP + no description available + 4 + 1 + read-write + + + 0 + Low power features enabled + #0 + + + 1 + Low power features disabled + #1 + + + + + IRSC + no description available + 5 + 1 + read-write + + + 0 + The vote logic uses the sampling clock (16x baud rate) for normal operation + #0 + + + 1 + The vote logic uses the UART reference clock + #1 + + + + + IDDMAEN + no description available + 6 + 1 + read-write + + + 0 + DMA IDLE interrupt disabled + #0 + + + 1 + DMA IDLE interrupt enabled + #1 + + + + + WKEN + no description available + 7 + 1 + read-write + + + 0 + Disable the WAKE interrupt + #0 + + + 1 + Enable the WAKE interrupt + #1 + + + + + ENIRI + no description available + 8 + 1 + read-write + + + 0 + Serial infrared Interrupt disabled + #0 + + + 1 + Serial infrared Interrupt enabled + #1 + + + + + INVR + no description available + 9 + 1 + read-write + + + 0 + RXD input is not inverted + #0 + + + 1 + RXD input is inverted + #1 + + + 0 + RXD active low detection + #0 + + + 1 + RXD active high detection + #1 + + + + + CTSTL + no description available + 10 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + 1 characters in the RxFIFO + #000001 + + + 100000 + 32 characters in the RxFIFO (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UFCR + UART FIFO Control Register + 0x90 + 32 + read-write + 0x801 + 0xFFFFFFFF + + + RXTL + no description available + 0 + 6 + read-write + + + 000000 + 0 characters received + #000000 + + + 000001 + RxFIFO has 1 character + #000001 + + + 011111 + RxFIFO has 31 characters + #011111 + + + 100000 + RxFIFO has 32 characters (maximum) + #100000 + + + + + DCEDTE + no description available + 6 + 1 + read-write + + + 0 + DCE mode selected + #0 + + + 1 + DTE mode selected + #1 + + + + + RFDIV + no description available + 7 + 3 + read-write + + + 000 + Divide input clock by 6 + #000 + + + 001 + Divide input clock by 5 + #001 + + + 010 + Divide input clock by 4 + #010 + + + 011 + Divide input clock by 3 + #011 + + + 100 + Divide input clock by 2 + #100 + + + 101 + Divide input clock by 1 + #101 + + + 110 + Divide input clock by 7 + #110 + + + 111 + Reserved + #111 + + + + + TXTL + no description available + 10 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + Reserved + #000001 + + + 000010 + TxFIFO has 2 or fewer characters + #000010 + + + 011111 + TxFIFO has 31 or fewer characters + #011111 + + + 100000 + TxFIFO has 32 characters (maximum) + #100000 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR1 + UART Status Register 1 + 0x94 + 32 + read-write + 0x2040 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + SAD + no description available + 3 + 1 + read-write + + + 0 + No slave address detected + #0 + + + 1 + Slave address detected + #1 + + + + + AWAKE + no description available + 4 + 1 + read-write + + + 0 + No falling edge was detected on the RXD Serial pin + #0 + + + 1 + A falling edge was detected on the RXD Serial pin + #1 + + + + + AIRINT + no description available + 5 + 1 + read-write + + + 0 + No pulse was detected on the RXD IrDA pin + #0 + + + 1 + A pulse was detected on the RXD IrDA pin + #1 + + + + + RXDS + no description available + 6 + 1 + read-only + + + 0 + Receive in progress + #0 + + + 1 + Receiver is IDLE + #1 + + + + + DTRD + no description available + 7 + 1 + read-write + + + 0 + DTR_B (DCE) or DSR_B (DTE) pin did not change state since last cleared + #0 + + + 1 + DTR_B (DCE) or DSR_B (DTE) pin changed state (write 1 to clear) + #1 + + + + + AGTIM + no description available + 8 + 1 + read-write + + + 0 + AGTIM is not active + #0 + + + 1 + AGTIM is active (write 1 to clear) + #1 + + + + + RRDY + no description available + 9 + 1 + read-only + + + 0 + No character ready + #0 + + + 1 + Character(s) ready (interrupt posted) + #1 + + + + + FRAMERR + no description available + 10 + 1 + read-write + + + 0 + No frame error detected + #0 + + + 1 + Frame error detected (write 1 to clear) + #1 + + + + + ESCF + no description available + 11 + 1 + read-write + + + 0 + No escape sequence detected + #0 + + + 1 + Escape sequence detected (write 1 to clear). + #1 + + + + + RTSD + no description available + 12 + 1 + read-write + + + 0 + RTS_B pin did not change state since last cleared + #0 + + + 1 + RTS_B pin changed state (write 1 to clear) + #1 + + + + + TRDY + no description available + 13 + 1 + read-only + + + 0 + The transmitter does not require data + #0 + + + 1 + The transmitter requires data (interrupt posted) + #1 + + + + + RTSS + no description available + 14 + 1 + read-only + + + 0 + The RTS_B pin is high (inactive) + #0 + + + 1 + The RTS_B pin is low (active) + #1 + + + + + PARITYERR + no description available + 15 + 1 + read-write + + + 0 + No parity error detected + #0 + + + 1 + Parity error detected (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + USR2 + UART Status Register 2 + 0x98 + 32 + read-write + 0x4028 + 0xFFFFFFFF + + + RDR + no description available + 0 + 1 + read-only + + + 0 + No receive data ready + #0 + + + 1 + Receive data ready + #1 + + + + + ORE + no description available + 1 + 1 + read-write + + + 0 + No overrun error + #0 + + + 1 + Overrun error (write 1 to clear) + #1 + + + + + BRCD + no description available + 2 + 1 + read-write + + + 0 + No BREAK condition was detected + #0 + + + 1 + A BREAK condition was detected (write 1 to clear) + #1 + + + + + TXDC + no description available + 3 + 1 + read-only + + + 0 + Transmit is incomplete + #0 + + + 1 + Transmit is complete + #1 + + + + + RTSF + no description available + 4 + 1 + read-write + + + 0 + Programmed edge not detected on RTS_B + #0 + + + 1 + Programmed edge detected on RTS_B (write 1 to clear) + #1 + + + + + DCDIN + no description available + 5 + 1 + read-only + + + 0 + Carrier signal Detected + #0 + + + 1 + No Carrier signal Detected + #1 + + + + + DCDDELT + no description available + 6 + 1 + read-write + + + 0 + Data Carrier Detect input has not changed state + #0 + + + 1 + Data Carrier Detect input has changed state (write 1 to clear) + #1 + + + + + WAKE + no description available + 7 + 1 + read-write + + + 0 + start bit not detected + #0 + + + 1 + start bit detected (write 1 to clear) + #1 + + + + + IRINT + no description available + 8 + 1 + read-write + + + 0 + no edge detected + #0 + + + 1 + valid edge detected (write 1 to clear) + #1 + + + + + RIIN + no description available + 9 + 1 + read-only + + + 0 + Ring Detected + #0 + + + 1 + No Ring Detected + #1 + + + + + RIDELT + no description available + 10 + 1 + read-write + + + 0 + Ring Indicator input has not changed state + #0 + + + 1 + Ring Indicator input has changed state (write 1 to clear) + #1 + + + + + ACST + no description available + 11 + 1 + read-write + + + 0 + Measurement of bit length not finished (in autobaud) + #0 + + + 1 + Measurement of bit length finished (in autobaud). (write 1 to clear) + #1 + + + + + IDLE + no description available + 12 + 1 + read-write + + + 0 + No idle condition detected + #0 + + + 1 + Idle condition detected (write 1 to clear) + #1 + + + + + DTRF + no description available + 13 + 1 + read-write + + + 0 + Programmed edge not detected on DTR/DSR + #0 + + + 1 + Programmed edge detected on DTR/DSR (write 1 to clear) + #1 + + + + + TXFE + no description available + 14 + 1 + read-only + + + 0 + The transmit buffer (TxFIFO) is not empty + #0 + + + 1 + The transmit buffer (TxFIFO) is empty + #1 + + + + + ADET + no description available + 15 + 1 + read-write + + + 0 + ASCII "A" or "a" was not received + #0 + + + 1 + ASCII "A" or "a" was received (write 1 to clear) + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UESC + UART Escape Character Register + 0x9C + 32 + read-write + 0x2B + 0xFFFFFFFF + + + ESC_CHAR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + UTIM + UART Escape Timer Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIM + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + UBIR + UART BRM Incremental Register + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBMR + UART BRM Modulator Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + UBRC + UART Baud Rate Count Register + 0xAC + 32 + read-only + 0x4 + 0xFFFFFFFF + + + BCNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ONEMS + UART One Millisecond Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ONEMS + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + UTS + UART Test Register + 0xB4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + SOFTRST + no description available + 0 + 1 + read-write + + + 0 + Software reset inactive + #0 + + + 1 + Software reset active + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + RXFULL + no description available + 3 + 1 + read-write + + + 0 + The RxFIFO is not full + #0 + + + 1 + The RxFIFO is full + #1 + + + + + TXFULL + no description available + 4 + 1 + read-write + + + 0 + The TxFIFO is not full + #0 + + + 1 + The TxFIFO is full + #1 + + + + + RXEMPTY + no description available + 5 + 1 + read-write + + + 0 + The RxFIFO is not empty + #0 + + + 1 + The RxFIFO is empty + #1 + + + + + TXEMPTY + no description available + 6 + 1 + read-write + + + 0 + The TxFIFO is not empty + #0 + + + 1 + The TxFIFO is empty + #1 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + RXDBG + no description available + 9 + 1 + read-write + + + 0 + rx fifo read pointer does not increment + #0 + + + 1 + rx_fifo read pointer increments as normal + #1 + + + + + LOOPIR + no description available + 10 + 1 + read-write + + + 0 + No IR loop + #0 + + + 1 + Connect IR transmitter to IR receiver + #1 + + + + + DBGEN + no description available + 11 + 1 + read-write + + + 0 + UART will go into debug mode when debug_req is HIGH + #0 + + + 1 + UART will not go into debug mode even if debug_req is HIGH + #1 + + + + + LOOP + no description available + 12 + 1 + read-write + + + 0 + Normal receiver operation + #0 + + + 1 + Internally connect the transmitter output to the receiver input + #1 + + + + + FRCPERR + no description available + 13 + 1 + read-write + + + 0 + Generate normal parity + #0 + + + 1 + Generate inverted parity (error) + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + UMCR + UART RS-485 Mode Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MDEN + no description available + 0 + 1 + read-write + + + 0 + Normal RS-232 or IrDA mode, see for detail. + #0 + + + 1 + Enable RS-485 mode, see for detail + #1 + + + + + SLAM + no description available + 1 + 1 + read-write + + + 0 + Select Normal Address Detect mode + #0 + + + 1 + Select Automatic Address Detect mode + #1 + + + + + TXB8 + no description available + 2 + 1 + read-write + + + 0 + 0 will be transmitted as the RS485 9th data bit + #0 + + + 1 + 1 will be transmitted as the RS485 9th data bit + #1 + + + + + SADEN + no description available + 3 + 1 + read-write + + + 0 + Disable RS-485 Slave Address Detected Interrupt + #0 + + + 1 + Enable RS-485 Slave Address Detected Interrupt + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SLADDR + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + ESAI + Enhanced Serial Audio Interface + ESAI_ + 0x2024000 + + 0 + 0x100 + registers + + + + ETDR + ESAI Transmit Data Register + 0 + 32 + write-only + 0 + 0xFFFFFFFF + + + ETDR + no description available + 0 + 32 + write-only + + + + + ERDR + ESAI Receive Data Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERDR + no description available + 0 + 32 + read-only + + + + + ECR + ESAI Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ESAIEN + no description available + 0 + 1 + read-write + + + 0 + ESAI disabled. + #0 + + + 1 + ESAI enabled. + #1 + + + + + ERST + no description available + 1 + 1 + read-write + + + 0 + ESAI not reset. + #0 + + + 1 + ESAI reset. + #1 + + + + + RESERVED + no description available + 2 + 14 + read-only + + + ERO + no description available + 16 + 1 + read-write + + + 0 + HCKR pin has normal function. + #0 + + + 1 + EXTAL driven onto HCKR pin. + #1 + + + + + ERI + no description available + 17 + 1 + read-write + + + 0 + HCKR pin has normal function. + #0 + + + 1 + EXTAL muxed into HCKR input. + #1 + + + + + ETO + no description available + 18 + 1 + read-write + + + 0 + HCKT pin has normal function. + #0 + + + 1 + EXTAL driven onto HCKT pin. + #1 + + + + + ETI + no description available + 19 + 1 + read-write + + + 0 + HCKT pin has normal function. + #0 + + + 1 + EXTAL muxed into HCKT input. + #1 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + ESR + ESAI Status Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + RD + no description available + 0 + 1 + read-only + + + 0 + RD is not the highest priority active interrupt. + #0 + + + 1 + RD is the highest priority active interrupt. + #1 + + + + + RED + no description available + 1 + 1 + read-only + + + 0 + RED is not the highest priority active interrupt. + #0 + + + 1 + RED is the highest priority active interrupt. + #1 + + + + + RDE + no description available + 2 + 1 + read-only + + + 0 + RDE is not the highest priority active interrupt. + #0 + + + 1 + RDE is the highest priority active interrupt. + #1 + + + + + RLS + no description available + 3 + 1 + read-only + + + 0 + RLS is not the highest priority active interrupt. + #0 + + + 1 + RLS is the highest priority active interrupt. + #1 + + + + + TD + no description available + 4 + 1 + read-only + + + 0 + TD is not the highest priority active interrupt. + #0 + + + 1 + TD is the highest priority active interrupt. + #1 + + + + + TED + no description available + 5 + 1 + read-only + + + 0 + TED is not the highest priority active interrupt. + #0 + + + 1 + TED is the highest priority active interrupt. + #1 + + + + + TDE + no description available + 6 + 1 + read-only + + + 0 + TDE is not the highest priority active interrupt. + #0 + + + 1 + TDE is the highest priority active interrupt. + #1 + + + + + TLS + no description available + 7 + 1 + read-only + + + 0 + TLS is not the highest priority active interrupt. + #0 + + + 1 + TLS is the highest priority active interrupt. + #1 + + + + + TFE + no description available + 8 + 1 + read-only + + + 0 + Number of empty slots in Transmit FIFO less than Transmit FIFO watermark. + #0 + + + 1 + Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark. + #1 + + + + + RFF + no description available + 9 + 1 + read-only + + + 0 + Number of words in Receive FIFO less than Receive FIFO watermark. + #0 + + + 1 + Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark. + #1 + + + + + TINIT + no description available + 10 + 1 + read-only + + + 0 + Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled). + #0 + + + 1 + Transmitter has not finished initializing the Transmit Data Registers. + #1 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + TFCR + Transmit FIFO Configuration Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFE + no description available + 0 + 1 + read-write + + + 0 + Transmit FIFO disabled. + #0 + + + 1 + Transmit FIFO enabled. + #1 + + + + + TFR + no description available + 1 + 1 + read-write + + + 0 + Transmit FIFO not reset. + #0 + + + 1 + Transmit FIFO reset. + #1 + + + + + TE0 + no description available + 2 + 1 + read-write + + + 0 + Transmitter #0 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #0 is using the Transmit FIFO. + #1 + + + + + TE1 + no description available + 3 + 1 + read-write + + + 0 + Transmitter #1 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #1 is using the Transmit FIFO. + #1 + + + + + TE2 + no description available + 4 + 1 + read-write + + + 0 + Transmitter #2 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #2 is using the Transmit FIFO. + #1 + + + + + TE3 + no description available + 5 + 1 + read-write + + + 0 + Transmitter #3 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #3 is using the Transmit FIFO. + #1 + + + + + TE4 + no description available + 6 + 1 + read-write + + + 0 + Transmitter #4 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #4 is using the Transmit FIFO. + #1 + + + + + TE5 + no description available + 7 + 1 + read-write + + + 0 + Transmitter #5 is not using the Transmit FIFO. + #0 + + + 1 + Transmitter #5 is using the Transmit FIFO. + #1 + + + + + TFWM + no description available + 8 + 8 + read-write + + + TWA + no description available + 16 + 3 + read-write + + + 000 + MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register. + #000 + + + 001 + MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register. + #001 + + + 010 + MSB of data is bit 23. + #010 + + + 011 + MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed. + #011 + + + 100 + MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed. + #100 + + + 101 + MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed. + #101 + + + 110 + MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed. + #110 + + + 111 + MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed. + #111 + + + + + TIEN + no description available + 19 + 1 + read-write + + + 0 + Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately. + #0 + + + 1 + Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled. + #1 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + TFSR + Transmit FIFO Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TFCNT + no description available + 0 + 8 + read-only + + + NTFI + no description available + 8 + 3 + read-only + + + 000 + Transmitter #0 receives next word written to the Transmit FIFO. + #000 + + + 001 + Transmitter #1 receives next word written to the Transmit FIFO. + #001 + + + 010 + Transmitter #2 receives next word written to the Transmit FIFO. + #010 + + + 011 + Transmitter #3 receives next word written to the Transmit FIFO. + #011 + + + 100 + Transmitter #4 receives next word written to the Transmit FIFO. + #100 + + + 101 + Transmitter #5 receives next word written to the Transmit FIFO. + #101 + + + 110 + Reserved. + #110 + + + 111 + Reserved. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + NTFO + no description available + 12 + 3 + read-only + + + 000 + Transmitter #0 receives next word from the Transmit FIFO. + #000 + + + 001 + Transmitter #1 receives next word from the Transmit FIFO. + #001 + + + 010 + Transmitter #2 receives next word from the Transmit FIFO. + #010 + + + 011 + Transmitter #3 receives next word from the Transmit FIFO. + #011 + + + 100 + Transmitter #4 receives next word from the Transmit FIFO. + #100 + + + 101 + Transmitter #5 receives next word from the Transmit FIFO. + #101 + + + 110 + Reserved. + #110 + + + 111 + Reserved. + #111 + + + + + RESERVED + no description available + 15 + 17 + read-only + + + + + RFCR + Receive FIFO Configuration Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + RFE + no description available + 0 + 1 + read-write + + + 0 + Receive FIFO disabled. + #0 + + + 1 + Receive FIFO enabled. + #1 + + + + + RFR + no description available + 1 + 1 + read-write + + + 0 + Receive FIFO not reset. + #0 + + + 1 + Receive FIFO reset. + #1 + + + + + RE0 + no description available + 2 + 1 + read-write + + + 0 + Receiver #0 is not using the Receive FIFO. + #0 + + + 1 + Receiver #0 is using the Receive FIFO. + #1 + + + + + RE1 + no description available + 3 + 1 + read-write + + + 0 + Receiver #1 is not using the Receive FIFO. + #0 + + + 1 + Receiver #1 is using the Receive FIFO. + #1 + + + + + RE2 + no description available + 4 + 1 + read-write + + + 0 + Receiver #2 is not using the Receive FIFO. + #0 + + + 1 + Receiver #2 is using the Receive FIFO. + #1 + + + + + RE3 + no description available + 5 + 1 + read-write + + + 0 + Receiver #3 is not using the Receive FIFO. + #0 + + + 1 + Receiver #3 is using the Receive FIFO. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + RFWM + no description available + 8 + 8 + read-write + + + RWA + no description available + 16 + 3 + read-write + + + 000 + MSB of data is at bit 31. Data bits 7-0 are zeroed. + #000 + + + 001 + MSB of data is at bit 27. Data bits 3-0 are zeroed. + #001 + + + 010 + MSB of data is at bit 23. + #010 + + + 011 + MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored. + #011 + + + 100 + MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored. + #100 + + + 101 + MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored. + #101 + + + 110 + MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored. + #110 + + + 111 + MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored. + #111 + + + + + REXT + no description available + 19 + 1 + read-write + + + 0 + Receive data is zero extended. + #0 + + + 1 + Receive data is sign extended. + #1 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + RFSR + Receive FIFO Status Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RFCNT + no description available + 0 + 8 + read-only + + + NRFO + no description available + 8 + 2 + read-only + + + 00 + Receiver #0 returns next word from the Receive FIFO. + #00 + + + 01 + Receiver #1 returns next word from the Receive FIFO. + #01 + + + 10 + Receiver #2 returns next word from the Receive FIFO. + #10 + + + 11 + Receiver #3 returns next word from the Receive FIFO. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + NRFI + no description available + 12 + 2 + read-only + + + 00 + Receiver #0 returns next word to the Receive FIFO. + #00 + + + 01 + Receiver #1 returns next word to the Receive FIFO. + #01 + + + 10 + Receiver #2 returns next word to the Receive FIFO. + #10 + + + 11 + Receiver #3 returns next word to the Receive FIFO. + #11 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + 6 + 0x4 + 0,1,2,3,4,5 + TX%s + Transmit Data Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXn + no description available + 0 + 24 + write-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + TSR + ESAI Transmit Slot Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSR + no description available + 0 + 24 + write-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + RX%s + Receive Data Register n + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXn + no description available + 0 + 24 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + SAISR + Serial Audio Interface Status Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + IF0 + no description available + 0 + 1 + read-only + + + IF1 + no description available + 1 + 1 + read-only + + + IF2 + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 3 + read-only + + + RFS + no description available + 6 + 1 + read-only + + + ROE + no description available + 7 + 1 + read-only + + + RDF + no description available + 8 + 1 + read-only + + + REDF + no description available + 9 + 1 + read-only + + + RODF + no description available + 10 + 1 + read-only + + + RESERVED + no description available + 11 + 2 + read-only + + + TFS + no description available + 13 + 1 + read-only + + + TUE + no description available + 14 + 1 + read-only + + + TDE + no description available + 15 + 1 + read-only + + + TEDE + no description available + 16 + 1 + read-only + + + TODFE + no description available + 17 + 1 + read-only + + + RESERVED + no description available + 18 + 14 + read-only + + + + + SAICR + Serial Audio Interface Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF0 + no description available + 0 + 1 + read-write + + + OF1 + no description available + 1 + 1 + read-write + + + OF2 + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 3 + read-only + + + SYN + no description available + 6 + 1 + read-write + + + TEBE + no description available + 7 + 1 + read-write + + + ALC + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + TCR + Transmit Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TE0 + no description available + 0 + 1 + read-write + + + TE1 + no description available + 1 + 1 + read-write + + + TE2 + no description available + 2 + 1 + read-write + + + TE3 + no description available + 3 + 1 + read-write + + + TE4 + no description available + 4 + 1 + read-write + + + TE5 + no description available + 5 + 1 + read-write + + + TSHFD + no description available + 6 + 1 + read-write + + + TWA + no description available + 7 + 1 + read-write + + + TMOD + no description available + 8 + 2 + read-write + + + TSWS + no description available + 10 + 5 + read-write + + + TFSL + no description available + 15 + 1 + read-write + + + TFSR + no description available + 16 + 1 + read-write + + + PADC + no description available + 17 + 1 + read-write + + + RESERVED + no description available + 18 + 1 + read-only + + + TPR + no description available + 19 + 1 + read-write + + + TEIE + no description available + 20 + 1 + read-write + + + TEDIE + no description available + 21 + 1 + read-write + + + TIE + no description available + 22 + 1 + read-write + + + TLIE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + TCCR + Transmit Clock Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TPM + no description available + 0 + 8 + read-write + + + TPSR + no description available + 8 + 1 + read-write + + + TDC + no description available + 9 + 5 + read-write + + + TFP + no description available + 14 + 4 + read-write + + + TCKP + no description available + 18 + 1 + read-write + + + TFSP + no description available + 19 + 1 + read-write + + + THCKP + no description available + 20 + 1 + read-write + + + TCKD + no description available + 21 + 1 + read-write + + + TFSD + no description available + 22 + 1 + read-write + + + THCKD + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + RCR + Receive Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RE0 + no description available + 0 + 1 + read-write + + + RE1 + no description available + 1 + 1 + read-write + + + RE2 + no description available + 2 + 1 + read-write + + + RE3 + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 2 + read-only + + + RSHFD + no description available + 6 + 1 + read-write + + + RWA + no description available + 7 + 1 + read-write + + + RMOD + no description available + 8 + 2 + read-write + + + RSWS + no description available + 10 + 5 + read-write + + + RFSL + no description available + 15 + 1 + read-write + + + RFSR + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 2 + read-only + + + RPR + no description available + 19 + 1 + read-write + + + REIE + no description available + 20 + 1 + read-write + + + REDIE + no description available + 21 + 1 + read-write + + + RIE + no description available + 22 + 1 + read-write + + + RLIE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + RCCR + Receive Clock Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RPM + no description available + 0 + 8 + read-write + + + RPSR + no description available + 8 + 1 + read-write + + + RDC + no description available + 9 + 5 + read-write + + + RFP + no description available + 14 + 4 + read-write + + + RCKP + no description available + 18 + 1 + read-write + + + RFSP + no description available + 19 + 1 + read-write + + + RHCKP + no description available + 20 + 1 + read-write + + + RCKD + no description available + 21 + 1 + read-write + + + RFSD + no description available + 22 + 1 + read-write + + + RHCKD + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + TSMA + Transmit Slot Mask Register A + 0xE4 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + TSMB + Transmit Slot Mask Register B + 0xE8 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + TS + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + RSMA + Receive Slot Mask Register A + 0xEC + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + RSMB + Receive Slot Mask Register B + 0xF0 + 32 + read-write + 0xFFFF + 0xFFFFFFFF + + + RS + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PRRC + Port C Direction Register + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PDC + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + PCRC + Port C Control Register + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + PC + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + + + SSI1 + SSI + SSI + SSI1_ + 0x2028000 + + 0 + 0x5C + registers + + + + 2 + 0x4 + 0,1 + STX%s + SSI Transmit Data Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + STXn + no description available + 0 + 32 + read-write + + + + + 2 + 0x4 + 0,1 + SRX%s + SSI Receive Data Register n + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + SRXn + no description available + 0 + 32 + read-only + + + + + SCR + SSI Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIEN + no description available + 0 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + TE + no description available + 1 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + RE + no description available + 2 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + NET + no description available + 3 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + SYN + no description available + 4 + 1 + read-write + + + 0 + ASYNC_MODE + #0 + + + 1 + SYNC_MODE + #1 + + + + + I2S_MODE + no description available + 5 + 2 + read-write + + + SYS_CLK_EN + no description available + 7 + 1 + read-write + + + 0 + NOT_OUTPUT + #0 + + + 1 + OUTPUT + #1 + + + + + TCH_EN + no description available + 8 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + CLK_IST + no description available + 9 + 1 + read-write + + + 0 + IDLE_0 + #0 + + + 1 + IDLE_1 + #1 + + + + + TFR_CLK_DIS + no description available + 10 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + RFR_CLK_DIS + no description available + 11 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + SYNC_TX_FS + no description available + 12 + 1 + read-write + + + 0 + TE_NOT_LATCHED + #0 + + + 1 + TE_LATCHED + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + SISR + SSI Interrupt Status Register + 0x14 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0 + no description available + 0 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + TFE1 + no description available + 1 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + RFF0 + no description available + 2 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RFF1 + no description available + 3 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RLS + no description available + 4 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last receive time slot of frame. + #1 + + + + + TLS + no description available + 5 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last transmit time slot of frame. + #1 + + + + + RFS + no description available + 6 + 1 + read-only + + + 0 + No Occurrence of Receive frame sync. + #0 + + + 1 + Receive frame sync occurred during reception of next word in SRX registers. + #1 + + + + + TFS + no description available + 7 + 1 + read-only + + + 0 + No Occurrence of Transmit frame sync. + #0 + + + 1 + Transmit frame sync occurred during transmission of last word written to STX registers. + #1 + + + + + TUE0 + no description available + 8 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TUE1 + no description available + 9 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE0 + no description available + 10 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE1 + no description available + 11 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TDE0 + no description available + 12 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + TDE1 + no description available + 13 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + RDR0 + no description available + 14 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RDR1 + no description available + 15 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RXT + no description available + 16 + 1 + read-only + + + 0 + No change in SATAG register. + #0 + + + 1 + SATAG register updated with different value. + #1 + + + + + CMDDU + no description available + 17 + 1 + read-only + + + 0 + No change in SACDAT register. + #0 + + + 1 + SACDAT register updated with different value. + #1 + + + + + CMDAU + no description available + 18 + 1 + read-only + + + 0 + No change in SACADD register. + #0 + + + 1 + SACADD register updated with different value. + #1 + + + + + RESERVED + no description available + 19 + 4 + read-only + + + TFRC + no description available + 23 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling TE or disabling TFR_CLK_DIS, when transmitter is already disabled. + #1 + + + + + RFRC + no description available + 24 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling RE or disabling RFR_CLK_DIS, when receiver is already disabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + SIER + SSI Interrupt Enable Register + 0x18 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0IE + no description available + 0 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFE1IE + no description available + 1 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF0IE + no description available + 2 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF1IE + no description available + 3 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RLSIE + no description available + 4 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TLSIE + no description available + 5 + 1 + read-only + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFSIE + no description available + 6 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFSIE + no description available + 7 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE0IE + no description available + 8 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE1IE + no description available + 9 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE0IE + no description available + 10 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE1IE + no description available + 11 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE0IE + no description available + 12 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE1IE + no description available + 13 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR0IE + no description available + 14 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR1IE + no description available + 15 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RXTIE + no description available + 16 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDDUIE + no description available + 17 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDAUIE + no description available + 18 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TIE + no description available + 19 + 1 + read-write + + + 0 + SSI Transmitter Interrupt requests disabled. + #0 + + + 1 + SSI Transmitter Interrupt requests enabled. + #1 + + + + + TDMAE + no description available + 20 + 1 + read-write + + + 0 + SSI Transmitter DMA requests disabled. + #0 + + + 1 + SSI Transmitter DMA requests enabled. + #1 + + + + + RIE + no description available + 21 + 1 + read-write + + + 0 + SSI Receiver Interrupt requests disabled. + #0 + + + 1 + SSI Receiver Interrupt requests enabled. + #1 + + + + + RDMAE + no description available + 22 + 1 + read-write + + + 0 + SSI Receiver DMA requests disabled. + #0 + + + 1 + SSI Receiver DMA requests enabled. + #1 + + + + + TFRCIE + no description available + 23 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFRCIE + no description available + 24 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + STCR + SSI Transmit Configuration Register + 0x1C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + TEFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + TFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + TFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + TSCKP + no description available + 3 + 1 + read-write + + + 0 + RISING_EDGE + #0 + + + 1 + FALLING_EDGE + #1 + + + + + TSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + TXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFEN0 + no description available + 7 + 1 + read-write + + + 0 + Transmit FIFO 0 disabled. + #0 + + + 1 + Transmit FIFO 0 enabled. + #1 + + + + + TFEN1 + no description available + 8 + 1 + read-write + + + 0 + Transmit FIFO 1 disabled. + #0 + + + 1 + Transmit FIFO 1 enabled. + #1 + + + + + TXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SRCR + SSI Receive Configuration Register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + REFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + RFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + RFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + RSCKP + no description available + 3 + 1 + read-write + + + 0 + FALLING_EDGE + #0 + + + 1 + RISING_EDGE + #1 + + + + + RSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + RXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFEN0 + no description available + 7 + 1 + read-write + + + 0 + Receive FIFO 0 disabled. + #0 + + + 1 + Receive FIFO 0 enabled. + #1 + + + + + RFEN1 + no description available + 8 + 1 + read-write + + + 0 + Receive FIFO 1 disabled. + #0 + + + 1 + Receive FIFO 1 enabled. + #1 + + + + + RXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RXEXT + no description available + 10 + 1 + read-write + + + 0 + OFF + #0 + + + 1 + ON + #1 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + STCCR + SSI Transmit Clock Control Register + 0x24 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SRCCR + SSI Receive Clock Control Register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SFCSR + SSI FIFO Control/Status Register + 0x2C + 32 + read-write + 0x810081 + 0xFFFFFFFF + + + TFWM0 + no description available + 0 + 4 + read-write + + + RFWM0 + no description available + 4 + 4 + read-write + + + TFCNT0 + no description available + 8 + 4 + read-write + + + RFCNT0 + no description available + 12 + 4 + read-write + + + TFWM1 + no description available + 16 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + TFE set when there are more than or equal to 1 empty slots in Transmit FIFO (default). Transmit FIFO empty is set when TxFIFO <= 14 data. + #0001 + + + 0010 + TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=13 data. + #0010 + + + 0011 + TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=12 data. + #0011 + + + 0100 + TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=11 data. + #0100 + + + 0101 + TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=10 data. + #0101 + + + 0110 + TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=9 data. + #0110 + + + 0111 + TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=8 data. + #0111 + + + 1000 + TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=7 data. + #1000 + + + 1001 + TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 6 data. + #1001 + + + 1010 + TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 5 data. + #1010 + + + 1011 + TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 4 data. + #1011 + + + 1100 + TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 3 data. + #1100 + + + 1101 + TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 2 data. + #1101 + + + 1110 + TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data. + #1110 + + + 1111 + TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data. + #1111 + + + + + RFWM1 + no description available + 20 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + RFF set when at least one data word has been written to the Receive FIFO. Set when RxFIFO = 1,2.....15 data words + #0001 + + + 0010 + RFF set when 2 or more data words have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words + #0010 + + + 0011 + RFF set when 3 or more data words have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words + #0011 + + + 0100 + RFF set when 4 or more data words have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words + #0100 + + + 0101 + RFF set when 5 or more data words have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words + #0101 + + + 0110 + RFF set when 6 or more data words have been written to the Receive.. Set when RxFIFO = 6,7......15 data words + #0110 + + + 0111 + RFF set when 7 or more data words have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words + #0111 + + + 1000 + RFF set when 8 or more data words have been written to the Receive FIFO. Set when RxFIFO =8,9..... 15 data words + #1000 + + + 1001 + RFF set when 9 or more data words have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words + #1001 + + + 1010 + RFF set when 10 or more data words have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words + #1010 + + + 1011 + RFF set when 11 or more data words have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words + #1011 + + + 1100 + RFF set when 12 or more data words have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words + #1100 + + + 1101 + RFF set when 13 or more data words have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words + #1101 + + + 1110 + RFF set when 14 or more data words have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words + #1110 + + + 1111 + RFF set when 15 data words have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words + #1111 + + + + + TFCNT1 + no description available + 24 + 4 + read-write + + + 0000 + 0 data word in transmit FIFO + #0000 + + + 0001 + 1 data word in transmit FIFO + #0001 + + + 0010 + 2 data word in transmit FIFO + #0010 + + + 0011 + 3 data word in transmit FIFO + #0011 + + + 0100 + 4 data word in transmit FIFO + #0100 + + + 0101 + 5 data word in transmit FIFO + #0101 + + + 0110 + 6 data word in transmit FIFO + #0110 + + + 0111 + 7 data word in transmit FIFO + #0111 + + + 1000 + 8 data word in transmit FIFO + #1000 + + + 1001 + 9 data word in transmit FIFO + #1001 + + + 1010 + 10 data word in transmit FIFO + #1010 + + + 1011 + 11 data word in transmit FIFO + #1011 + + + 1100 + 12 data word in transmit FIFO + #1100 + + + 1101 + 13 data word in transmit FIFO + #1101 + + + 1110 + 14 data word in transmit FIFO + #1110 + + + 1111 + 15 data word in transmit FIFO + #1111 + + + + + RFCNT1 + no description available + 28 + 4 + read-write + + + 0000 + 0 data word in receive FIFO + #0000 + + + 0001 + 1 data word in receive FIFO + #0001 + + + 0010 + 2 data word in receive FIFO + #0010 + + + 0011 + 3 data word in receive FIFO + #0011 + + + 0100 + 4 data word in receive FIFO + #0100 + + + 0101 + 5 data word in receive FIFO + #0101 + + + 0110 + 6 data word in receive FIFO + #0110 + + + 0111 + 7 data word in receive FIFO + #0111 + + + 1000 + 8 data word in receive FIFO + #1000 + + + 1001 + 9 data word in receive FIFO + #1001 + + + 1010 + 10 data word in receive FIFO + #1010 + + + 1011 + 11 data word in receive FIFO + #1011 + + + 1100 + 12 data word in receive FIFO + #1100 + + + 1101 + 13 data word in receive FIFO + #1101 + + + 1110 + 14 data word in receive FIFO + #1110 + + + 1111 + 15 data word in receive FIFO + #1111 + + + + + + + SACNT + SSI AC97 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + AC97EN + no description available + 0 + 1 + read-write + + + 0 + AC97 mode disabled. + #0 + + + 1 + SSI in AC97 mode. + #1 + + + + + FV + no description available + 1 + 1 + read-write + + + 0 + FIXED + #0 + + + 1 + VARIABLE + #1 + + + + + TIF + no description available + 2 + 1 + read-write + + + 0 + SATAG_REGISTER + #0 + + + 1 + RX_FIFO0 + #1 + + + + + RD + no description available + 3 + 1 + read-write + + + 0 + Next frame will not have a Read Command. + #0 + + + 1 + Next frame will have a Read Command. + #1 + + + + + WR + no description available + 4 + 1 + read-write + + + 0 + Next frame will not have a Write Command. + #0 + + + 1 + Next frame will have a Write Command. + #1 + + + + + FRDIV + no description available + 5 + 6 + read-write + + + RESERVED + no description available + 11 + 21 + read-only + + + + + SACADD + SSI AC97 Command Address Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + SACADD + no description available + 0 + 19 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SACDAT + SSI AC97 Command Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACDAT + no description available + 0 + 20 + read-write + + + RESERVED + no description available + 20 + 12 + read-only + + + + + SATAG + SSI AC97 Tag Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + SATAG + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + STMSK + SSI Transmit Time Slot Mask Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + STMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data transmitted in this time slot). + #1 + + + + + + + SRMSK + SSI Receive Time Slot Mask Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + SRMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data received in this time slot). + #1 + + + + + + + SACCST + SSI AC97 Channel Status Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + SACCST + no description available + 0 + 10 + read-only + + + 0 + Data channel disabled. + #0 + + + 1 + Data channel enabled. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCEN + SSI AC97 Channel Enable Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCEN + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Enables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCDIS + SSI AC97 Channel Disable Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCDIS + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Disables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + SSI2 + SSI + SSI + SSI2_ + 0x202C000 + + 0 + 0x5C + registers + + + + 2 + 0x4 + 0,1 + STX%s + SSI Transmit Data Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + STXn + no description available + 0 + 32 + read-write + + + + + 2 + 0x4 + 0,1 + SRX%s + SSI Receive Data Register n + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + SRXn + no description available + 0 + 32 + read-only + + + + + SCR + SSI Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIEN + no description available + 0 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + TE + no description available + 1 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + RE + no description available + 2 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + NET + no description available + 3 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + SYN + no description available + 4 + 1 + read-write + + + 0 + ASYNC_MODE + #0 + + + 1 + SYNC_MODE + #1 + + + + + I2S_MODE + no description available + 5 + 2 + read-write + + + SYS_CLK_EN + no description available + 7 + 1 + read-write + + + 0 + NOT_OUTPUT + #0 + + + 1 + OUTPUT + #1 + + + + + TCH_EN + no description available + 8 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + CLK_IST + no description available + 9 + 1 + read-write + + + 0 + IDLE_0 + #0 + + + 1 + IDLE_1 + #1 + + + + + TFR_CLK_DIS + no description available + 10 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + RFR_CLK_DIS + no description available + 11 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + SYNC_TX_FS + no description available + 12 + 1 + read-write + + + 0 + TE_NOT_LATCHED + #0 + + + 1 + TE_LATCHED + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + SISR + SSI Interrupt Status Register + 0x14 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0 + no description available + 0 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + TFE1 + no description available + 1 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + RFF0 + no description available + 2 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RFF1 + no description available + 3 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RLS + no description available + 4 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last receive time slot of frame. + #1 + + + + + TLS + no description available + 5 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last transmit time slot of frame. + #1 + + + + + RFS + no description available + 6 + 1 + read-only + + + 0 + No Occurrence of Receive frame sync. + #0 + + + 1 + Receive frame sync occurred during reception of next word in SRX registers. + #1 + + + + + TFS + no description available + 7 + 1 + read-only + + + 0 + No Occurrence of Transmit frame sync. + #0 + + + 1 + Transmit frame sync occurred during transmission of last word written to STX registers. + #1 + + + + + TUE0 + no description available + 8 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TUE1 + no description available + 9 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE0 + no description available + 10 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE1 + no description available + 11 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TDE0 + no description available + 12 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + TDE1 + no description available + 13 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + RDR0 + no description available + 14 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RDR1 + no description available + 15 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RXT + no description available + 16 + 1 + read-only + + + 0 + No change in SATAG register. + #0 + + + 1 + SATAG register updated with different value. + #1 + + + + + CMDDU + no description available + 17 + 1 + read-only + + + 0 + No change in SACDAT register. + #0 + + + 1 + SACDAT register updated with different value. + #1 + + + + + CMDAU + no description available + 18 + 1 + read-only + + + 0 + No change in SACADD register. + #0 + + + 1 + SACADD register updated with different value. + #1 + + + + + RESERVED + no description available + 19 + 4 + read-only + + + TFRC + no description available + 23 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling TE or disabling TFR_CLK_DIS, when transmitter is already disabled. + #1 + + + + + RFRC + no description available + 24 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling RE or disabling RFR_CLK_DIS, when receiver is already disabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + SIER + SSI Interrupt Enable Register + 0x18 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0IE + no description available + 0 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFE1IE + no description available + 1 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF0IE + no description available + 2 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF1IE + no description available + 3 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RLSIE + no description available + 4 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TLSIE + no description available + 5 + 1 + read-only + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFSIE + no description available + 6 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFSIE + no description available + 7 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE0IE + no description available + 8 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE1IE + no description available + 9 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE0IE + no description available + 10 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE1IE + no description available + 11 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE0IE + no description available + 12 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE1IE + no description available + 13 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR0IE + no description available + 14 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR1IE + no description available + 15 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RXTIE + no description available + 16 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDDUIE + no description available + 17 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDAUIE + no description available + 18 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TIE + no description available + 19 + 1 + read-write + + + 0 + SSI Transmitter Interrupt requests disabled. + #0 + + + 1 + SSI Transmitter Interrupt requests enabled. + #1 + + + + + TDMAE + no description available + 20 + 1 + read-write + + + 0 + SSI Transmitter DMA requests disabled. + #0 + + + 1 + SSI Transmitter DMA requests enabled. + #1 + + + + + RIE + no description available + 21 + 1 + read-write + + + 0 + SSI Receiver Interrupt requests disabled. + #0 + + + 1 + SSI Receiver Interrupt requests enabled. + #1 + + + + + RDMAE + no description available + 22 + 1 + read-write + + + 0 + SSI Receiver DMA requests disabled. + #0 + + + 1 + SSI Receiver DMA requests enabled. + #1 + + + + + TFRCIE + no description available + 23 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFRCIE + no description available + 24 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + STCR + SSI Transmit Configuration Register + 0x1C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + TEFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + TFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + TFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + TSCKP + no description available + 3 + 1 + read-write + + + 0 + RISING_EDGE + #0 + + + 1 + FALLING_EDGE + #1 + + + + + TSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + TXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFEN0 + no description available + 7 + 1 + read-write + + + 0 + Transmit FIFO 0 disabled. + #0 + + + 1 + Transmit FIFO 0 enabled. + #1 + + + + + TFEN1 + no description available + 8 + 1 + read-write + + + 0 + Transmit FIFO 1 disabled. + #0 + + + 1 + Transmit FIFO 1 enabled. + #1 + + + + + TXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SRCR + SSI Receive Configuration Register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + REFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + RFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + RFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + RSCKP + no description available + 3 + 1 + read-write + + + 0 + FALLING_EDGE + #0 + + + 1 + RISING_EDGE + #1 + + + + + RSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + RXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFEN0 + no description available + 7 + 1 + read-write + + + 0 + Receive FIFO 0 disabled. + #0 + + + 1 + Receive FIFO 0 enabled. + #1 + + + + + RFEN1 + no description available + 8 + 1 + read-write + + + 0 + Receive FIFO 1 disabled. + #0 + + + 1 + Receive FIFO 1 enabled. + #1 + + + + + RXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RXEXT + no description available + 10 + 1 + read-write + + + 0 + OFF + #0 + + + 1 + ON + #1 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + STCCR + SSI Transmit Clock Control Register + 0x24 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SRCCR + SSI Receive Clock Control Register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SFCSR + SSI FIFO Control/Status Register + 0x2C + 32 + read-write + 0x810081 + 0xFFFFFFFF + + + TFWM0 + no description available + 0 + 4 + read-write + + + RFWM0 + no description available + 4 + 4 + read-write + + + TFCNT0 + no description available + 8 + 4 + read-write + + + RFCNT0 + no description available + 12 + 4 + read-write + + + TFWM1 + no description available + 16 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + TFE set when there are more than or equal to 1 empty slots in Transmit FIFO (default). Transmit FIFO empty is set when TxFIFO <= 14 data. + #0001 + + + 0010 + TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=13 data. + #0010 + + + 0011 + TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=12 data. + #0011 + + + 0100 + TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=11 data. + #0100 + + + 0101 + TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=10 data. + #0101 + + + 0110 + TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=9 data. + #0110 + + + 0111 + TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=8 data. + #0111 + + + 1000 + TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=7 data. + #1000 + + + 1001 + TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 6 data. + #1001 + + + 1010 + TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 5 data. + #1010 + + + 1011 + TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 4 data. + #1011 + + + 1100 + TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 3 data. + #1100 + + + 1101 + TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 2 data. + #1101 + + + 1110 + TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data. + #1110 + + + 1111 + TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data. + #1111 + + + + + RFWM1 + no description available + 20 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + RFF set when at least one data word has been written to the Receive FIFO. Set when RxFIFO = 1,2.....15 data words + #0001 + + + 0010 + RFF set when 2 or more data words have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words + #0010 + + + 0011 + RFF set when 3 or more data words have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words + #0011 + + + 0100 + RFF set when 4 or more data words have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words + #0100 + + + 0101 + RFF set when 5 or more data words have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words + #0101 + + + 0110 + RFF set when 6 or more data words have been written to the Receive.. Set when RxFIFO = 6,7......15 data words + #0110 + + + 0111 + RFF set when 7 or more data words have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words + #0111 + + + 1000 + RFF set when 8 or more data words have been written to the Receive FIFO. Set when RxFIFO =8,9..... 15 data words + #1000 + + + 1001 + RFF set when 9 or more data words have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words + #1001 + + + 1010 + RFF set when 10 or more data words have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words + #1010 + + + 1011 + RFF set when 11 or more data words have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words + #1011 + + + 1100 + RFF set when 12 or more data words have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words + #1100 + + + 1101 + RFF set when 13 or more data words have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words + #1101 + + + 1110 + RFF set when 14 or more data words have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words + #1110 + + + 1111 + RFF set when 15 data words have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words + #1111 + + + + + TFCNT1 + no description available + 24 + 4 + read-write + + + 0000 + 0 data word in transmit FIFO + #0000 + + + 0001 + 1 data word in transmit FIFO + #0001 + + + 0010 + 2 data word in transmit FIFO + #0010 + + + 0011 + 3 data word in transmit FIFO + #0011 + + + 0100 + 4 data word in transmit FIFO + #0100 + + + 0101 + 5 data word in transmit FIFO + #0101 + + + 0110 + 6 data word in transmit FIFO + #0110 + + + 0111 + 7 data word in transmit FIFO + #0111 + + + 1000 + 8 data word in transmit FIFO + #1000 + + + 1001 + 9 data word in transmit FIFO + #1001 + + + 1010 + 10 data word in transmit FIFO + #1010 + + + 1011 + 11 data word in transmit FIFO + #1011 + + + 1100 + 12 data word in transmit FIFO + #1100 + + + 1101 + 13 data word in transmit FIFO + #1101 + + + 1110 + 14 data word in transmit FIFO + #1110 + + + 1111 + 15 data word in transmit FIFO + #1111 + + + + + RFCNT1 + no description available + 28 + 4 + read-write + + + 0000 + 0 data word in receive FIFO + #0000 + + + 0001 + 1 data word in receive FIFO + #0001 + + + 0010 + 2 data word in receive FIFO + #0010 + + + 0011 + 3 data word in receive FIFO + #0011 + + + 0100 + 4 data word in receive FIFO + #0100 + + + 0101 + 5 data word in receive FIFO + #0101 + + + 0110 + 6 data word in receive FIFO + #0110 + + + 0111 + 7 data word in receive FIFO + #0111 + + + 1000 + 8 data word in receive FIFO + #1000 + + + 1001 + 9 data word in receive FIFO + #1001 + + + 1010 + 10 data word in receive FIFO + #1010 + + + 1011 + 11 data word in receive FIFO + #1011 + + + 1100 + 12 data word in receive FIFO + #1100 + + + 1101 + 13 data word in receive FIFO + #1101 + + + 1110 + 14 data word in receive FIFO + #1110 + + + 1111 + 15 data word in receive FIFO + #1111 + + + + + + + SACNT + SSI AC97 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + AC97EN + no description available + 0 + 1 + read-write + + + 0 + AC97 mode disabled. + #0 + + + 1 + SSI in AC97 mode. + #1 + + + + + FV + no description available + 1 + 1 + read-write + + + 0 + FIXED + #0 + + + 1 + VARIABLE + #1 + + + + + TIF + no description available + 2 + 1 + read-write + + + 0 + SATAG_REGISTER + #0 + + + 1 + RX_FIFO0 + #1 + + + + + RD + no description available + 3 + 1 + read-write + + + 0 + Next frame will not have a Read Command. + #0 + + + 1 + Next frame will have a Read Command. + #1 + + + + + WR + no description available + 4 + 1 + read-write + + + 0 + Next frame will not have a Write Command. + #0 + + + 1 + Next frame will have a Write Command. + #1 + + + + + FRDIV + no description available + 5 + 6 + read-write + + + RESERVED + no description available + 11 + 21 + read-only + + + + + SACADD + SSI AC97 Command Address Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + SACADD + no description available + 0 + 19 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SACDAT + SSI AC97 Command Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACDAT + no description available + 0 + 20 + read-write + + + RESERVED + no description available + 20 + 12 + read-only + + + + + SATAG + SSI AC97 Tag Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + SATAG + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + STMSK + SSI Transmit Time Slot Mask Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + STMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data transmitted in this time slot). + #1 + + + + + + + SRMSK + SSI Receive Time Slot Mask Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + SRMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data received in this time slot). + #1 + + + + + + + SACCST + SSI AC97 Channel Status Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + SACCST + no description available + 0 + 10 + read-only + + + 0 + Data channel disabled. + #0 + + + 1 + Data channel enabled. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCEN + SSI AC97 Channel Enable Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCEN + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Enables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCDIS + SSI AC97 Channel Disable Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCDIS + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Disables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + SSI3 + SSI + SSI + SSI3_ + 0x2030000 + + 0 + 0x5C + registers + + + + 2 + 0x4 + 0,1 + STX%s + SSI Transmit Data Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + STXn + no description available + 0 + 32 + read-write + + + + + 2 + 0x4 + 0,1 + SRX%s + SSI Receive Data Register n + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + SRXn + no description available + 0 + 32 + read-only + + + + + SCR + SSI Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIEN + no description available + 0 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + TE + no description available + 1 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + RE + no description available + 2 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + NET + no description available + 3 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + SYN + no description available + 4 + 1 + read-write + + + 0 + ASYNC_MODE + #0 + + + 1 + SYNC_MODE + #1 + + + + + I2S_MODE + no description available + 5 + 2 + read-write + + + SYS_CLK_EN + no description available + 7 + 1 + read-write + + + 0 + NOT_OUTPUT + #0 + + + 1 + OUTPUT + #1 + + + + + TCH_EN + no description available + 8 + 1 + read-write + + + 0 + DISABLED + #0 + + + 1 + ENABLED + #1 + + + + + CLK_IST + no description available + 9 + 1 + read-write + + + 0 + IDLE_0 + #0 + + + 1 + IDLE_1 + #1 + + + + + TFR_CLK_DIS + no description available + 10 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + RFR_CLK_DIS + no description available + 11 + 1 + read-write + + + 0 + CONTINUE + #0 + + + 1 + STOP + #1 + + + + + SYNC_TX_FS + no description available + 12 + 1 + read-write + + + 0 + TE_NOT_LATCHED + #0 + + + 1 + TE_LATCHED + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + SISR + SSI Interrupt Status Register + 0x14 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0 + no description available + 0 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + TFE1 + no description available + 1 + 1 + read-only + + + 0 + HAS_DATA + #0 + + + 1 + EMPTY + #1 + + + + + RFF0 + no description available + 2 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RFF1 + no description available + 3 + 1 + read-only + + + 0 + NOT_FULL + #0 + + + 1 + FULL + #1 + + + + + RLS + no description available + 4 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last receive time slot of frame. + #1 + + + + + TLS + no description available + 5 + 1 + read-only + + + 0 + Current time slot is not last time slot of frame. + #0 + + + 1 + Current time slot is the last transmit time slot of frame. + #1 + + + + + RFS + no description available + 6 + 1 + read-only + + + 0 + No Occurrence of Receive frame sync. + #0 + + + 1 + Receive frame sync occurred during reception of next word in SRX registers. + #1 + + + + + TFS + no description available + 7 + 1 + read-only + + + 0 + No Occurrence of Transmit frame sync. + #0 + + + 1 + Transmit frame sync occurred during transmission of last word written to STX registers. + #1 + + + + + TUE0 + no description available + 8 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TUE1 + no description available + 9 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE0 + no description available + 10 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + ROE1 + no description available + 11 + 1 + read-write + + + 0 + Default interrupt issued to the Core. + #0 + + + 1 + Exception interrupt issued to the Core. + #1 + + + + + TDE0 + no description available + 12 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + TDE1 + no description available + 13 + 1 + read-only + + + 0 + Data available for transmission. + #0 + + + 1 + Data needs to be written by the Core for transmission. + #1 + + + + + RDR0 + no description available + 14 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RDR1 + no description available + 15 + 1 + read-only + + + 0 + No new data for Core to read. + #0 + + + 1 + New data for Core to read. + #1 + + + + + RXT + no description available + 16 + 1 + read-only + + + 0 + No change in SATAG register. + #0 + + + 1 + SATAG register updated with different value. + #1 + + + + + CMDDU + no description available + 17 + 1 + read-only + + + 0 + No change in SACDAT register. + #0 + + + 1 + SACDAT register updated with different value. + #1 + + + + + CMDAU + no description available + 18 + 1 + read-only + + + 0 + No change in SACADD register. + #0 + + + 1 + SACADD register updated with different value. + #1 + + + + + RESERVED + no description available + 19 + 4 + read-only + + + TFRC + no description available + 23 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling TE or disabling TFR_CLK_DIS, when transmitter is already disabled. + #1 + + + + + RFRC + no description available + 24 + 1 + read-only + + + 0 + End of Frame not reached + #0 + + + 1 + End of frame reached after disabling RE or disabling RFR_CLK_DIS, when receiver is already disabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + SIER + SSI Interrupt Enable Register + 0x18 + 32 + read-write + 0x3003 + 0xFFFFFFFF + + + TFE0IE + no description available + 0 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFE1IE + no description available + 1 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF0IE + no description available + 2 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFF1IE + no description available + 3 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RLSIE + no description available + 4 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TLSIE + no description available + 5 + 1 + read-only + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFSIE + no description available + 6 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TFSIE + no description available + 7 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE0IE + no description available + 8 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TUE1IE + no description available + 9 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE0IE + no description available + 10 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + ROE1IE + no description available + 11 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE0IE + no description available + 12 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TDE1IE + no description available + 13 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR0IE + no description available + 14 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RDR1IE + no description available + 15 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RXTIE + no description available + 16 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDDUIE + no description available + 17 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + CMDAUIE + no description available + 18 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + TIE + no description available + 19 + 1 + read-write + + + 0 + SSI Transmitter Interrupt requests disabled. + #0 + + + 1 + SSI Transmitter Interrupt requests enabled. + #1 + + + + + TDMAE + no description available + 20 + 1 + read-write + + + 0 + SSI Transmitter DMA requests disabled. + #0 + + + 1 + SSI Transmitter DMA requests enabled. + #1 + + + + + RIE + no description available + 21 + 1 + read-write + + + 0 + SSI Receiver Interrupt requests disabled. + #0 + + + 1 + SSI Receiver Interrupt requests enabled. + #1 + + + + + RDMAE + no description available + 22 + 1 + read-write + + + 0 + SSI Receiver DMA requests disabled. + #0 + + + 1 + SSI Receiver DMA requests enabled. + #1 + + + + + TFRCIE + no description available + 23 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RFRCIE + no description available + 24 + 1 + read-write + + + 0 + Corresponding status bit cannot issue interrupt. + #0 + + + 1 + Corresponding status bit can issue interrupt. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + STCR + SSI Transmit Configuration Register + 0x1C + 32 + read-write + 0x200 + 0xFFFFFFFF + + + TEFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + TFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + TFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + TSCKP + no description available + 3 + 1 + read-write + + + 0 + RISING_EDGE + #0 + + + 1 + FALLING_EDGE + #1 + + + + + TSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + TXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + TFEN0 + no description available + 7 + 1 + read-write + + + 0 + Transmit FIFO 0 disabled. + #0 + + + 1 + Transmit FIFO 0 enabled. + #1 + + + + + TFEN1 + no description available + 8 + 1 + read-write + + + 0 + Transmit FIFO 1 disabled. + #0 + + + 1 + Transmit FIFO 1 enabled. + #1 + + + + + TXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SRCR + SSI Receive Configuration Register + 0x20 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + REFS + no description available + 0 + 1 + read-write + + + 0 + FIRST_BIT + #0 + + + 1 + ONE_BIT_BEFORE + #1 + + + + + RFSL + no description available + 1 + 1 + read-write + + + 0 + ONE_WORD + #0 + + + 1 + ONE_CLOCK_BIT + #1 + + + + + RFSI + no description available + 2 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + RSCKP + no description available + 3 + 1 + read-write + + + 0 + FALLING_EDGE + #0 + + + 1 + RISING_EDGE + #1 + + + + + RSHFD + no description available + 4 + 1 + read-write + + + 0 + MSB_FIRST + #0 + + + 1 + LSB_FIRST + #1 + + + + + RXDIR + no description available + 5 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFDIR + no description available + 6 + 1 + read-write + + + 0 + EXTERNAL + #0 + + + 1 + INTERNAL + #1 + + + + + RFEN0 + no description available + 7 + 1 + read-write + + + 0 + Receive FIFO 0 disabled. + #0 + + + 1 + Receive FIFO 0 enabled. + #1 + + + + + RFEN1 + no description available + 8 + 1 + read-write + + + 0 + Receive FIFO 1 disabled. + #0 + + + 1 + Receive FIFO 1 enabled. + #1 + + + + + RXBIT0 + no description available + 9 + 1 + read-write + + + 0 + MSB_ALIGNED + #0 + + + 1 + LSB_ALIGNED + #1 + + + + + RXEXT + no description available + 10 + 1 + read-write + + + 0 + OFF + #0 + + + 1 + ON + #1 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + STCCR + SSI Transmit Clock Control Register + 0x24 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SRCCR + SSI Receive Clock Control Register + 0x28 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + PM7_PM0 + no description available + 0 + 8 + read-write + + + DC4_DC0 + no description available + 8 + 5 + read-write + + + WL3_WL0 + no description available + 13 + 4 + read-write + + + PSR + no description available + 17 + 1 + read-write + + + DIV2 + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SFCSR + SSI FIFO Control/Status Register + 0x2C + 32 + read-write + 0x810081 + 0xFFFFFFFF + + + TFWM0 + no description available + 0 + 4 + read-write + + + RFWM0 + no description available + 4 + 4 + read-write + + + TFCNT0 + no description available + 8 + 4 + read-write + + + RFCNT0 + no description available + 12 + 4 + read-write + + + TFWM1 + no description available + 16 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + TFE set when there are more than or equal to 1 empty slots in Transmit FIFO (default). Transmit FIFO empty is set when TxFIFO <= 14 data. + #0001 + + + 0010 + TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=13 data. + #0010 + + + 0011 + TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=12 data. + #0011 + + + 0100 + TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=11 data. + #0100 + + + 0101 + TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=10 data. + #0101 + + + 0110 + TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=9 data. + #0110 + + + 0111 + TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=8 data. + #0111 + + + 1000 + TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=7 data. + #1000 + + + 1001 + TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 6 data. + #1001 + + + 1010 + TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 5 data. + #1010 + + + 1011 + TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 4 data. + #1011 + + + 1100 + TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 3 data. + #1100 + + + 1101 + TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 2 data. + #1101 + + + 1110 + TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data. + #1110 + + + 1111 + TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data. + #1111 + + + + + RFWM1 + no description available + 20 + 4 + read-write + + + 0000 + Reserved + #0000 + + + 0001 + RFF set when at least one data word has been written to the Receive FIFO. Set when RxFIFO = 1,2.....15 data words + #0001 + + + 0010 + RFF set when 2 or more data words have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words + #0010 + + + 0011 + RFF set when 3 or more data words have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words + #0011 + + + 0100 + RFF set when 4 or more data words have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words + #0100 + + + 0101 + RFF set when 5 or more data words have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words + #0101 + + + 0110 + RFF set when 6 or more data words have been written to the Receive.. Set when RxFIFO = 6,7......15 data words + #0110 + + + 0111 + RFF set when 7 or more data words have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words + #0111 + + + 1000 + RFF set when 8 or more data words have been written to the Receive FIFO. Set when RxFIFO =8,9..... 15 data words + #1000 + + + 1001 + RFF set when 9 or more data words have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words + #1001 + + + 1010 + RFF set when 10 or more data words have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words + #1010 + + + 1011 + RFF set when 11 or more data words have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words + #1011 + + + 1100 + RFF set when 12 or more data words have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words + #1100 + + + 1101 + RFF set when 13 or more data words have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words + #1101 + + + 1110 + RFF set when 14 or more data words have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words + #1110 + + + 1111 + RFF set when 15 data words have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words + #1111 + + + + + TFCNT1 + no description available + 24 + 4 + read-write + + + 0000 + 0 data word in transmit FIFO + #0000 + + + 0001 + 1 data word in transmit FIFO + #0001 + + + 0010 + 2 data word in transmit FIFO + #0010 + + + 0011 + 3 data word in transmit FIFO + #0011 + + + 0100 + 4 data word in transmit FIFO + #0100 + + + 0101 + 5 data word in transmit FIFO + #0101 + + + 0110 + 6 data word in transmit FIFO + #0110 + + + 0111 + 7 data word in transmit FIFO + #0111 + + + 1000 + 8 data word in transmit FIFO + #1000 + + + 1001 + 9 data word in transmit FIFO + #1001 + + + 1010 + 10 data word in transmit FIFO + #1010 + + + 1011 + 11 data word in transmit FIFO + #1011 + + + 1100 + 12 data word in transmit FIFO + #1100 + + + 1101 + 13 data word in transmit FIFO + #1101 + + + 1110 + 14 data word in transmit FIFO + #1110 + + + 1111 + 15 data word in transmit FIFO + #1111 + + + + + RFCNT1 + no description available + 28 + 4 + read-write + + + 0000 + 0 data word in receive FIFO + #0000 + + + 0001 + 1 data word in receive FIFO + #0001 + + + 0010 + 2 data word in receive FIFO + #0010 + + + 0011 + 3 data word in receive FIFO + #0011 + + + 0100 + 4 data word in receive FIFO + #0100 + + + 0101 + 5 data word in receive FIFO + #0101 + + + 0110 + 6 data word in receive FIFO + #0110 + + + 0111 + 7 data word in receive FIFO + #0111 + + + 1000 + 8 data word in receive FIFO + #1000 + + + 1001 + 9 data word in receive FIFO + #1001 + + + 1010 + 10 data word in receive FIFO + #1010 + + + 1011 + 11 data word in receive FIFO + #1011 + + + 1100 + 12 data word in receive FIFO + #1100 + + + 1101 + 13 data word in receive FIFO + #1101 + + + 1110 + 14 data word in receive FIFO + #1110 + + + 1111 + 15 data word in receive FIFO + #1111 + + + + + + + SACNT + SSI AC97 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + AC97EN + no description available + 0 + 1 + read-write + + + 0 + AC97 mode disabled. + #0 + + + 1 + SSI in AC97 mode. + #1 + + + + + FV + no description available + 1 + 1 + read-write + + + 0 + FIXED + #0 + + + 1 + VARIABLE + #1 + + + + + TIF + no description available + 2 + 1 + read-write + + + 0 + SATAG_REGISTER + #0 + + + 1 + RX_FIFO0 + #1 + + + + + RD + no description available + 3 + 1 + read-write + + + 0 + Next frame will not have a Read Command. + #0 + + + 1 + Next frame will have a Read Command. + #1 + + + + + WR + no description available + 4 + 1 + read-write + + + 0 + Next frame will not have a Write Command. + #0 + + + 1 + Next frame will have a Write Command. + #1 + + + + + FRDIV + no description available + 5 + 6 + read-write + + + RESERVED + no description available + 11 + 21 + read-only + + + + + SACADD + SSI AC97 Command Address Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + SACADD + no description available + 0 + 19 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + SACDAT + SSI AC97 Command Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACDAT + no description available + 0 + 20 + read-write + + + RESERVED + no description available + 20 + 12 + read-only + + + + + SATAG + SSI AC97 Tag Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + SATAG + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + STMSK + SSI Transmit Time Slot Mask Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + STMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data transmitted in this time slot). + #1 + + + + + + + SRMSK + SSI Receive Time Slot Mask Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + SRMSK + no description available + 0 + 32 + read-write + + + 0 + Valid Time Slot. + #0 + + + 1 + Time Slot masked (no data received in this time slot). + #1 + + + + + + + SACCST + SSI AC97 Channel Status Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + SACCST + no description available + 0 + 10 + read-only + + + 0 + Data channel disabled. + #0 + + + 1 + Data channel enabled. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCEN + SSI AC97 Channel Enable Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCEN + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Enables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + SACCDIS + SSI AC97 Channel Disable Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + SACCDIS + no description available + 0 + 10 + write-only + + + 0 + Write Has no effect. + #0 + + + 1 + Write Disables the corresponding data channel. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + ASRC + ASRC Registers + ASRC_ + 0x2034000 + + 0 + 0xCC + registers + + + + ASRCTR + ASRC Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASRCEN + no description available + 0 + 1 + read-write + + + ASREA + no description available + 1 + 1 + read-write + + + ASREB + no description available + 2 + 1 + read-write + + + ASREC + no description available + 3 + 1 + read-write + + + SRST + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 8 + read-only + + + IDRA + no description available + 13 + 1 + read-write + + + USRA + no description available + 14 + 1 + read-write + + + IDRB + no description available + 15 + 1 + read-write + + + USRB + no description available + 16 + 1 + read-write + + + IDRC + no description available + 17 + 1 + read-write + + + USRC + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + ATSA + no description available + 20 + 1 + read-write + + + ATSB + no description available + 21 + 1 + read-write + + + ATSC + no description available + 22 + 1 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIER + ASRC Interrupt Enable Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADIEA + no description available + 0 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + ADIEB + no description available + 1 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + ADIEC + no description available + 2 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + ADOEA + no description available + 3 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + ADOEB + no description available + 4 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + ADOEC + no description available + 5 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + AOLIE + no description available + 6 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + AFPWE + no description available + 7 + 1 + read-write + + + 1 + interrupt enabled + #1 + + + 0 + interrupt disabled + #0 + + + + + RESERVED + no description available + 8 + 16 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCNCR + ASRC Channel Number Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ANCA + no description available + 0 + 4 + read-write + + + 0000 + 0 channels in A (Pair A is disabled) + #0000 + + + 0001 + 1 channel in A + #0001 + + + 0010 + 2 channels in A + #0010 + + + 0011 + 3 channels in A + #0011 + + + 0100 + 4 channels in A + #0100 + + + 0101 + 5 channels in A + #0101 + + + 0110 + 6 channels in A + #0110 + + + 0111 + 7 channels in A + #0111 + + + 1000 + 8 channels in A + #1000 + + + 1001 + 9 channels in A + #1001 + + + 1010 + 10 channels in A + #1010 + + + + + ANCB + no description available + 4 + 4 + read-write + + + 0000 + 0 channels in B (Pair B is disabled) + #0000 + + + 0001 + 1 channel in B + #0001 + + + 0010 + 2 channels in B + #0010 + + + 0011 + 3 channels in B + #0011 + + + 0100 + 4 channels in B + #0100 + + + 0101 + 5 channels in B + #0101 + + + 0110 + 6 channels in B + #0110 + + + 0111 + 7 channels in B + #0111 + + + 1000 + 8 channels in B + #1000 + + + 1001 + 9 channels in B + #1001 + + + 1010 + 10 channels in B + #1010 + + + + + ANCC + no description available + 8 + 4 + read-write + + + 0000 + 0 channels in C (Pair C is disabled) + #0000 + + + 0001 + 1 channel in C + #0001 + + + 0010 + 2 channels in C + #0010 + + + 0011 + 3 channels in C + #0011 + + + 0100 + 4 channels in C + #0100 + + + 0101 + 5 channels in C + #0101 + + + 0110 + 6 channels in C + #0110 + + + 0111 + 7 channels in C + #0111 + + + 1000 + 8 channels in C + #1000 + + + 1001 + 9 channels in C + #1001 + + + 1010 + 10 channels in C + #1010 + + + + + RESERVED + no description available + 12 + 12 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCFG + ASRC Filter Configuration Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 6 + read-only + + + PREMODA + no description available + 6 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #00 + + + 01 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #10 + + + 11 + Select passthrough mode. In this case, POSTMODA[1-0] have no use. + #11 + + + + + POSTMODA + no description available + 8 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #00 + + + 01 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #10 + + + + + PREMODB + no description available + 10 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #00 + + + 01 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #10 + + + 11 + Select passthrough mode. In this case, POSTMODB[1-0] have no use. + #11 + + + + + POSTMODB + no description available + 12 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #00 + + + 01 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #10 + + + + + PREMODC + no description available + 14 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #00 + + + 01 + Select Direct-Connection as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate conversion requirements. + #10 + + + 11 + Select passthrough mode. In this case, POSTMODC[1-0] have no use. + #11 + + + + + POSTMODC + no description available + 16 + 2 + read-write + + + 00 + Select Upsampling-by-2 as defined in Signal Processing Flow. + #00 + + + 01 + Select Direct-Connection as defined in Signal Processing Flow. + #01 + + + 10 + Select Downsampling-by-2 as defined in Signal Processing Flow. + #10 + + + + + NDPRA + no description available + 18 + 1 + read-write + + + 0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + #0 + + + 1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + #1 + + + + + NDPRB + no description available + 19 + 1 + read-write + + + 0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + #0 + + + 1 + Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. + #1 + + + + + NDPRC + no description available + 20 + 1 + read-write + + + 0 + Use default parameters for RAM-stored parameters. Override any parameters already in RAM. + #0 + + + 1 + Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. + #1 + + + + + INIRQA + no description available + 21 + 1 + read-only + + + INIRQB + no description available + 22 + 1 + read-only + + + INIRQC + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCSR + ASRC Clock Source Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICSA + no description available + 0 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + AICSB + no description available + 4 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + AICSC + no description available + 8 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + AOCSA + no description available + 12 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + AOCSB + no description available + 16 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + AOCSC + no description available + 20 + 4 + read-write + + + 0000 + bit clock 0 + #0000 + + + 0001 + bit clock 1 + #0001 + + + 0010 + bit clock 2 + #0010 + + + 0011 + bit clock 3 + #0011 + + + 0100 + bit clock 4 + #0100 + + + 0101 + bit clock 5 + #0101 + + + 0110 + bit clock 6 + #0110 + + + 0111 + bit clock 7 + #0111 + + + 1000 + bit clock 8 + #1000 + + + 1001 + bit clock 9 + #1001 + + + 1010 + bit clock A + #1010 + + + 1011 + bit clock B + #1011 + + + 1100 + bit clock C + #1100 + + + 1101 + bit clock D + #1101 + + + 1111 + clock disabled, connected to zero + #1111 + + + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCDR1 + ASRC Clock Divider Register 1 + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPA + no description available + 0 + 3 + read-write + + + AICDA + no description available + 3 + 3 + read-write + + + AICPB + no description available + 6 + 3 + read-write + + + AICDB + no description available + 9 + 3 + read-write + + + AOCPA + no description available + 12 + 3 + read-write + + + AOCDA + no description available + 15 + 3 + read-write + + + AOCPB + no description available + 18 + 3 + read-write + + + AOCDB + no description available + 21 + 3 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCDR2 + ASRC Clock Divider Register 2 + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + AICPC + no description available + 0 + 3 + read-write + + + AICDC + no description available + 3 + 3 + read-write + + + AOCPC + no description available + 6 + 3 + read-write + + + AOCDC + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 12 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRSTR + ASRC Status Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + AIDEA + no description available + 0 + 1 + read-only + + + AIDEB + no description available + 1 + 1 + read-only + + + AIDEC + no description available + 2 + 1 + read-only + + + AODFA + no description available + 3 + 1 + read-only + + + AODFB + no description available + 4 + 1 + read-only + + + AODFC + no description available + 5 + 1 + read-only + + + AOLE + no description available + 6 + 1 + read-only + + + FPWT + no description available + 7 + 1 + read-only + + + AIDUA + no description available + 8 + 1 + read-only + + + AIDUB + no description available + 9 + 1 + read-only + + + AIDUC + no description available + 10 + 1 + read-only + + + AODOA + no description available + 11 + 1 + read-only + + + AODOB + no description available + 12 + 1 + read-only + + + AODOC + no description available + 13 + 1 + read-only + + + AIOLA + no description available + 14 + 1 + read-only + + + AIOLB + no description available + 15 + 1 + read-only + + + AIOLC + no description available + 16 + 1 + read-only + + + AOOLA + no description available + 17 + 1 + read-only + + + AOOLB + no description available + 18 + 1 + read-only + + + AOOLC + no description available + 19 + 1 + read-only + + + ATQOL + no description available + 20 + 1 + read-only + + + DSLCNT + no description available + 21 + 1 + read-only + + + RESERVED + no description available + 22 + 2 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + 5 + 0x4 + 1,2,3,4,5 + ASRPMn%s + ASRC Parameter Register n + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + PARAMETER_VALUE + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRTFR1 + ASRC ASRC Task Queue FIFO Register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 6 + read-only + + + TF_BASE + no description available + 6 + 7 + read-write + + + TF_FILL + no description available + 13 + 7 + read-only + + + RESERVED + no description available + 20 + 4 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRCCR + ASRC Channel Counter Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACIA + no description available + 0 + 4 + read-write + + + ACIB + no description available + 4 + 4 + read-write + + + ACIC + no description available + 8 + 4 + read-write + + + ACOA + no description available + 12 + 4 + read-write + + + ACOB + no description available + 16 + 4 + read-write + + + ACOC + no description available + 20 + 4 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + 3 + 0x8 + A,B,C + ASRDI%s + ASRC Data Input Register for Pair x + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 24 + write-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + 3 + 0x8 + A,B,C + ASRDO%s + ASRC Data Output Register for Pair x + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 24 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRHA + ASRC Ideal Ratio for Pair A-High Part + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 16 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRLA + ASRC Ideal Ratio for Pair A -Low Part + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOA + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRHB + ASRC Ideal Ratio for Pair B-High Part + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 16 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRLB + ASRC Ideal Ratio for Pair B-Low Part + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOB + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRHC + ASRC Ideal Ratio for Pair C-High Part + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 16 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRIDRLC + ASRC Ideal Ratio for Pair C-Low Part + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDRATIOC + no description available + 0 + 24 + read-write + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASR76K + ASRC 76kHz Period in terms of ASRC processing clock + 0x98 + 32 + read-write + 0xA47 + 0xFFFFFFFF + + + ASR76K + no description available + 0 + 17 + read-write + + + RESERVED + no description available + 17 + 7 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASR56K + ASRC 56kHz Period in terms of ASRC processing clock + 0x9C + 32 + read-write + 0xDF3 + 0xFFFFFFFF + + + ASR56K + no description available + 0 + 17 + read-write + + + RESERVED + no description available + 17 + 7 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRMCRA + ASRC Misc Control Register for Pair A + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDA + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 4 + read-only + + + RSYNOFA + no description available + 10 + 1 + read-write + + + RSYNIFA + no description available + 11 + 1 + read-write + + + OUTFIFO_THRESHOLDA + no description available + 12 + 6 + read-write + + + RESERVED + no description available + 18 + 2 + read-only + + + BYPASSPOLYA + no description available + 20 + 1 + read-write + + + 1 + Bypass polyphase filtering. + #1 + + + 0 + Don't bypass polyphase filtering. + #0 + + + + + BUFSTALLA + no description available + 21 + 1 + read-write + + + 1 + Stall Pair A conversion in case of near empty/full FIFO conditions. + #1 + + + 0 + Don't stall Pair A conversion even in case of near empty/full FIFO conditions. + #0 + + + + + EXTTHRSHA + no description available + 22 + 1 + read-write + + + 1 + Use external defined thresholds. + #1 + + + 0 + Use default thresholds. + #0 + + + + + ZEROBUFA + no description available + 23 + 1 + read-write + + + 1 + Don't zeroize the buffer + #1 + + + 0 + Zeroize the buffer + #0 + + + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRFSTA + ASRC FIFO Status Register for Pair A + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLA + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 4 + read-only + + + IAEA + no description available + 11 + 1 + read-only + + + OUTFIFO_FILLA + no description available + 12 + 7 + read-only + + + RESERVED + no description available + 19 + 4 + read-only + + + OAFA + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRMCRB + ASRC Misc Control Register for Pair B + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDB + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 4 + read-only + + + RSYNOFB + no description available + 10 + 1 + read-write + + + RSYNIFB + no description available + 11 + 1 + read-write + + + OUTFIFO_THRESHOLDB + no description available + 12 + 6 + read-write + + + RESERVED + no description available + 18 + 2 + read-only + + + BYPASSPOLYB + no description available + 20 + 1 + read-write + + + 1 + Bypass polyphase filtering. + #1 + + + 0 + Don't bypass polyphase filtering. + #0 + + + + + BUFSTALLB + no description available + 21 + 1 + read-write + + + 1 + Stall Pair B conversion in case of near empty/full FIFO conditions. + #1 + + + 0 + Don't stall Pair B conversion even in case of near empty/full FIFO conditions. + #0 + + + + + EXTTHRSHB + no description available + 22 + 1 + read-write + + + 1 + Use external defined thresholds. + #1 + + + 0 + Use default thresholds. + #0 + + + + + ZEROBUFB + no description available + 23 + 1 + read-write + + + 1 + Don't zeroize the buffer + #1 + + + 0 + Zeroize the buffer + #0 + + + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRFSTB + ASRC FIFO Status Register for Pair B + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLB + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 4 + read-only + + + IAEB + no description available + 11 + 1 + read-only + + + OUTFIFO_FILLB + no description available + 12 + 7 + read-only + + + RESERVED + no description available + 19 + 4 + read-only + + + OAFB + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRMCRC + ASRC Misc Control Register for Pair C + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INFIFO_THRESHOLDC + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 4 + read-only + + + RSYNOFC + no description available + 10 + 1 + read-write + + + RSYNIFC + no description available + 11 + 1 + read-write + + + OUTFIFO_THRESHOLDC + no description available + 12 + 6 + read-write + + + RESERVED + no description available + 18 + 2 + read-only + + + BYPASSPOLYC + no description available + 20 + 1 + read-write + + + 1 + Bypass polyphase filtering. + #1 + + + 0 + Don't bypass polyphase filtering. + #0 + + + + + BUFSTALLC + no description available + 21 + 1 + read-write + + + 1 + Stall Pair C conversion in case of near empty/full FIFO conditions. + #1 + + + 0 + Don't stall Pair C conversion even in case of near empty/full FIFO conditions. + #0 + + + + + EXTTHRSHC + no description available + 22 + 1 + read-write + + + 1 + Use external defined thresholds. + #1 + + + 0 + Use default thresholds. + #0 + + + + + ZEROBUFC + no description available + 23 + 1 + read-write + + + 1 + Don't zeroize the buffer + #1 + + + 0 + Zeroize the buffer + #0 + + + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + ASRFSTC + ASRC FIFO Status Register for Pair C + 0xB4 + 32 + read-only + 0 + 0xFFFFFFFF + + + INFIFO_FILLC + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 4 + read-only + + + IAEC + no description available + 11 + 1 + read-only + + + OUTFIFO_FILLC + no description available + 12 + 7 + read-only + + + RESERVED + no description available + 19 + 4 + read-only + + + OAFC + no description available + 23 + 1 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + 3 + 0x4 + A,B,C + ASRMCR1%s + ASRC Misc Control Register 1 for Pair X + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + OW16 + no description available + 0 + 1 + read-write + + + 1 + 16-bit output data + #1 + + + 0 + 24-bit output data. + #0 + + + + + OSGN + no description available + 1 + 1 + read-write + + + 1 + Sign extension. + #1 + + + 0 + No sign extension. + #0 + + + + + OMSB + no description available + 2 + 1 + read-write + + + 1 + MSB aligned. + #1 + + + 0 + LSB aligned. + #0 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + IMSB + no description available + 8 + 1 + read-write + + + 1 + MSB aligned. + #1 + + + 0 + LSB aligned. + #0 + + + + + IWD + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 12 + read-only + + + RESERVED + This is a 24-bit register the upper byte is unimplemented. + 24 + 8 + read-only + + + + + + + SPBA + Temperature Monitor + SPBA_ + 0x203C000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + PRR%s + Peripheral Rights Register + 0 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + RARA + no description available + 0 + 1 + read-write + + + 0 + PROHIBITED + #0 + + + 1 + ALLOWED + #1 + + + + + RARB + no description available + 1 + 1 + read-write + + + 0 + PROHIBITED + #0 + + + 1 + ALLOWED + #1 + + + + + RARC + no description available + 2 + 1 + read-write + + + 0 + PROHIBITED + #0 + + + 1 + ALLOWED + #1 + + + + + RESERVED + no description available + 3 + 13 + read-only + + + ROI + no description available + 16 + 2 + read-only + + + 00 + UNOWNED + #00 + + + 01 + MASTER_A + #01 + + + 10 + MASTER_B + #10 + + + 11 + MASTER_C + #11 + + + + + RESERVED + no description available + 18 + 12 + read-only + + + RMO + no description available + 30 + 2 + read-only + + + 00 + UNOWNED + #00 + + + 01 + Reserved. + #01 + + + 10 + ANOTHER_MASTER + #10 + + + 11 + REQUESTING_MASTER + #11 + + + + + + + + + VPU + vpu + VPU_ + 0x2040000 + + 0 + 0x24 + registers + + + + CodeRun + BIT Processor run start + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CodeRun + no description available + 0 + 1 + write-only + + + 0 + BIT Processor stop execution. + #0 + + + 1 + BIT Processor start execution. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CodeDown + BIT Boot Code Download Data register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CodeData + no description available + 0 + 16 + write-only + + + CodeAddr + no description available + 16 + 13 + write-only + + + RESERVED + no description available + 29 + 3 + read-only + + + + + HostIntReq + Host Interrupt Request to BIT + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IntReq + no description available + 0 + 1 + write-only + + + 0 + No host interrupt is requested. + #0 + + + 1 + The host processor request interrupt to the BIT processor. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + BitIntClear + BIT Interrupt Clear + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IntClear + no description available + 0 + 1 + write-only + + + 0 + No operation is issued. + #0 + + + 1 + Clear the BIT interrupt to the host. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + BitIntSts + BIT Interrupt Status + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + IntSts + no description available + 0 + 1 + read-only + + + 0 + No BIT interrupt is asserted. + #0 + + + 1 + The BIT interrupt is asserted to the host. It is cleared when the host processor write "1" to VPU_BitIntClear register. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + BitCurPc + BIT Current PC + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CurPc + no description available + 0 + 14 + read-only + + + RESERVED + no description available + 14 + 18 + read-only + + + + + BitCodecBusy + BIT CODEC Busy + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CodecBusy + no description available + 0 + 1 + read-only + + + RESERVED + no description available + 1 + 31 + read-only + + + + + + + PWM1 + PWM + PWM + PWM1_ + 0x2080000 + + 0 + 0x18 + registers + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + PWM disabled + #0 + + + 1 + PWM enabled + #1 + + + + + REPEAT + no description available + 1 + 2 + read-write + + + 00 + Use each sample once + #00 + + + 01 + Use each sample twice + #01 + + + 10 + Use each sample four times + #10 + + + 11 + Use each sample eight times + #11 + + + + + SWR + no description available + 3 + 1 + read-write + + + 0 + PWM is out of reset + #0 + + + 1 + PWM is undergoing reset + #1 + + + + + PRESCALER + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + CLKSRC + no description available + 16 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + ipg_clk + #01 + + + 10 + ipg_clk_highfreq + #10 + + + 11 + ipg_clk_32k + #11 + + + + + POUTC + no description available + 18 + 2 + read-write + + + 00 + Output pin is set at rollover and cleared at comparison + #00 + + + 01 + Output pin is cleared at rollover and set at comparison + #01 + + + 10 + PWM output is disconnected + #10 + + + 11 + PWM output is disconnected + #11 + + + + + HCTR + no description available + 20 + 1 + read-write + + + 0 + Half word swapping does not take place + #0 + + + 1 + Half words from write data bus are swapped + #1 + + + + + BCTR + no description available + 21 + 1 + read-write + + + 0 + byte ordering remains the same + #0 + + + 1 + byte ordering is reversed + #1 + + + + + DBGEN + no description available + 22 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 23 + 1 + read-write + + + 0 + Inactive in wait mode + #0 + + + 1 + Active in wait mode + #1 + + + + + DOZEN + no description available + 24 + 1 + read-write + + + 0 + Inactive in doze mode + #0 + + + 1 + Active in doze mode + #1 + + + + + STOPEN + no description available + 25 + 1 + read-write + + + 0 + Inactive in stop mode + #0 + + + 1 + Active in stop mode + #1 + + + + + FWM + no description available + 26 + 2 + read-write + + + 00 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + #00 + + + 01 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + #01 + + + 10 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + #10 + + + 11 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + #11 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + no description available + 0 + 3 + read-only + + + 000 + No data available + #000 + + + 001 + 1 word of data in FIFO + #001 + + + 010 + 2 words of data in FIFO + #010 + + + 011 + 3 words of data in FIFO + #011 + + + 100 + 4 words of data in FIFO + #100 + + + 101 + unused + #101 + + + 110 + unused + #110 + + + 111 + unused + #111 + + + + + FE + no description available + 3 + 1 + read-write + + + 0 + Data level is above water mark + #0 + + + 1 + When the data level falls below the mark set by FWM field + #1 + + + + + ROV + no description available + 4 + 1 + read-write + + + 0 + Roll-over event not occurred + #0 + + + 1 + Roll-over event occurred + #1 + + + + + CMP + no description available + 5 + 1 + read-write + + + 0 + Compare event not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + FWE + no description available + 6 + 1 + read-write + + + 0 + FIFO write error not occurred + #0 + + + 1 + FIFO write error occurred + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + no description available + 0 + 1 + read-write + + + 0 + FIFO Empty interrupt disabled + #0 + + + 1 + FIFO Empty interrupt enabled + #1 + + + + + RIE + no description available + 1 + 1 + read-write + + + 0 + Roll-over interrupt not enabled + #0 + + + 1 + Roll-over Interrupt enabled + #1 + + + + + CIE + no description available + 2 + 1 + read-write + + + 0 + Compare Interrupt not enabled + #0 + + + 1 + Compare Interrupt enabled + #1 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + PWM2 + PWM + PWM + PWM2_ + 0x2084000 + + 0 + 0x18 + registers + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + PWM disabled + #0 + + + 1 + PWM enabled + #1 + + + + + REPEAT + no description available + 1 + 2 + read-write + + + 00 + Use each sample once + #00 + + + 01 + Use each sample twice + #01 + + + 10 + Use each sample four times + #10 + + + 11 + Use each sample eight times + #11 + + + + + SWR + no description available + 3 + 1 + read-write + + + 0 + PWM is out of reset + #0 + + + 1 + PWM is undergoing reset + #1 + + + + + PRESCALER + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + CLKSRC + no description available + 16 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + ipg_clk + #01 + + + 10 + ipg_clk_highfreq + #10 + + + 11 + ipg_clk_32k + #11 + + + + + POUTC + no description available + 18 + 2 + read-write + + + 00 + Output pin is set at rollover and cleared at comparison + #00 + + + 01 + Output pin is cleared at rollover and set at comparison + #01 + + + 10 + PWM output is disconnected + #10 + + + 11 + PWM output is disconnected + #11 + + + + + HCTR + no description available + 20 + 1 + read-write + + + 0 + Half word swapping does not take place + #0 + + + 1 + Half words from write data bus are swapped + #1 + + + + + BCTR + no description available + 21 + 1 + read-write + + + 0 + byte ordering remains the same + #0 + + + 1 + byte ordering is reversed + #1 + + + + + DBGEN + no description available + 22 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 23 + 1 + read-write + + + 0 + Inactive in wait mode + #0 + + + 1 + Active in wait mode + #1 + + + + + DOZEN + no description available + 24 + 1 + read-write + + + 0 + Inactive in doze mode + #0 + + + 1 + Active in doze mode + #1 + + + + + STOPEN + no description available + 25 + 1 + read-write + + + 0 + Inactive in stop mode + #0 + + + 1 + Active in stop mode + #1 + + + + + FWM + no description available + 26 + 2 + read-write + + + 00 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + #00 + + + 01 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + #01 + + + 10 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + #10 + + + 11 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + #11 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + no description available + 0 + 3 + read-only + + + 000 + No data available + #000 + + + 001 + 1 word of data in FIFO + #001 + + + 010 + 2 words of data in FIFO + #010 + + + 011 + 3 words of data in FIFO + #011 + + + 100 + 4 words of data in FIFO + #100 + + + 101 + unused + #101 + + + 110 + unused + #110 + + + 111 + unused + #111 + + + + + FE + no description available + 3 + 1 + read-write + + + 0 + Data level is above water mark + #0 + + + 1 + When the data level falls below the mark set by FWM field + #1 + + + + + ROV + no description available + 4 + 1 + read-write + + + 0 + Roll-over event not occurred + #0 + + + 1 + Roll-over event occurred + #1 + + + + + CMP + no description available + 5 + 1 + read-write + + + 0 + Compare event not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + FWE + no description available + 6 + 1 + read-write + + + 0 + FIFO write error not occurred + #0 + + + 1 + FIFO write error occurred + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + no description available + 0 + 1 + read-write + + + 0 + FIFO Empty interrupt disabled + #0 + + + 1 + FIFO Empty interrupt enabled + #1 + + + + + RIE + no description available + 1 + 1 + read-write + + + 0 + Roll-over interrupt not enabled + #0 + + + 1 + Roll-over Interrupt enabled + #1 + + + + + CIE + no description available + 2 + 1 + read-write + + + 0 + Compare Interrupt not enabled + #0 + + + 1 + Compare Interrupt enabled + #1 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + PWM3 + PWM + PWM + PWM3_ + 0x2088000 + + 0 + 0x18 + registers + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + PWM disabled + #0 + + + 1 + PWM enabled + #1 + + + + + REPEAT + no description available + 1 + 2 + read-write + + + 00 + Use each sample once + #00 + + + 01 + Use each sample twice + #01 + + + 10 + Use each sample four times + #10 + + + 11 + Use each sample eight times + #11 + + + + + SWR + no description available + 3 + 1 + read-write + + + 0 + PWM is out of reset + #0 + + + 1 + PWM is undergoing reset + #1 + + + + + PRESCALER + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + CLKSRC + no description available + 16 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + ipg_clk + #01 + + + 10 + ipg_clk_highfreq + #10 + + + 11 + ipg_clk_32k + #11 + + + + + POUTC + no description available + 18 + 2 + read-write + + + 00 + Output pin is set at rollover and cleared at comparison + #00 + + + 01 + Output pin is cleared at rollover and set at comparison + #01 + + + 10 + PWM output is disconnected + #10 + + + 11 + PWM output is disconnected + #11 + + + + + HCTR + no description available + 20 + 1 + read-write + + + 0 + Half word swapping does not take place + #0 + + + 1 + Half words from write data bus are swapped + #1 + + + + + BCTR + no description available + 21 + 1 + read-write + + + 0 + byte ordering remains the same + #0 + + + 1 + byte ordering is reversed + #1 + + + + + DBGEN + no description available + 22 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 23 + 1 + read-write + + + 0 + Inactive in wait mode + #0 + + + 1 + Active in wait mode + #1 + + + + + DOZEN + no description available + 24 + 1 + read-write + + + 0 + Inactive in doze mode + #0 + + + 1 + Active in doze mode + #1 + + + + + STOPEN + no description available + 25 + 1 + read-write + + + 0 + Inactive in stop mode + #0 + + + 1 + Active in stop mode + #1 + + + + + FWM + no description available + 26 + 2 + read-write + + + 00 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + #00 + + + 01 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + #01 + + + 10 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + #10 + + + 11 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + #11 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + no description available + 0 + 3 + read-only + + + 000 + No data available + #000 + + + 001 + 1 word of data in FIFO + #001 + + + 010 + 2 words of data in FIFO + #010 + + + 011 + 3 words of data in FIFO + #011 + + + 100 + 4 words of data in FIFO + #100 + + + 101 + unused + #101 + + + 110 + unused + #110 + + + 111 + unused + #111 + + + + + FE + no description available + 3 + 1 + read-write + + + 0 + Data level is above water mark + #0 + + + 1 + When the data level falls below the mark set by FWM field + #1 + + + + + ROV + no description available + 4 + 1 + read-write + + + 0 + Roll-over event not occurred + #0 + + + 1 + Roll-over event occurred + #1 + + + + + CMP + no description available + 5 + 1 + read-write + + + 0 + Compare event not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + FWE + no description available + 6 + 1 + read-write + + + 0 + FIFO write error not occurred + #0 + + + 1 + FIFO write error occurred + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + no description available + 0 + 1 + read-write + + + 0 + FIFO Empty interrupt disabled + #0 + + + 1 + FIFO Empty interrupt enabled + #1 + + + + + RIE + no description available + 1 + 1 + read-write + + + 0 + Roll-over interrupt not enabled + #0 + + + 1 + Roll-over Interrupt enabled + #1 + + + + + CIE + no description available + 2 + 1 + read-write + + + 0 + Compare Interrupt not enabled + #0 + + + 1 + Compare Interrupt enabled + #1 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + PWM4 + PWM + PWM + PWM4_ + 0x208C000 + + 0 + 0x18 + registers + + + + PWMCR + PWM Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + PWM disabled + #0 + + + 1 + PWM enabled + #1 + + + + + REPEAT + no description available + 1 + 2 + read-write + + + 00 + Use each sample once + #00 + + + 01 + Use each sample twice + #01 + + + 10 + Use each sample four times + #10 + + + 11 + Use each sample eight times + #11 + + + + + SWR + no description available + 3 + 1 + read-write + + + 0 + PWM is out of reset + #0 + + + 1 + PWM is undergoing reset + #1 + + + + + PRESCALER + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + CLKSRC + no description available + 16 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + ipg_clk + #01 + + + 10 + ipg_clk_highfreq + #10 + + + 11 + ipg_clk_32k + #11 + + + + + POUTC + no description available + 18 + 2 + read-write + + + 00 + Output pin is set at rollover and cleared at comparison + #00 + + + 01 + Output pin is cleared at rollover and set at comparison + #01 + + + 10 + PWM output is disconnected + #10 + + + 11 + PWM output is disconnected + #11 + + + + + HCTR + no description available + 20 + 1 + read-write + + + 0 + Half word swapping does not take place + #0 + + + 1 + Half words from write data bus are swapped + #1 + + + + + BCTR + no description available + 21 + 1 + read-write + + + 0 + byte ordering remains the same + #0 + + + 1 + byte ordering is reversed + #1 + + + + + DBGEN + no description available + 22 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 23 + 1 + read-write + + + 0 + Inactive in wait mode + #0 + + + 1 + Active in wait mode + #1 + + + + + DOZEN + no description available + 24 + 1 + read-write + + + 0 + Inactive in doze mode + #0 + + + 1 + Active in doze mode + #1 + + + + + STOPEN + no description available + 25 + 1 + read-write + + + 0 + Inactive in stop mode + #0 + + + 1 + Active in stop mode + #1 + + + + + FWM + no description available + 26 + 2 + read-write + + + 00 + FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO + #00 + + + 01 + FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO + #01 + + + 10 + FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO + #10 + + + 11 + FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO + #11 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + PWMSR + PWM Status Register + 0x4 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOAV + no description available + 0 + 3 + read-only + + + 000 + No data available + #000 + + + 001 + 1 word of data in FIFO + #001 + + + 010 + 2 words of data in FIFO + #010 + + + 011 + 3 words of data in FIFO + #011 + + + 100 + 4 words of data in FIFO + #100 + + + 101 + unused + #101 + + + 110 + unused + #110 + + + 111 + unused + #111 + + + + + FE + no description available + 3 + 1 + read-write + + + 0 + Data level is above water mark + #0 + + + 1 + When the data level falls below the mark set by FWM field + #1 + + + + + ROV + no description available + 4 + 1 + read-write + + + 0 + Roll-over event not occurred + #0 + + + 1 + Roll-over event occurred + #1 + + + + + CMP + no description available + 5 + 1 + read-write + + + 0 + Compare event not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + FWE + no description available + 6 + 1 + read-write + + + 0 + FIFO write error not occurred + #0 + + + 1 + FIFO write error occurred + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + PWMIR + PWM Interrupt Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIE + no description available + 0 + 1 + read-write + + + 0 + FIFO Empty interrupt disabled + #0 + + + 1 + FIFO Empty interrupt enabled + #1 + + + + + RIE + no description available + 1 + 1 + read-write + + + 0 + Roll-over interrupt not enabled + #0 + + + 1 + Roll-over Interrupt enabled + #1 + + + + + CIE + no description available + 2 + 1 + read-write + + + 0 + Compare Interrupt not enabled + #0 + + + 1 + Compare Interrupt enabled + #1 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + PWMSAR + PWM Sample Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SAMPLE + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMPR + PWM Period Register + 0x10 + 32 + read-write + 0xFFFE + 0xFFFFFFFF + + + PERIOD + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PWMCNR + PWM Counter Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 16 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + FLEXCAN1 + FLEXCAN + FLEXCAN + FLEXCAN1_ + 0x2090000 + + 0 + 0x9E4 + registers + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDAM + no description available + 8 + 2 + read-write + + + 00 + Format A One full ID (standard or extended) per ID filter Table element. + #00 + + + 01 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + #01 + + + 10 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + #10 + + + 11 + Format D All frames rejected. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + AEN + no description available + 12 + 1 + read-write + + + 1 + Abort enabled + #1 + + + 0 + Abort disabled + #0 + + + + + LPRIO_EN + no description available + 13 + 1 + read-write + + + 1 + Local Priority enabled + #1 + + + 0 + Local Priority disabled + #0 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + IRMQ + no description available + 16 + 1 + read-write + + + 1 + Individual Rx masking and queue feature are enabled. + #1 + + + 0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + #0 + + + + + SRX_DIS + no description available + 17 + 1 + read-write + + + 1 + Self reception disabled + #1 + + + 0 + Self reception enabled + #0 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + WAK_SRC + no description available + 19 + 1 + read-write + + + 1 + FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + #1 + + + 0 + FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + #0 + + + + + LPM_ACK + no description available + 20 + 1 + read-only + + + 1 + FLEXCAN is either in Disable Mode, or Stop mode + #1 + + + 0 + FLEXCAN not in any of the low power modes + #0 + + + + + WRN_EN + no description available + 21 + 1 + read-write + + + 1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + #1 + + + 0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + #0 + + + + + SLF_WAK + no description available + 22 + 1 + read-write + + + 1 + FLEXCAN Self Wake Up feature is enabled + #1 + + + 0 + FLEXCAN Self Wake Up feature is disabled + #0 + + + + + SUPV + no description available + 23 + 1 + read-write + + + 1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + #1 + + + 0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + #0 + + + + + FRZ_ACK + no description available + 24 + 1 + read-only + + + 1 + FLEXCAN in Freeze Mode, prescaler stopped + #1 + + + 0 + FLEXCAN not in Freeze Mode, prescaler running + #0 + + + + + SOFT_RST + no description available + 25 + 1 + read-write + + + 1 + Reset the registers + #1 + + + 0 + No reset request + #0 + + + + + WAK_MSK + no description available + 26 + 1 + read-write + + + 1 + Wake Up Interrupt is enabled + #1 + + + 0 + Wake Up Interrupt is disabled + #0 + + + + + NOT_RDY + no description available + 27 + 1 + read-only + + + 1 + FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + #1 + + + 0 + FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + #0 + + + + + HALT + no description available + 28 + 1 + read-write + + + 1 + Enters Freeze Mode if the FRZ bit is asserted. + #1 + + + 0 + No Freeze Mode request. + #0 + + + + + RFEN + no description available + 29 + 1 + read-write + + + 1 + FIFO enabled + #1 + + + 0 + FIFO not enabled + #0 + + + + + FRZ + no description available + 30 + 1 + read-write + + + 1 + Enabled to enter Freeze Mode + #1 + + + 0 + Not enabled to enter Freeze Mode + #0 + + + + + MDIS + no description available + 31 + 1 + read-write + + + 1 + Disable the FLEXCAN module + #1 + + + 0 + Enable the FLEXCAN module + #0 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROP_SEG + no description available + 0 + 3 + read-write + + + LOM + no description available + 3 + 1 + read-write + + + 1 + FLEXCAN module operates in Listen Only Mode + #1 + + + 0 + Listen Only Mode is deactivated + #0 + + + + + LBUF + no description available + 4 + 1 + read-write + + + 1 + Lowest number buffer is transmitted first + #1 + + + 0 + Buffer with highest priority is transmitted first + #0 + + + + + TSYN + no description available + 5 + 1 + read-write + + + 1 + Timer Sync feature enabled + #1 + + + 0 + Timer Sync feature disabled + #0 + + + + + BOFF_REC + no description available + 6 + 1 + read-write + + + 1 + Automatic recovering from Bus Off state disabled + #1 + + + 0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + #0 + + + + + SMP + no description available + 7 + 1 + read-write + + + 1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + #1 + + + 0 + Just one sample is used to determine the bit value + #0 + + + + + RESERVED + no description available + 8 + 2 + read-only + + + RWRN_MSK + no description available + 10 + 1 + read-write + + + 1 + Rx Warning Interrupt enabled + #1 + + + 0 + Rx Warning Interrupt disabled + #0 + + + + + TWRN_MSK + no description available + 11 + 1 + read-write + + + 1 + Tx Warning Interrupt enabled + #1 + + + 0 + Tx Warning Interrupt disabled + #0 + + + + + LPB + no description available + 12 + 1 + read-write + + + 1 + Loop Back enabled + #1 + + + 0 + Loop Back disabled + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + ERR_MSK + no description available + 14 + 1 + read-write + + + 1 + Error interrupt enabled + #1 + + + 0 + Error interrupt disabled + #0 + + + + + BOFF_MSK + no description available + 15 + 1 + read-write + + + 1 + Bus Off interrupt enabled + #1 + + + 0 + Bus Off interrupt disabled + #0 + + + + + PSEG2 + no description available + 16 + 3 + read-write + + + PSEG1 + no description available + 19 + 3 + read-write + + + RJW + no description available + 22 + 2 + read-write + + + PRESDIV + no description available + 24 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG31_MG0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked against the one received + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M31_RX14M0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M31_RX15M0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + Tx_Err_Counter + no description available + 0 + 8 + read-write + + + Rx_Err_Counter + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAK_INT + no description available + 0 + 1 + read-write + + + 1 + Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + #1 + + + 0 + No such occurrence + #0 + + + + + ERR_INT + no description available + 1 + 1 + read-write + + + 1 + Indicates setting of any Error Bit in the Error and Status Register + #1 + + + 0 + No such occurrence + #0 + + + + + BOFF_INT + no description available + 2 + 1 + read-write + + + 1 + FLEXCAN module entered 'Bus Off' state + #1 + + + 0 + No such occurrence + #0 + + + + + RX + no description available + 3 + 1 + read-only + + + 1 + FLEXCAN is transmitting a message + #1 + + + 0 + FLEXCAN is receiving a message + #0 + + + + + FLT_CONF + no description available + 4 + 2 + read-only + + + 00 + Error Active + #00 + + + 01 + Error Passive + #01 + + + 1x + Bus off + #1x + + + + + TX + no description available + 6 + 1 + read-only + + + 1 + FLEXCAN is transmitting a message + #1 + + + 0 + FLEXCAN is receiving a message + #0 + + + + + IDLE + no description available + 7 + 1 + read-only + + + 1 + CAN bus is now IDLE + #1 + + + 0 + No such occurrence + #0 + + + + + RX_WRN + no description available + 8 + 1 + read-only + + + 1 + Rx_Err_Counter >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + TX_WRN + no description available + 9 + 1 + read-only + + + 1 + TX_Err_Counter >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + STF_ERR + no description available + 10 + 1 + read-only + + + 1 + A Stuffing Error occurred since last read of this register. + #1 + + + 0 + No such occurrence. + #0 + + + + + FRM_ERR + no description available + 11 + 1 + read-only + + + 1 + A Form Error occurred since last read of this register + #1 + + + 0 + No such occurrence + #0 + + + + + CRC_ERR + no description available + 12 + 1 + read-only + + + 1 + A CRC error occurred since last read of this register. + #1 + + + 0 + No such occurrence + #0 + + + + + ACK_ERR + no description available + 13 + 1 + read-only + + + 1 + An ACK error occurred since last read of this register + #1 + + + 0 + No such occurrence + #0 + + + + + BIT0_ERR + no description available + 14 + 1 + read-only + + + 1 + At least one bit sent as dominant is received as recessive + #1 + + + 0 + No such occurrence + #0 + + + + + BIT1_ERR + no description available + 15 + 1 + read-only + + + 1 + At least one bit sent as recessive is received as dominant + #1 + + + 0 + No such occurrence + #0 + + + + + RWRN_INT + no description available + 16 + 1 + read-write + + + 1 + The Rx error counter transition from < 96 to >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + TWRN_INT + no description available + 17 + 1 + read-write + + + 1 + The Tx error counter transition from < 96 to >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + SYNCH + no description available + 18 + 1 + read-only + + + 1 + FlexCAN is synchronized to the CAN bus + #1 + + + 0 + FlexCAN is not synchronized to the CAN bus + #0 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63M_BUF32M + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer Interrupt is enabled + #1 + + + 0 + The corresponding buffer Interrupt is disabled + #0 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF31M_BUF0M + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer Interrupt is enabled + #1 + + + 0 + The corresponding buffer Interrupt is disabled + #0 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63I_BUF32I + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer has successfully completed transmission or reception + #1 + + + 0 + No such occurrence + #0 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4I_BUF0I + no description available + 0 + 5 + read-write + + + 1 + Corresponding MB completed transmission/reception + #1 + + + 0 + No such occurrence + #0 + + + + + BUF5I + no description available + 5 + 1 + read-write + + + 1 + MB5 completed transmission/reception or frames available in the FIFO + #1 + + + 0 + No such occurrence + #0 + + + + + BUF6I + no description available + 6 + 1 + read-write + + + 1 + MB6 completed transmission/reception or FIFO almost full + #1 + + + 0 + No such occurrence + #0 + + + + + BUF7I + no description available + 7 + 1 + read-write + + + 1 + MB7 completed transmission/reception or FIFO overflow + #1 + + + 0 + No such occurrence + #0 + + + + + BUF31I_BUF8I + no description available + 8 + 24 + read-write + + + 1 + The corresponding MB has successfully completed transmission or reception + #1 + + + 0 + No such occurrence + #0 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + EACEN + no description available + 16 + 1 + read-write + + + 1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + #1 + + + 0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + #0 + + + + + RRS + no description available + 17 + 1 + read-write + + + 1 + Remote Request Frame is stored + #1 + + + 0 + Remote Response Frame is generated + #0 + + + + + MRP + no description available + 18 + 1 + read-write + + + 1 + Matching starts from Mailboxes and continues on Rx FIFO + #1 + + + 0 + Matching starts from Rx FIFO and continues on Mailboxes + #0 + + + + + TASD + no description available + 19 + 5 + read-write + + + RFEN + no description available + 24 + 4 + read-write + + + WRMFRZ + no description available + 28 + 1 + read-write + + + 1 + Enable unrestricted write access to FlexCAN memory + #1 + + + 0 + Keep the write access restricted in some regions of FlexCAN memory + #0 + + + + + RESERVED + no description available + 29 + 2 + read-only + + + RESERVED + no description available + 31 + 1 + write-only + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + IMB + no description available + 13 + 1 + read-only + + + 1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + #1 + + + 0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + #0 + + + + + VPS + no description available + 14 + 1 + read-only + + + 1 + Contents of IMB and LPTM are valid + #1 + + + 0 + Contents of IMB and LPTM are invalid + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + LPTM + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 9 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + no description available + 0 + 15 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + MBCRC + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 9 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM31_FGM0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + The corresponding bit in the filter is "don't care" + #0 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + no description available + 0 + 9 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + RXIMR0_RXIMR63 + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI31_MI0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + + + FLEXCAN2 + FLEXCAN + FLEXCAN + FLEXCAN2_ + 0x2094000 + + 0 + 0x9E4 + registers + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDAM + no description available + 8 + 2 + read-write + + + 00 + Format A One full ID (standard or extended) per ID filter Table element. + #00 + + + 01 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + #01 + + + 10 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + #10 + + + 11 + Format D All frames rejected. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + AEN + no description available + 12 + 1 + read-write + + + 1 + Abort enabled + #1 + + + 0 + Abort disabled + #0 + + + + + LPRIO_EN + no description available + 13 + 1 + read-write + + + 1 + Local Priority enabled + #1 + + + 0 + Local Priority disabled + #0 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + IRMQ + no description available + 16 + 1 + read-write + + + 1 + Individual Rx masking and queue feature are enabled. + #1 + + + 0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + #0 + + + + + SRX_DIS + no description available + 17 + 1 + read-write + + + 1 + Self reception disabled + #1 + + + 0 + Self reception enabled + #0 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + WAK_SRC + no description available + 19 + 1 + read-write + + + 1 + FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + #1 + + + 0 + FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + #0 + + + + + LPM_ACK + no description available + 20 + 1 + read-only + + + 1 + FLEXCAN is either in Disable Mode, or Stop mode + #1 + + + 0 + FLEXCAN not in any of the low power modes + #0 + + + + + WRN_EN + no description available + 21 + 1 + read-write + + + 1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + #1 + + + 0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + #0 + + + + + SLF_WAK + no description available + 22 + 1 + read-write + + + 1 + FLEXCAN Self Wake Up feature is enabled + #1 + + + 0 + FLEXCAN Self Wake Up feature is disabled + #0 + + + + + SUPV + no description available + 23 + 1 + read-write + + + 1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + #1 + + + 0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + #0 + + + + + FRZ_ACK + no description available + 24 + 1 + read-only + + + 1 + FLEXCAN in Freeze Mode, prescaler stopped + #1 + + + 0 + FLEXCAN not in Freeze Mode, prescaler running + #0 + + + + + SOFT_RST + no description available + 25 + 1 + read-write + + + 1 + Reset the registers + #1 + + + 0 + No reset request + #0 + + + + + WAK_MSK + no description available + 26 + 1 + read-write + + + 1 + Wake Up Interrupt is enabled + #1 + + + 0 + Wake Up Interrupt is disabled + #0 + + + + + NOT_RDY + no description available + 27 + 1 + read-only + + + 1 + FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + #1 + + + 0 + FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + #0 + + + + + HALT + no description available + 28 + 1 + read-write + + + 1 + Enters Freeze Mode if the FRZ bit is asserted. + #1 + + + 0 + No Freeze Mode request. + #0 + + + + + RFEN + no description available + 29 + 1 + read-write + + + 1 + FIFO enabled + #1 + + + 0 + FIFO not enabled + #0 + + + + + FRZ + no description available + 30 + 1 + read-write + + + 1 + Enabled to enter Freeze Mode + #1 + + + 0 + Not enabled to enter Freeze Mode + #0 + + + + + MDIS + no description available + 31 + 1 + read-write + + + 1 + Disable the FLEXCAN module + #1 + + + 0 + Enable the FLEXCAN module + #0 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROP_SEG + no description available + 0 + 3 + read-write + + + LOM + no description available + 3 + 1 + read-write + + + 1 + FLEXCAN module operates in Listen Only Mode + #1 + + + 0 + Listen Only Mode is deactivated + #0 + + + + + LBUF + no description available + 4 + 1 + read-write + + + 1 + Lowest number buffer is transmitted first + #1 + + + 0 + Buffer with highest priority is transmitted first + #0 + + + + + TSYN + no description available + 5 + 1 + read-write + + + 1 + Timer Sync feature enabled + #1 + + + 0 + Timer Sync feature disabled + #0 + + + + + BOFF_REC + no description available + 6 + 1 + read-write + + + 1 + Automatic recovering from Bus Off state disabled + #1 + + + 0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + #0 + + + + + SMP + no description available + 7 + 1 + read-write + + + 1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + #1 + + + 0 + Just one sample is used to determine the bit value + #0 + + + + + RESERVED + no description available + 8 + 2 + read-only + + + RWRN_MSK + no description available + 10 + 1 + read-write + + + 1 + Rx Warning Interrupt enabled + #1 + + + 0 + Rx Warning Interrupt disabled + #0 + + + + + TWRN_MSK + no description available + 11 + 1 + read-write + + + 1 + Tx Warning Interrupt enabled + #1 + + + 0 + Tx Warning Interrupt disabled + #0 + + + + + LPB + no description available + 12 + 1 + read-write + + + 1 + Loop Back enabled + #1 + + + 0 + Loop Back disabled + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + ERR_MSK + no description available + 14 + 1 + read-write + + + 1 + Error interrupt enabled + #1 + + + 0 + Error interrupt disabled + #0 + + + + + BOFF_MSK + no description available + 15 + 1 + read-write + + + 1 + Bus Off interrupt enabled + #1 + + + 0 + Bus Off interrupt disabled + #0 + + + + + PSEG2 + no description available + 16 + 3 + read-write + + + PSEG1 + no description available + 19 + 3 + read-write + + + RJW + no description available + 22 + 2 + read-write + + + PRESDIV + no description available + 24 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + no description available + 0 + 16 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG31_MG0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked against the one received + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M31_RX14M0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M31_RX15M0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + Tx_Err_Counter + no description available + 0 + 8 + read-write + + + Rx_Err_Counter + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAK_INT + no description available + 0 + 1 + read-write + + + 1 + Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + #1 + + + 0 + No such occurrence + #0 + + + + + ERR_INT + no description available + 1 + 1 + read-write + + + 1 + Indicates setting of any Error Bit in the Error and Status Register + #1 + + + 0 + No such occurrence + #0 + + + + + BOFF_INT + no description available + 2 + 1 + read-write + + + 1 + FLEXCAN module entered 'Bus Off' state + #1 + + + 0 + No such occurrence + #0 + + + + + RX + no description available + 3 + 1 + read-only + + + 1 + FLEXCAN is transmitting a message + #1 + + + 0 + FLEXCAN is receiving a message + #0 + + + + + FLT_CONF + no description available + 4 + 2 + read-only + + + 00 + Error Active + #00 + + + 01 + Error Passive + #01 + + + 1x + Bus off + #1x + + + + + TX + no description available + 6 + 1 + read-only + + + 1 + FLEXCAN is transmitting a message + #1 + + + 0 + FLEXCAN is receiving a message + #0 + + + + + IDLE + no description available + 7 + 1 + read-only + + + 1 + CAN bus is now IDLE + #1 + + + 0 + No such occurrence + #0 + + + + + RX_WRN + no description available + 8 + 1 + read-only + + + 1 + Rx_Err_Counter >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + TX_WRN + no description available + 9 + 1 + read-only + + + 1 + TX_Err_Counter >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + STF_ERR + no description available + 10 + 1 + read-only + + + 1 + A Stuffing Error occurred since last read of this register. + #1 + + + 0 + No such occurrence. + #0 + + + + + FRM_ERR + no description available + 11 + 1 + read-only + + + 1 + A Form Error occurred since last read of this register + #1 + + + 0 + No such occurrence + #0 + + + + + CRC_ERR + no description available + 12 + 1 + read-only + + + 1 + A CRC error occurred since last read of this register. + #1 + + + 0 + No such occurrence + #0 + + + + + ACK_ERR + no description available + 13 + 1 + read-only + + + 1 + An ACK error occurred since last read of this register + #1 + + + 0 + No such occurrence + #0 + + + + + BIT0_ERR + no description available + 14 + 1 + read-only + + + 1 + At least one bit sent as dominant is received as recessive + #1 + + + 0 + No such occurrence + #0 + + + + + BIT1_ERR + no description available + 15 + 1 + read-only + + + 1 + At least one bit sent as recessive is received as dominant + #1 + + + 0 + No such occurrence + #0 + + + + + RWRN_INT + no description available + 16 + 1 + read-write + + + 1 + The Rx error counter transition from < 96 to >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + TWRN_INT + no description available + 17 + 1 + read-write + + + 1 + The Tx error counter transition from < 96 to >= 96 + #1 + + + 0 + No such occurrence + #0 + + + + + SYNCH + no description available + 18 + 1 + read-only + + + 1 + FlexCAN is synchronized to the CAN bus + #1 + + + 0 + FlexCAN is not synchronized to the CAN bus + #0 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63M_BUF32M + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer Interrupt is enabled + #1 + + + 0 + The corresponding buffer Interrupt is disabled + #0 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF31M_BUF0M + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer Interrupt is enabled + #1 + + + 0 + The corresponding buffer Interrupt is disabled + #0 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63I_BUF32I + no description available + 0 + 32 + read-write + + + 1 + The corresponding buffer has successfully completed transmission or reception + #1 + + + 0 + No such occurrence + #0 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4I_BUF0I + no description available + 0 + 5 + read-write + + + 1 + Corresponding MB completed transmission/reception + #1 + + + 0 + No such occurrence + #0 + + + + + BUF5I + no description available + 5 + 1 + read-write + + + 1 + MB5 completed transmission/reception or frames available in the FIFO + #1 + + + 0 + No such occurrence + #0 + + + + + BUF6I + no description available + 6 + 1 + read-write + + + 1 + MB6 completed transmission/reception or FIFO almost full + #1 + + + 0 + No such occurrence + #0 + + + + + BUF7I + no description available + 7 + 1 + read-write + + + 1 + MB7 completed transmission/reception or FIFO overflow + #1 + + + 0 + No such occurrence + #0 + + + + + BUF31I_BUF8I + no description available + 8 + 24 + read-write + + + 1 + The corresponding MB has successfully completed transmission or reception + #1 + + + 0 + No such occurrence + #0 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + EACEN + no description available + 16 + 1 + read-write + + + 1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + #1 + + + 0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + #0 + + + + + RRS + no description available + 17 + 1 + read-write + + + 1 + Remote Request Frame is stored + #1 + + + 0 + Remote Response Frame is generated + #0 + + + + + MRP + no description available + 18 + 1 + read-write + + + 1 + Matching starts from Mailboxes and continues on Rx FIFO + #1 + + + 0 + Matching starts from Rx FIFO and continues on Mailboxes + #0 + + + + + TASD + no description available + 19 + 5 + read-write + + + RFEN + no description available + 24 + 4 + read-write + + + WRMFRZ + no description available + 28 + 1 + read-write + + + 1 + Enable unrestricted write access to FlexCAN memory + #1 + + + 0 + Keep the write access restricted in some regions of FlexCAN memory + #0 + + + + + RESERVED + no description available + 29 + 2 + read-only + + + RESERVED + no description available + 31 + 1 + write-only + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + IMB + no description available + 13 + 1 + read-only + + + 1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + #1 + + + 0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + #0 + + + + + VPS + no description available + 14 + 1 + read-only + + + 1 + Contents of IMB and LPTM are valid + #1 + + + 0 + Contents of IMB and LPTM are invalid + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + LPTM + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 9 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + no description available + 0 + 15 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + MBCRC + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 9 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM31_FGM0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + The corresponding bit in the filter is "don't care" + #0 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + no description available + 0 + 9 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + RXIMR0_RXIMR63 + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI31_MI0 + no description available + 0 + 32 + read-write + + + 1 + The corresponding bit in the filter is checked + #1 + + + 0 + the corresponding bit in the filter is "don't care" + #0 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + + + GPT + GPT + GPT_ + 0x2098000 + + 0 + 0x28 + registers + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + GPT is disabled. + #0 + + + 1 + GPT is enabled. + #1 + + + + + ENMOD + no description available + 1 + 1 + read-write + + + 0 + GPT counter will retain its value when it is disabled. + #0 + + + 1 + GPT counter value is reset to 0 when it is disabled. + #1 + + + + + DBGEN + no description available + 2 + 1 + read-write + + + 0 + GPT is disabled in debug mode. + #0 + + + 1 + GPT is enabled in debug mode. + #1 + + + + + WAITEN + no description available + 3 + 1 + read-write + + + 0 + GPT is disabled in wait mode. + #0 + + + 1 + GPT is enabled in wait mode. + #1 + + + + + DOZEEN + no description available + 4 + 1 + read-write + + + 0 + GPT is disabled in doze mode. + #0 + + + 1 + GPT is enabled in doze mode. + #1 + + + + + STOPEN + no description available + 5 + 1 + read-write + + + 0 + GPT is disabled in Stop mode. + #0 + + + 1 + GPT is enabled in Stop mode. + #1 + + + + + CLKSRC + no description available + 6 + 3 + read-write + + + 000 + No clock + #000 + + + 001 + Peripheral Clock + #001 + + + 010 + High Frequency Reference Clock + #010 + + + 011 + External Clock (CLKIN) + #011 + + + 100 + Low Frequency Reference Clock + #100 + + + 101 + Crystal oscillator as Reference Clock + #101 + + + + + FRR + no description available + 9 + 1 + read-write + + + 0 + Restart mode + #0 + + + 1 + Free-Run mode + #1 + + + + + 24MEN + no description available + 10 + 1 + read-write + + + 0 + 24M clock disabled + #0 + + + 1 + 24M clock enabled + #1 + + + + + RESERVED + no description available + 11 + 4 + read-only + + + SWR + no description available + 15 + 1 + read-write + + + 0 + GPT is not in reset state + #0 + + + 1 + GPT is in reset state + #1 + + + + + IM1 + no description available + 16 + 2 + read-write + + + IM2 + no description available + 18 + 2 + read-write + + + 00 + capture disabled + #00 + + + 01 + capture on rising edge only + #01 + + + 10 + capture on falling edge only + #10 + + + 11 + capture on both edges + #11 + + + + + OM1 + no description available + 20 + 3 + read-write + + + OM2 + no description available + 23 + 3 + read-write + + + OM3 + no description available + 26 + 3 + read-write + + + 000 + Output disconnected. No response on pin. + #000 + + + 001 + Toggle output pin + #001 + + + 010 + Clear output pin + #010 + + + 011 + Set output pin + #011 + + + 1xx + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + no description available + 29 + 1 + write-only + + + FO2 + no description available + 30 + 1 + write-only + + + FO3 + no description available + 31 + 1 + write-only + + + 0 + Writing a 0 has no effect. + #0 + + + 1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + #1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + no description available + 0 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + PRESCALER24M + no description available + 12 + 4 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2 + #1 + + + 1111 + Divide by 16 + #1111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + no description available + 0 + 1 + read-write + + + OF2 + no description available + 1 + 1 + read-write + + + OF3 + no description available + 2 + 1 + read-write + + + 0 + Compare event has not occurred. + #0 + + + 1 + Compare event has occurred. + #1 + + + + + IF1 + no description available + 3 + 1 + read-write + + + IF2 + no description available + 4 + 1 + read-write + + + 0 + Capture event has not occurred. + #0 + + + 1 + Capture event has occurred. + #1 + + + + + ROV + no description available + 5 + 1 + read-write + + + 0 + Rollover has not occurred. + #0 + + + 1 + Rollover has occurred. + #1 + + + + + RESERVED + no description available + 6 + 26 + read-only + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + no description available + 0 + 1 + read-write + + + OF2IE + no description available + 1 + 1 + read-write + + + OF3IE + no description available + 2 + 1 + read-write + + + 0 + Output Compare Channel n interrupt is disabled. + #0 + + + 1 + Output Compare Channel n interrupt is enabled. + #1 + + + + + IF1IE + no description available + 3 + 1 + read-write + + + IF2IE + no description available + 4 + 1 + read-write + + + 0 + IF2IE Input Capture n Interrupt Enable is disabled. + #0 + + + 1 + IF2IE Input Capture n Interrupt Enable is enabled. + #1 + + + + + ROVIE + no description available + 5 + 1 + read-write + + + 0 + Rollover interrupt is disabled. + #0 + + + 1 + Rollover interrupt enabled. + #1 + + + + + RESERVED + no description available + 6 + 26 + read-only + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + no description available + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + no description available + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + no description available + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + no description available + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + no description available + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 32 + read-only + + + + + + + GPIO1 + GPIO + GPIO + GPIO1_ + 0x209C000 + + 0 + 0x20 + registers + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + no description available + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + no description available + 0 + 32 + read-write + + + 0 + INPUT + #0 + + + 1 + OUTPUT + #1 + + + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + no description available + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + no description available + 0 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR1 + no description available + 2 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR2 + no description available + 4 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR3 + no description available + 6 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR4 + no description available + 8 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR5 + no description available + 10 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR6 + no description available + 12 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR7 + no description available + 14 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR8 + no description available + 16 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR9 + no description available + 18 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR10 + no description available + 20 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR11 + no description available + 22 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR12 + no description available + 24 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR13 + no description available + 26 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR14 + no description available + 28 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR15 + no description available + 30 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + no description available + 0 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR17 + no description available + 2 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR18 + no description available + 4 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR19 + no description available + 6 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR20 + no description available + 8 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR21 + no description available + 10 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR22 + no description available + 12 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR23 + no description available + 14 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR24 + no description available + 16 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR25 + no description available + 18 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR26 + no description available + 20 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR27 + no description available + 22 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR28 + no description available + 24 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR29 + no description available + 26 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR30 + no description available + 28 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR31 + no description available + 30 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + no description available + 0 + 32 + read-write + + + 0 + UNMASKED + #0 + + + 1 + MASKED + #1 + + + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + no description available + 0 + 32 + read-write + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + no description available + 0 + 32 + read-write + + + + + + + GPIO2 + GPIO + GPIO + GPIO2_ + 0x20A0000 + + 0 + 0x20 + registers + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + no description available + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + no description available + 0 + 32 + read-write + + + 0 + INPUT + #0 + + + 1 + OUTPUT + #1 + + + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + no description available + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + no description available + 0 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR1 + no description available + 2 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR2 + no description available + 4 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR3 + no description available + 6 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR4 + no description available + 8 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR5 + no description available + 10 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR6 + no description available + 12 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR7 + no description available + 14 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR8 + no description available + 16 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR9 + no description available + 18 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR10 + no description available + 20 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR11 + no description available + 22 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR12 + no description available + 24 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR13 + no description available + 26 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR14 + no description available + 28 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR15 + no description available + 30 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + no description available + 0 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR17 + no description available + 2 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR18 + no description available + 4 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR19 + no description available + 6 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE + #11 + + + + + ICR20 + no description available + 8 + 2 + read-write + + + 00 + LOW_LEVEL + #00 + + + 01 + HIGH_LEVEL + #01 + + + 10 + RISING_EDGE + #10 + + + 11 + FALLING_EDGE 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+ read-write + + + 0 + No key release detected + #0 + + + 1 + All keys have been released + #1 + + + + + KDSC + no description available + 2 + 1 + write-only + + + 0 + No effect + #0 + + + 1 + Set bits that clear the keypad depress synchronizer chain + #1 + + + + + KRSS + no description available + 3 + 1 + write-only + + + 0 + No effect + #0 + + + 1 + Set bits which sets keypad release synchronizer chain + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + KDIE + no description available + 8 + 1 + read-write + + + 0 + No interrupt request is generated when KPKD is set. + #0 + + + 1 + An interrupt request is generated when KPKD is set. + #1 + + + + + KRIE + no description available + 9 + 1 + read-write + + + 0 + No interrupt request is generated when KPKR is set. + #0 + + + 1 + An interrupt request is generated when KPKR is set. + #1 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + no description available + 0 + 8 + read-write + + + 0 + INPUT + #0 + + + 1 + OUTPUT + #1 + + + + + KCDD + no description available + 8 + 8 + read-write + + + 0 + INPUT + #0 + + + 1 + OUTPUT + #1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + no description available + 0 + 8 + read-write + + + KCD + no description available + 8 + 8 + read-write + + + + + + + WDOG1 + WDOG + WDOG + WDOG1_ + 0x20BC000 + + 0 + 0xA + registers + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + no description available + 0 + 1 + read-write + + + 0 + Continue timer operation (Default). + #0 + + + 1 + Suspend the watchdog timer. + #1 + + + + + WDBG + no description available + 1 + 1 + read-write + + + 0 + Continue WDOG timer operation (Default). + #0 + + + 1 + Suspend the watchdog timer. + #1 + + + + + WDE + no description available + 2 + 1 + read-write + + + 0 + Disable the Watchdog (Default). + #0 + + + 1 + Enable the Watchdog. + #1 + + + + + WDT + no description available + 3 + 1 + read-write + + + 0 + No effect on WDOG_B (Default). + #0 + + + 1 + Assert WDOG_B upon a Watchdog Time-out event. + #1 + + + + + SRS + no description available + 4 + 1 + read-write + + + 0 + Assert system reset signal. + #0 + + + 1 + No effect on the system (Default). + #1 + + + + + WDA + no description available + 5 + 1 + read-write + + + 0 + Assert WDOG_B output. + #0 + + + 1 + No effect on system (Default). + #1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + 0 + using original way to generate software reset (default) + #0 + + + 1 + using new way to generate software reset. + #1 + + + + + WDW + no description available + 7 + 1 + read-write + + + 0 + Continue WDOG timer operation (Default). + #0 + + + 1 + Suspend WDOG timer operation. + #1 + + + + + WT + no description available + 8 + 8 + read-write + + + 0 + - 0.5 Seconds (Default). + #0 + + + 1 + - 1.0 Seconds. + #1 + + + 10 + - 1.5 Seconds. + #10 + + + 11 + - 2.0 Seconds. + #11 + + + 11111111 + - 128 Seconds. + #11111111 + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + no description available + 0 + 16 + read-write + + + 101010101010101 + Write to the Watchdog Service Register (WDOG_WSR). + #101010101010101 + + + 1010101010101010 + Write to the Watchdog Service Register (WDOG_WSR). + #1010101010101010 + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + no description available + 0 + 1 + read-only + + + 0 + Reset is not the result of a software reset. + #0 + + + 1 + Reset is the result of a software reset. + #1 + + + + + TOUT + no description available + 1 + 1 + read-only + + + 0 + Reset is not the result of a WDOG timeout. + #0 + + + 1 + Reset is the result of a WDOG timeout. + #1 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + POR + no description available + 4 + 1 + read-only + + + 0 + Reset is not the result of a power on reset. + #0 + + + 1 + Reset is the result of a power on reset. + #1 + + + + + RESERVED + no description available + 5 + 11 + read-only + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + no description available + 0 + 8 + read-write + + + 0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + #0 + + + 1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + #1 + + + 100 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + #100 + + + 11111111 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + #11111111 + + + + + RESERVED + no description available + 8 + 6 + read-only + + + WTIS + no description available + 14 + 1 + read-write + + + 0 + No interrupt has occurred (Default). + #0 + + + 1 + Interrupt has occurred + #1 + + + + + WIE + no description available + 15 + 1 + read-write + + + 0 + Disable Interrupt (Default). + #0 + + + 1 + Enable Interrupt. + #1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + no description available + 0 + 1 + read-write + + + 0 + Power Down Counter of WDOG is disabled. + #0 + + + 1 + Power Down Counter of WDOG is enabled (Default). + #1 + + + + + RESERVED + no description available + 1 + 15 + read-only + + + + + + + WDOG2 + WDOG + WDOG + WDOG2_ + 0x20C0000 + + 0 + 0xA + registers + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + no description available + 0 + 1 + read-write + + + 0 + Continue timer operation (Default). + #0 + + + 1 + Suspend the watchdog timer. + #1 + + + + + WDBG + no description available + 1 + 1 + read-write + + + 0 + Continue WDOG timer operation (Default). + #0 + + + 1 + Suspend the watchdog timer. + #1 + + + + + WDE + no description available + 2 + 1 + read-write + + + 0 + Disable the Watchdog (Default). + #0 + + + 1 + Enable the Watchdog. + #1 + + + + + WDT + no description available + 3 + 1 + read-write + + + 0 + No effect on WDOG_B (Default). + #0 + + + 1 + Assert WDOG_B upon a Watchdog Time-out event. + #1 + + + + + SRS + no description available + 4 + 1 + read-write + + + 0 + Assert system reset signal. + #0 + + + 1 + No effect on the system (Default). + #1 + + + + + WDA + no description available + 5 + 1 + read-write + + + 0 + Assert WDOG_B output. + #0 + + + 1 + No effect on system (Default). + #1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + 0 + using original way to generate software reset (default) + #0 + + + 1 + using new way to generate software reset. + #1 + + + + + WDW + no description available + 7 + 1 + read-write + + + 0 + Continue WDOG timer operation (Default). + #0 + + + 1 + Suspend WDOG timer operation. + #1 + + + + + WT + no description available + 8 + 8 + read-write + + + 0 + - 0.5 Seconds (Default). + #0 + + + 1 + - 1.0 Seconds. + #1 + + + 10 + - 1.5 Seconds. + #10 + + + 11 + - 2.0 Seconds. + #11 + + + 11111111 + - 128 Seconds. + #11111111 + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + no description available + 0 + 16 + read-write + + + 101010101010101 + Write to the Watchdog Service Register (WDOG_WSR). + #101010101010101 + + + 1010101010101010 + Write to the Watchdog Service Register (WDOG_WSR). + #1010101010101010 + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + no description available + 0 + 1 + read-only + + + 0 + Reset is not the result of a software reset. + #0 + + + 1 + Reset is the result of a software reset. + #1 + + + + + TOUT + no description available + 1 + 1 + read-only + + + 0 + Reset is not the result of a WDOG timeout. + #0 + + + 1 + Reset is the result of a WDOG timeout. + #1 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + POR + no description available + 4 + 1 + read-only + + + 0 + Reset is not the result of a power on reset. + #0 + + + 1 + Reset is the result of a power on reset. + #1 + + + + + RESERVED + no description available + 5 + 11 + read-only + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + no description available + 0 + 8 + read-write + + + 0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + #0 + + + 1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + #1 + + + 100 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + #100 + + + 11111111 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + #11111111 + + + + + RESERVED + no description available + 8 + 6 + read-only + + + WTIS + no description available + 14 + 1 + read-write + + + 0 + No interrupt has occurred (Default). + #0 + + + 1 + Interrupt has occurred + #1 + + + + + WIE + no description available + 15 + 1 + read-write + + + 0 + Disable Interrupt (Default). + #0 + + + 1 + Enable Interrupt. + #1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + no description available + 0 + 1 + read-write + + + 0 + Power Down Counter of WDOG is disabled. + #0 + + + 1 + Power Down Counter of WDOG is enabled (Default). + #1 + + + + + RESERVED + no description available + 1 + 15 + read-only + + + + + + + CCM + CCM + CCM_ + 0x20C4000 + + 0 + 0x8C + registers + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x40116FF + 0xFFFFFFFF + + + OSCNT + no description available + 0 + 8 + read-write + + + 00000000 + count 1 ckil + #00000000 + + + 11111111 + count 256 ckil's (default) + #11111111 + + + + + RESERVED + no description available + 8 + 4 + read-only + + + COSC_EN + no description available + 12 + 1 + read-write + + + 0 + disable on chip oscillator + #0 + + + 1 + enable on chip oscillator + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + WB_COUNT + no description available + 16 + 3 + read-write + + + 000 + no delay + #000 + + + 001 + 1 CKIL clock delay + #001 + + + 111 + 7 CKIL clocks delay + #111 + + + + + RESERVED + no description available + 19 + 2 + read-only + + + REG_BYPASS_COUNT + no description available + 21 + 6 + read-write + + + 000000 + no delay + #000000 + + + 000001 + 1 CKIL clock period delay + #000001 + + + 111111 + 63 CKIL clock periods delay + #111111 + + + + + RBC_EN + no description available + 27 + 1 + read-write + + + 1 + REG_BYPASS_COUNTER enabled. + #1 + + + 0 + REG_BYPASS_COUNTER disabled + #0 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CCDR + CCM Control Divider Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + mmdc_ch1_mask + no description available + 16 + 1 + read-write + + + 0 + allow handshake with mmdc_ch1 module + #0 + + + 1 + mask handshake with mmdc_ch1. Request signal will not be generated. + #1 + + + + + mmdc_ch0_mask + no description available + 17 + 1 + read-write + + + 0 + allow handshake with mmdc_ch0 module + #0 + + + 1 + mask handshake with mmdc_ch0. Request signal will not be generated. + #1 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + no description available + 0 + 1 + read-only + + + 0 + value of CCM_REF_EN_B is '0' + #0 + + + 1 + value of CCM_REF_EN_B is '1' + #1 + + + + + RESERVED + no description available + 1 + 3 + read-only + + + RESERVED + no description available + 4 + 1 + read-only + + + cosc_ready + no description available + 5 + 1 + read-only + + + 0 + on board oscillator is not ready. + #0 + + + 1 + on board oscillator is ready. + #1 + + + + + RESERVED + no description available + 6 + 26 + read-only + + + + + CCSR + CCM Clock Swither Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + pll3_sw_clk_sel + no description available + 0 + 1 + read-write + + + 0 + pll3_main_clk(default) + #0 + + + 1 + pll3 bypass clock + #1 + + + + + pll2_sw_clk_sel + no description available + 1 + 1 + read-write + + + 0 + pll2_main_clk(default) + #0 + + + 1 + pll2 bypass clock + #1 + + + + + pll1_sw_clk_sel + no description available + 2 + 1 + read-write + + + 0 + pll1_main_clk(default) + #0 + + + 1 + step_clk + #1 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + step_sel + no description available + 8 + 1 + read-write + + + 0 + osc_clk (24M) - source for lp_apm. (default) + #0 + + + 1 + pll2 PFD clock + #1 + + + + + pfd_396m_dis_mask + no description available + 9 + 1 + read-write + + + 0 + 396M PFD disable=0 (PFD always on) + #0 + + + 1 + 396M PFD disable is managed by associated dividers disable. If all 396M-driven dividers are closed, PFD is disabled. + #1 + + + + + pfd_307m_dis_mask + no description available + 10 + 1 + read-write + + + 0 + 307M PFD disable=0 (PFD always on) + #0 + + + 1 + 307M PFD disable is managed by associated dividers disable. If all 307M-driven dividers are closed, PFD is disabled. + #1 + + + + + pfd_528m_dis_mask + no description available + 11 + 1 + read-write + + + 0 + 528M PFD disable=0 (PFD always on) + #0 + + + 1 + 528M PFD disable is managed by associated dividers disable. If all 528M-driven dividers are closed, PFD is disabled. + #1 + + + + + pfd_508m_dis_mask + no description available + 12 + 1 + read-write + + + 0 + 508M PFD disable=0 (PFD always on) + #0 + + + 1 + 508M PFD disable is managed by associated dividers disable. If all 508M-driven dividers are closed, PFD is disabled. + #1 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + RESERVED + no description available + 14 + 1 + read-only + + + pfd_540m_dis_mask + no description available + 15 + 1 + read-write + + + 0 + - 540M PFD disable=0 (PFD always on) + #0 + + + 1 + 540M PFD disable is managed by associated dividers disable. If all 540M-driven dividers are closed, PFD is disabled. + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + arm_podf + no description available + 0 + 3 + read-write + + + 000 + divide by 1(default) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0x18D00 + 0xFFFFFFFF + + + periph2_clk2_podf + no description available + 0 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + mmdc_ch1_axi_podf + no description available + 3 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + axi_sel + no description available + 6 + 1 + read-write + + + 0 + Periph_clk output will be used as AXI clock root + #0 + + + 1 + AXI alternative clock will be used as AXI clock root + #1 + + + + + axi_alt_sel + no description available + 7 + 1 + read-write + + + 0 + pll2 396MHz PFD will be selected as alternative clock for AXI root clock + #0 + + + 1 + pll3 540MHz PFD will be selected as alternative clock for AXI root clock + #1 + + + + + ipg_podf + no description available + 8 + 2 + read-write + + + 00 + divide by 1 + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 3 + #10 + + + 11 + divide by 4 + #11 + + + + + ahb_podf + no description available + 10 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + axi_podf + no description available + 16 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + mmdc_ch0_axi_podf + no description available + 19 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 22 + 3 + read-only + + + periph_clk_sel + no description available + 25 + 1 + read-write + + + 0 + derive clock from pll2_sw_clk muxed clock source. + #0 + + + 1 + derive clock from periph_clk2_clk clock source. + #1 + + + + + periph2_clk_sel + no description available + 26 + 1 + read-write + + + 0 + derive clock from pll2_sw_clk muxed clock source. + #0 + + + 1 + derive clock from periph_clk2_clk clock source. + #1 + + + + + periph_clk2_podf + no description available + 27 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x820324 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + RESERVED + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + gpu3d_core_clk_sel + no description available + 4 + 2 + read-write + + + 00 + derive clock from mmdc_ch0 + #00 + + + 01 + derive clock from pll3 + #01 + + + 10 + derive clock from 528M PFD + #10 + + + 11 + derive clock from 396M PFD + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + gpu2d_core_sel + no description available + 8 + 2 + read-write + + + 00 + derive clock from mmdc_ch0 clk + #00 + + + 01 + derive clock from pll3 + #01 + + + 10 + derive clock from 528M PFD + #10 + + + 11 + derive clock from Reserved PFD + #11 + + + + + pcie_axi_clk_sel + no description available + 10 + 1 + read-write + + + 0 + derive clock from axi clk + #0 + + + 1 + derive clock from system_133M clk + #1 + + + + + vdoaxi_clk_sel + no description available + 11 + 1 + read-write + + + 0 + derive clock from axi clk + #0 + + + 1 + derive clock from 132M clock + #1 + + + + + periph_clk2_sel + no description available + 12 + 2 + read-write + + + 00 + derive clock from pll3_sw_clk + #00 + + + 01 + derive clock from pll1_ref_clk + #01 + + + 10 + derive clock from pll2_burn_in_clk + #10 + + + 11 + reserved + #11 + + + + + vpu_axi_clk_sel + no description available + 14 + 2 + read-write + + + 00 + derive clock from AXI + #00 + + + 01 + derive clock from 396M PFD + #01 + + + 10 + derive clock from 307M PFD + #10 + + + 11 + Restricted + #11 + + + + + mlb_sys_sel + no description available + 16 + 2 + read-write + + + 00 + derive clock from axi + #00 + + + 01 + derive clock from pll3 + #01 + + + 10 + 307M PFD + #10 + + + 11 + derive clock from 396M PFD + #11 + + + + + pre_periph_clk_sel + no description available + 18 + 2 + read-write + + + 00 + derive clock from PLL2 main 528MHz clock + #00 + + + 01 + derive clock from 396MHz PLL2 PFD + #01 + + + 10 + derive clock from 307M PFD + #10 + + + 11 + derive clock from 198MHz clock (divided 396MHz PLL2 PFD) + #11 + + + + + periph2_clk2_sel + no description available + 20 + 1 + read-write + + + 0 + derive clock from pll3_sw_clk + #0 + + + 1 + derive clock from PLL2 Main + #1 + + + + + pre_periph2_clk_sel + no description available + 21 + 2 + read-write + + + 00 + derive clock from PLL2 main 528MHz clock + #00 + + + 01 + derive clock from 396MHz PLL2 PFD + #01 + + + 10 + derive clock from 307M PFD + #10 + + + 11 + derive clock from 198MHz clock (divided 396MHz PLL2 PFD) + #11 + + + + + mlb_sys_clk_podf + no description available + 23 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + gpu3d_core_podf + no description available + 26 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + gpu2d_core_podf + no description available + 29 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0xF00000 + 0xFFFFFFFF + + + perclk_podf + no description available + 0 + 6 + read-write + + + 000 + divide by 1 (default) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 6 + 4 + read-only + + + ssi1_clk_sel + no description available + 10 + 2 + read-write + + + 00 + derive clock from 508.2M PFD (default) + #00 + + + 10 + derive clock from pll4 + #10 + + + 11 + Restricted + #11 + + + + + ssi2_clk_sel + no description available + 12 + 2 + read-write + + + 00 + derive clock from 508.2M PFD (default) + #00 + + + 10 + derive clock from pll4 + #10 + + + 11 + Restricted + #11 + + + + + ssi3_clk_sel + no description available + 14 + 2 + read-write + + + 00 + derive clock from 508.2M PFD (default) + #00 + + + 10 + derive clock from pll4 + #10 + + + 11 + Restricted + #11 + + + + + usdhc1_clk_sel + no description available + 16 + 1 + read-write + + + 0 + derive clock from 396M PFD + #0 + + + 1 + derive clock from 307M PFD + #1 + + + + + usdhc2_clk_sel + no description available + 17 + 1 + read-write + + + 0 + derive clock from 396M PFD + #0 + + + 1 + derive clock from 307M PFD + #1 + + + + + usdhc3_clk_sel + no description available + 18 + 1 + read-write + + + 0 + derive clock from 396M PFD + #0 + + + 1 + derive clock from 307M PFD + #1 + + + + + usdhc4_clk_sel + no description available + 19 + 1 + read-write + + + 0 + derive clock from 396M PFD + #0 + + + 1 + derive clock from 307M PFD + #1 + + + + + aclk_podf + no description available + 20 + 3 + read-write + + + 000 + divide by 7 (Read value 110) + #000 + + + 001 + divide by 8 (Read value 111) + #001 + + + 010 + divide by 5 (Read value 100) + #010 + + + 011 + divide by 6 (Read value 101) + #011 + + + 100 + divide by 3 (Read value 010) + #100 + + + 101 + divide by 4 (Read value 011) + #101 + + + 110 + divide by 1 (Read value 000) + #110 + + + 111 + divide by 2 (default) (Read value 001) + #111 + + + + + aclk_eim_slow_podf + no description available + 23 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 26 + 1 + read-only + + + aclk_sel + no description available + 27 + 2 + read-write + + + 00 + derive clock from 396M PFD (default) + #00 + + + 01 + derive clock from PLL3 + #01 + + + 10 + derive clock from AXI clk root + #10 + + + 11 + derive clock from 307M PFD + #11 + + + + + aclk_eim_slow_sel + no description available + 29 + 2 + read-write + + + 00 + derive clock from AXI clk root (default) + #00 + + + 01 + derive clock from PLL3 + #01 + + + 10 + derive clock from 396M PFD + #10 + + + 11 + derive clock from 307M PFD + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x2B92F06 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + can_clk_podf + no description available + 2 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 000111 + divide by 8 + #000111 + + + 111111 + divide by 2^6 + #111111 + + + + + RESERVED + no description available + 8 + 2 + read-only + + + ldb_di0_ipu_div + no description available + 10 + 1 + read-write + + + 0 + divide by 3.5 + #0 + + + 1 + divide by 7(default) + #1 + + + + + ldb_di1_ipu_div + no description available + 11 + 1 + read-write + + + 0 + divide by 3.5 + #0 + + + 1 + divide by 7(default) + #1 + + + + + RESERVED + no description available + 12 + 7 + read-only + + + esai_clk_sel + no description available + 19 + 2 + read-write + + + 00 + derive clock from pll4 divided clock + #00 + + + 01 + derive clock from 508M PFD clock + #01 + + + 11 + derive clock from pll3 clock + #11 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x490B00 + 0xFFFFFFFF + + + uart_clk_podf + no description available + 0 + 6 + read-write + + + 000000 + divide by 1 (default) + #000000 + + + 111111 + divide by 2^6 + #111111 + + + + + RESERVED + no description available + 6 + 5 + read-only + + + usdhc1_podf + no description available + 11 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + usdhc2_podf + no description available + 16 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + usdhc3_podf + no description available + 19 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + usdhc4_podf + no description available + 22 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + vpu_axi_podf + no description available + 25 + 3 + read-write + + + 000 + divide by 1 (default) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CS1CDR + CCM SSI1 Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + ssi1_clk_podf + no description available + 0 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 111111 + divide by 2^6 + #111111 + + + + + ssi1_clk_pred + no description available + 6 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + esai_clk_pred + no description available + 9 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + ssi3_clk_podf + no description available + 16 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 111111 + divide by 2^6 + #111111 + + + + + ssi3_clk_pred + no description available + 22 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + esai_clk_podf + no description available + 25 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CS2CDR + CCM SSI2 Clock Divider Register + 0x2C + 32 + read-write + 0x736C1 + 0xFFFFFFFF + + + ssi2_clk_podf + no description available + 0 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 111111 + divide by 2^6 + #111111 + + + + + ssi2_clk_pred + no description available + 6 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + ldb_di0_clk_sel + no description available + 9 + 3 + read-write + + + 000 + pll5 clock + #000 + + + 001 + pll2 307M PFD (default) + #001 + + + 010 + pll2 396M PFD + #010 + + + 011 + MMDC_CH1 clock + #011 + + + 100 + pll3 clock + #100 + + + 101 + 111 Resrticted + #101 + + + + + ldb_di1_clk_sel + no description available + 12 + 3 + read-write + + + 000 + pll5 clock + #000 + + + 001 + pll2 307M PFD (default) + #001 + + + 010 + pll2 396M PFD + #010 + + + 011 + MMDC_CH1 clock + #011 + + + 100 + pll3 clock + #100 + + + 101 + 111 Resrticted + #101 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + enfc_clk_sel + no description available + 16 + 2 + read-write + + + 00 + pll2 307M PFD (default) + #00 + + + 01 + pll2 clock + #01 + + + 10 + pll3 clock + #10 + + + 11 + pll2 396M PFD + #11 + + + + + enfc_clk_pred + no description available + 18 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + enfc_clk_podf + no description available + 21 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 000001 + divide by 2 (default) + #000001 + + + 111111 + divide by 2^6 + #111111 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 7 + read-only + + + spdif1_clk_sel + no description available + 7 + 2 + read-write + + + 00 + derive clock from pll4 divided clock + #00 + + + 01 + derive clock from 508M PFD clock + #01 + + + 11 + derive clock from pll3 clock + #11 + + + + + spdif1_clk_podf + no description available + 9 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 111 + divide by 8 + #111 + + + + + spdif1_clk_pred + no description available + 12 + 3 + read-write + + + 000 + divide by 1 (do not use with high input frequencies) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 (default) + #010 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + RESERVED + no description available + 16 + 4 + read-only + + + spdif0_clk_sel + no description available + 20 + 2 + read-write + + + 00 + derive clock from pll4 divided clock + #00 + + + 01 + derive clock from 508M PFD clock + #01 + + + 11 + derive clock from pll3 clock + #11 + + + + + spdif0_clk_podf + no description available + 22 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 111 + divide by 8 + #111 + + + + + spdif0_clk_pred + no description available + 25 + 3 + read-write + + + 000 + divide by 1 (do not use with high input frequencies) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 (default) + #010 + + + 111 + divide by 8 + #111 + + + + + hsi_tx_clk_sel + no description available + 28 + 1 + read-write + + + 0 + derive from pll3 120M clock (default) + #0 + + + 1 + derive from pll2 396M PFD + #1 + + + + + hsi_tx_podf + no description available + 29 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 (default) + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + + + CHSCCDR + CCM HSC Clock Divider Register + 0x34 + 32 + read-write + 0x2A150 + 0xFFFFFFFF + + + ipu1_di0_clk_sel + no description available + 0 + 3 + read-write + + + 000 + derive clock from divided pre-muxed ipu1 di0 clock (default) + #000 + + + 001 + derive clock from ipp_di0_clk + #001 + + + 010 + derive clock from ipp_di1_clk + #010 + + + 011 + derive clock from ldb_di0_clk + #011 + + + 100 + derive clock from ldb_di1_clk + #100 + + + + + ipu1_di0_podf + no description available + 3 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 (default) + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + ipu1_di0_pre_clk_sel + no description available + 6 + 3 + read-write + + + 000 + derive clock from mmdc_ch0 clock + #000 + + + 001 + derive clock from pll3 + #001 + + + 010 + derive clock from pll5 + #010 + + + 011 + derive clock from 307M PFD + #011 + + + 100 + derive clock from 396M PFD + #100 + + + 101 + derive clock from 540M PFD + #101 + + + + + ipu1_di1_clk_sel + no description available + 9 + 3 + read-write + + + 000 + derive clock from divided pre-muxed ipu1 di1 clock (default) + #000 + + + 001 + derive clock from ipp_di0_clk + #001 + + + 010 + derive clock from ipp_di1_clk + #010 + + + 011 + derive clock from ldb_di0_clk + #011 + + + 100 + derive clock from ldb_di1_clk + #100 + + + + + ipu1_di1_podf + no description available + 12 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 (default) + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + ipu1_di1_pre_clk_sel + no description available + 15 + 3 + read-write + + + 000 + derive clock from mmdc_ch0 clock + #000 + + + 001 + derive clock from pll3 + #001 + + + 010 + derive clock from pll5 + #010 + + + 011 + derive clock from 307M PFD + #011 + + + 100 + derive clock from 396M PFD + #100 + + + 101 + derive clock from 540M PFD + #101 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29B48 + 0xFFFFFFFF + + + lcdif_pix_clk_sel + no description available + 0 + 3 + read-write + + + 000 + derive clock from divided pre-muxed lcdif_pix clock (default) + #000 + + + 001 + derive clock from ipp_di0_clk + #001 + + + 010 + derive clock from ipp_di1_clk + #010 + + + 011 + derive clock from ldb_di0_clk + #011 + + + 100 + derive clock from ldb_di1_clk + #100 + + + + + lcdif_pix_podf + no description available + 3 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 (default) + #111 + + + + + lcdif_pix_pre_clk_sel + no description available + 6 + 3 + read-write + + + 000 + derive clock from mmdc_ch0 clock + #000 + + + 001 + derive clock from pll3 (default) + #001 + + + 010 + derive clock from pll5 + #010 + + + 011 + derive clock from 307M PFD + #011 + + + 100 + derive clock from 396M PFD + #100 + + + 101 + derive clock from 540M PFD + #101 + + + + + epdc_pix_clk_sel + no description available + 9 + 3 + read-write + + + 000 + derive clock from divided pre-muxed epdc_pix clock (default) + #000 + + + 001 + derive clock from ipp_di0_clk + #001 + + + 010 + derive clock from ipp_di1_clk + #010 + + + 011 + derive clock from ldb_di0_clk + #011 + + + 100 + derive clock from ldb_di1_clk + #100 + + + + + epdc_pix_podf + no description available + 12 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 (default) + #111 + + + + + epdc_pix_pre_clk_sel + no description available + 15 + 3 + read-write + + + 000 + derive clock from mmdc_ch0 clock + #000 + + + 001 + derive clock from pll3 + #001 + + + 010 + derive clock from pll5 + #010 + + + 011 + derive clock from 307M PFD + #011 + + + 100 + derive clock from 396M PFD + #100 + + + 101 + derive clock from 540M PFD + #101 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + ecspi_clk_podf + no description available + 19 + 6 + read-write + + + 000000 + divide by 1 + #000000 + + + 111111 + divide by 2^6 + #111111 + + + + + RESERVED + no description available + 25 + 6 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x14841 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 9 + read-only + + + ipu1_hsp_clk_sel + no description available + 9 + 2 + read-write + + + 00 + derive clock from mmdc_ch0 clock (default) + #00 + + + 01 + derive clock from 396M PFD + #01 + + + 10 + derive clock from 120M + #10 + + + 11 + derive clock from 540M PFD + #11 + + + + + ipu1_hsp_podf + no description available + 11 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + epdc_clk_sel + no description available + 14 + 2 + read-write + + + 00 + derive clock from mmdc_ch0 clock + #00 + + + 01 + derive clock from 396M PFD (default) + #01 + + + 10 + derive clock from 120M + #10 + + + 11 + derive clock from 540M PFD + #11 + + + + + epdc_podf + no description available + 16 + 3 + read-write + + + 000 + divide by 1 + #000 + + + 001 + divide by 2 (default) + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + CWDR + CCM Wakeup Detector Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + axi_podf_busy + no description available + 0 + 1 + read-only + + + 0 + divider is not busy and its value represents the actual division. + #0 + + + 1 + divider is busy with handshake process with module. The value read in the divider represents the previous value odivision factor, and after the handshake the written value of the axi_podf will be applied. + #1 + + + + + ahb_podf_busy + no description available + 1 + 1 + read-only + + + 0 + divider is not busy and its value represents the actual division. + #0 + + + 1 + divider is busy with handshake process with module. The value read in the divider represents the previous value odivision factor, and after the handshake the written value of the ahb_podf will be applied. + #1 + + + + + mmdc_ch1_podf_busy + no description available + 2 + 1 + read-only + + + 0 + divider is not busy and its value represents the actual division. + #0 + + + 1 + divider is busy with handshake process with module. The value read in the divider represents the previous value odivision factor, and after the handshake the written value of the mmdc_ch1_axi_podf will be applied. + #1 + + + + + periph2_clk_sel_busy + no description available + 3 + 1 + read-only + + + 0 + mux is not busy and its value represents the actual division. + #0 + + + 1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + #1 + + + + + mmdc_ch0_podf_busy + no description available + 4 + 1 + read-only + + + 0 + divider is not busy and its value represents the actual division. + #0 + + + 1 + divider is busy with handshake process with module. The value read in the divider represents the previous value odivision factor, and after the handshake the written value of the mmdc_ch0_axi_podf will be applied. + #1 + + + + + periph_clk_sel_busy + no description available + 5 + 1 + read-only + + + 0 + mux is not busy and its value represents the actual division. + #0 + + + 1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + #1 + + + + + RESERVED + no description available + 6 + 10 + read-only + + + arm_podf_busy + no description available + 16 + 1 + read-only + + + 0 + divider is not busy and its value represents the actual division. + #0 + + + 1 + divider is busy with handshake process with module. The value read in the divider represents the previous value odivision factor, and after the handshake the written value of the arm_podf will be applied. + #1 + + + + + RESERVED + no description available + 17 + 15 + read-only + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + no description available + 0 + 2 + read-write + + + 00 + Remain in run mode + #00 + + + 01 + Transfer to wait mode + #01 + + + 10 + Transfer to stop mode + #10 + + + 11 + Reserved + #11 + + + + + bypass_pmic_ready + no description available + 2 + 1 + read-write + + + 0 + Don't bypass the CCM_PMIC_READY signal - CCM will wait for it's assertion during exit of low power mode if standby voltage was enabled. + #0 + + + 1 + bypass the CCM_PMIC_READY signal - CCM will not wait for it's assertion during exit of low power mode if standby voltage was enabled. + #1 + + + + + RESERVED + no description available + 3 + 2 + read-only + + + ARM_clk_dis_on_lpm + no description available + 5 + 1 + read-write + + + 0 + ARM clock enabled on wait mode. + #0 + + + 1 + ARM clock disabled on wait mode. (default). + #1 + + + + + SBYOS + no description available + 6 + 1 + read-write + + + 0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + #0 + + + 1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). (Default.) When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + #1 + + + + + dis_ref_osc + no description available + 7 + 1 + read-write + + + 0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.(default) + #0 + + + 1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + #1 + + + + + VSTBY + no description available + 8 + 1 + read-write + + + 0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_VSTBY_REQ will remain negated - '0') + #0 + + + 1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_VSTBY_REQ will be asserted - '1'). + #1 + + + + + stby_count + no description available + 9 + 2 + read-write + + + 00 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + #00 + + + 01 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + #01 + + + 10 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + #10 + + + 11 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + #11 + + + + + cosc_pwrdown + no description available + 11 + 1 + read-write + + + 0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.(default) + #0 + + + 1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + #1 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + wb_per_at_lpm + no description available + 16 + 1 + read-write + + + 0 + Periphery charge pump won't be enabled at STOP or WAIT low power modes + #0 + + + 1 + Periphery charge pump will be enabled at STOP or WAIT low power modes + #1 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + RESERVED + no description available + 18 + 1 + read-only + + + bypass_mmdc_ch0_lpm_hs + no description available + 19 + 1 + read-write + + + 0 + Handshake with mmdc_ch0 on next entrance to low power mode will be performed. (default). + #0 + + + 1 + Handshake with mmdc_ch0 on next entrance to low power mode will be bypassed. + #1 + + + + + RESERVED + no description available + 20 + 1 + read-only + + + bypass_mmdc_ch1_lpm_hs + no description available + 21 + 1 + read-write + + + 0 + Handshake with mmdc_ch1 on next entrance to low power mode will be performed. (Default.) + #0 + + + 1 + Handshake with mmdc_ch1 on next entrance to low power mode will be bypassed. + #1 + + + + + mask_core0_wfi + no description available + 22 + 1 + read-write + + + 0 + WFI of core0 is not masked + #0 + + + 1 + WFI of core0 is masked + #1 + + + + + mask_core1_wfi + no description available + 23 + 1 + read-write + + + 1 + WFI of core1 is masked + #1 + + + 0 + WFI of core1 is not masked + #0 + + + + + RESERVED + no description available + 24 + 2 + read-only + + + mask_scu_idle + no description available + 26 + 1 + read-write + + + 1 + SCU IDLE is masked + #1 + + + 0 + SCU IDLE is not masked + #0 + + + + + mask_l2cc_idle + no description available + 27 + 1 + read-write + + + 1 + L2CC IDLE is masked + #1 + + + 0 + L2CC IDLE is not masked + #0 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + lrf_pll + no description available + 0 + 1 + read-write + + + 0 + interrupt is not genrerated due to lock ready of all enabled and not bypaseed PLLs + #0 + + + 1 + interrupt genrerated due to lock ready of all enabled and not bypaseed PLLs + #1 + + + + + RESERVED + no description available + 1 + 5 + read-only + + + cosc_ready + no description available + 6 + 1 + read-write + + + 0 + interrupt is not genrerated due to on board oscillator ready + #0 + + + 1 + interrupt genrerated due to on board oscillator ready + #1 + + + + + RESERVED + no description available + 7 + 10 + read-only + + + axi_podf_loaded + no description available + 17 + 1 + read-write + + + 0 + interrupt is not genrerated due to frequency change of axi_podf + #0 + + + 1 + interrupt genrerated due to frequency change of axi_podf + #1 + + + + + mmdc_ch0_axi_podf_loaded + no description available + 18 + 1 + read-only + + + 0 + interrupt is not genrerated due to frequency change of mmdc_ch0_axi_podf + #0 + + + 1 + interrupt genrerated due to frequency change of mmdc_ch0_axi_podf + #1 + + + + + periph2_clk_sel_loaded + no description available + 19 + 1 + read-write + + + 0 + interrupt is not genrerated due to frequency change of periph2_clk_sel + #0 + + + 1 + interrupt genrerated due to frequency change of periph2_clk_sel + #1 + + + + + ahb_podf_loaded + no description available + 20 + 1 + read-write + + + 0 + interrupt is not genrerated due to frequency change of ahb_podf + #0 + + + 1 + interrupt genrerated due to frequency change of ahb_podf + #1 + + + + + mmdc_ch1_podf_loaded + no description available + 21 + 1 + read-write + + + 0 + interrupt is not genrerated due to frequency change of mmdc_ch0_podf_ loaded + #0 + + + 1 + interrupt genrerated due to frequency change of mmdc_ch0_podf_ loaded + #1 + + + + + periph_clk_sel_loaded + no description available + 22 + 1 + read-write + + + 0 + interrupt is not genrerated due to update of periph_clk_sel. + #0 + + + 1 + interrupt genrerated due to update of periph_clk_sel. + #1 + + + + + mmdc_ch0_podf_loaded + no description available + 23 + 1 + read-write + + + 0 + interrupt is not genrerated due to update of mmdc_ch0_axi_podf. + #0 + + + 1 + interrupt genrerated due to update of mmdc_ch0_axi_podf* + #1 + + + + + RESERVED + no description available + 24 + 2 + read-only + + + arm_podf_loaded + no description available + 26 + 1 + read-write + + + 0 + interrupt is not genrerated due to frequency change of arm_podf + #0 + + + 1 + interrupt genrerated due to frequency change of arm_podf + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + mask_lrf_pll + no description available + 0 + 1 + read-write + + + 0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + #0 + + + 1 + mask interrupt due to lrf of PLLs + #1 + + + + + RESERVED + no description available + 1 + 5 + read-only + + + mask_cosc_ready + no description available + 6 + 1 + read-write + + + 0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + #0 + + + 1 + mask interrupt due to on board oscillator ready + #1 + + + + + RESERVED + no description available + 7 + 10 + read-only + + + mask_axi_podf_loaded + no description available + 17 + 1 + read-write + + + 0 + don't mask interrupt due to frequency change of axi_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to frequency change of axi_podf + #1 + + + + + mask_mmdc_ch0_axi_podf_loaded + no description available + 18 + 1 + read-only + + + 0 + don't mask interrupt due to frequency change of mmdc_ch0_axi_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to frequency change of mmdc_ch0_axi_podf + #1 + + + + + mask_periph2_clk_sel_loaded + no description available + 19 + 1 + read-write + + + 0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + #0 + + + 1 + mask interrupt due to update of periph2_clk_sel + #1 + + + + + mask_ahb_podf_loaded + no description available + 20 + 1 + read-write + + + 0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to frequency change of ahb_podf + #1 + + + + + mask_mmdc_ch1_podf_loaded + no description available + 21 + 1 + read-write + + + 0 + don't mask interrupt due to update of mask_mmdc_ch1_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to update of mask_mmdc_ch1_podf + #1 + + + + + mask_periph_clk_sel_loaded + no description available + 22 + 1 + read-write + + + 0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + #0 + + + 1 + mask interrupt due to update of periph_clk_sel + #1 + + + + + mask_mmdc_ch0_podf_loaded + no description available + 23 + 1 + read-write + + + 0 + don't mask interrupt due to update of mask_mmdc_ch0_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to update of mask_mmdc_ch0_podf + #1 + + + + + RESERVED + no description available + 24 + 2 + read-only + + + arm_podf_loaded + no description available + 26 + 1 + read-write + + + 0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + #0 + + + 1 + mask interrupt due to frequency change of arm_podf + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO1_SEL + no description available + 0 + 4 + read-write + + + 0000 + pll3_sw_clk (this inputs has additional constant division /2) + #0000 + + + 0001 + pll2_main_clk (default) (this inputs has additional constant division /2) + #0001 + + + 0010 + pll1_main_clk (this inputs has additional constant division /2) + #0010 + + + 0011 + pll5_main_clk (this inputs has additional constant division /2) + #0011 + + + 0100 + video_27M_clk_root + #0100 + + + 0101 + dtcp_clk_root + #0101 + + + 0110 + enfc_clk_root + #0110 + + + 0111 + ipu1_di0_clk_root + #0111 + + + 1000 + ipu1_di1_clk_root + #1000 + + + 1001 + lcdif_pix_clk_root + #1001 + + + 1010 + epdc_pix_clk_root + #1010 + + + 1011 + ahb_clk_root + #1011 + + + 1100 + ipg_clk_root + #1100 + + + 1101 + perclk_root + #1101 + + + 1110 + ckil_sync_clk_root + #1110 + + + 1111 + pll4_main_clk + #1111 + + + + + CLKO1_DIV + no description available + 4 + 3 + read-write + + + 000 + divide by 1(default) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + CLKO1_EN + no description available + 7 + 1 + read-write + + + 0 + CCM_CLKO1 disabled. + #0 + + + 1 + CCM_CLKO1 enabled. + #1 + + + + + CLK_OUT_SEL + no description available + 8 + 1 + read-write + + + 0 + CCM_CLKO1 output drives CCM_CLKO1 clock + #0 + + + 1 + CCM_CLKO1 output drives CCM_CLKO2 clock + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + CLKO2_SEL + no description available + 16 + 5 + read-write + + + 00000 + mmdc_ch0_axi_clk_root + #00000 + + + 00001 + mmdc_ch1_axi_clk_root + #00001 + + + 00010 + usdhc4_clk_root + #00010 + + + 00011 + usdhc1_clk_root + #00011 + + + 00101 + wrck_clk_root + #00101 + + + 00110 + ecspi_clk_root + #00110 + + + 01000 + usdhc3_clk_root + #01000 + + + 01001 + pcie_clk_root + #01001 + + + 01010 + arm_clk_root (default) + #01010 + + + 01011 + ipu1_hsp_clk_root + #01011 + + + 01100 + epdc_axi_clk_root, lcdif_axi_clk_root, pxp_axi_clk_root + #01100 + + + 01101 + vdo_axi_clk_root + #01101 + + + 01110 + osc_clk + #01110 + + + 01111 + mlb_sys_clk_root + #01111 + + + 10000 + gpu3d_core_clk_root + #10000 + + + 10001 + usdhc2_clk_root + #10001 + + + 10010 + ssi1_clk_root + #10010 + + + 10011 + ssi2_clk_root + #10011 + + + 10100 + ssi3_clk_root + #10100 + + + 10101 + gpu2d_core_clk_root + #10101 + + + 10110 + vpu_axi_clk_root + #10110 + + + 10111 + can_clk_root + #10111 + + + 11000 + ldb_di0_serial_clk_root + #11000 + + + 11001 + ldb_di1_serial_clk_root + #11001 + + + 11010 + esai_clk_root + #11010 + + + 11011 + aclk_eim_slow_clk_root + #11011 + + + 11100 + uart_clk_root + #11100 + + + 11101 + spdif0_clk_root + #11101 + + + 11110 + spdif1_clk_root + #11110 + + + 11111 + hsi_tx_clk_root + #11111 + + + + + CLKO2_DIV + no description available + 21 + 3 + read-write + + + 000 + divide by 1 (default) + #000 + + + 001 + divide by 2 + #001 + + + 010 + divide by 3 + #010 + + + 011 + divide by 4 + #011 + + + 100 + divide by 5 + #100 + + + 101 + divide by 6 + #101 + + + 110 + divide by 7 + #110 + + + 111 + divide by 8 + #111 + + + + + CLKO2_EN + no description available + 24 + 1 + read-write + + + 0 + CCM_CLKO2 disabled. + #0 + + + 1 + CCM_CLKO2 enabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + pmic_delay_scaler + no description available + 0 + 1 + read-write + + + 0 + clock is not divided + #0 + + + 1 + clock is divided /8 + #1 + + + + + RESERVED + no description available + 1 + 1 + write-only + + + mmdc_ext_clk_dis + no description available + 2 + 1 + read-write + + + 1 + disable during stop mode + #1 + + + 0 + don't disable during stop mode. + #0 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + efuse_prog_supply_gate + no description available + 4 + 1 + read-write + + + 0 + fuse programing supply voltage is gated off to the efuse module + #0 + + + 1 + allow fuse programing. + #1 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + RESERVED + no description available + 7 + 2 + read-only + + + RESERVED + no description available + 9 + 7 + read-only + + + FPL + Fast PLL enable. + 16 + 1 + read-write + + + 0 + Engage PLL enable default way. + #0 + + + 1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + #1 + + + + + INT_MEM_CLK_LPM + no description available + 17 + 1 + read-write + + + 0 + Disable the clock to the ARM platform memories when entering Low Power Mode (Default) + #0 + + + 1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + #1 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + no description available + 0 + 2 + read-write + + + CG1 + no description available + 2 + 2 + read-write + + + CG2 + no description available + 4 + 2 + read-write + + + CG3 + no description available + 6 + 2 + read-write + + + CG4 + no description available + 8 + 2 + read-write + + + CG5 + no description available + 10 + 2 + read-write + + + CG6 + no description available + 12 + 2 + read-write + + + CG7 + no description available + 14 + 2 + read-write + + + CG8 + no description available + 16 + 2 + read-write + + + CG9 + no description available + 18 + 2 + read-write + + + CG10 + no description available + 20 + 2 + read-write + + + CG11 + no description available + 22 + 2 + read-write + + + CG12 + no description available + 24 + 2 + read-write + + + CG13 + no description available + 26 + 2 + read-write + + + CG14 + no description available + 28 + 2 + read-write + + + CG15 + no description available + 30 + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + mod_en_ov_vdoa + no description available + 4 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_gpt + no description available + 5 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_epit + no description available + 6 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_usdhc + no description available + 7 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_dap + no description available + 8 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_vpu + no description available + 9 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_gpu2d + no description available + 10 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + mod_en_ov_gpu3d + no description available + 11 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + RESERVED + no description available + 12 + 16 + read-only + + + mod_en_ov_can2_cpi + no description available + 28 + 1 + read-write + + + 0 + don't override module enable signal + #0 + + + 1 + override module enable signal + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + mod_en_ov_can1_cpi + no description available + 30 + 1 + read-write + + + 0 + don't overide module enable signal + #0 + + + 1 + overide module enable signal + #1 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + + + PMU + PMU + PMU_ + 0x20C8000 + + 0x140 + 0x40 + registers + + + + REG_CORE + Digital Regulator Core Register + 0x140 + 32 + read-write + 0x402010 + 0xFFFFFFFF + + + REG0_TARG + no description available + 0 + 5 + read-write + + + 00000 + Power gated off + #00000 + + + 00001 + Target core voltage = 0.725V + #00001 + + + 10000 + Target core voltage = 1.100V + #10000 + + + 11110 + Target core voltage = 1.450V + #11110 + + + 11111 + Power FET switched full on. No regulation. + #11111 + + + + + REG0_ADJ + no description available + 5 + 4 + read-write + + + 0000 + No adjustment + #0000 + + + 0001 + + 0.25% + #0001 + + + 0010 + + 0.50% + #0010 + + + 0011 + + 0.75% + #0011 + + + 0100 + + 1.00% + #0100 + + + 0101 + + 1.25% + #0101 + + + 0110 + + 1.50% + #0110 + + + 0111 + + 1.75% + #0111 + + + 1000 + - 0.25% + #1000 + + + 1001 + - 0.50% + #1001 + + + 1010 + - 0.75% + #1010 + + + 1011 + - 1.00% + #1011 + + + 1100 + - 1.25% + #1100 + + + 1101 + - 1.50% + #1101 + + + 1110 + - 1.75% + #1110 + + + 1111 + - 2.00% + #1111 + + + + + REG1_TARG + no description available + 9 + 5 + read-write + + + 00000 + Power gated off + #00000 + + + 00001 + Target core voltage = 0.725V + #00001 + + + 10000 + Target core voltage = 1.100V + #10000 + + + 11110 + Target core voltage = 1.450V + #11110 + + + 11111 + Power FET switched full on. No regulation. + #11111 + + + + + REG1_ADJ + no description available + 14 + 4 + read-write + + + 0000 + No adjustment + #0000 + + + 0001 + + 0.25% + #0001 + + + 0010 + + 0.50% + #0010 + + + 0011 + + 0.75% + #0011 + + + 0100 + + 1.00% + #0100 + + + 0101 + + 1.25% + #0101 + + + 0110 + + 1.50% + #0110 + + + 0111 + + 1.75% + #0111 + + + 1000 + - 0.25% + #1000 + + + 1001 + - 0.50% + #1001 + + + 1010 + - 0.75% + #1010 + + + 1011 + - 1.00% + #1011 + + + 1100 + - 1.25% + #1100 + + + 1101 + - 1.50% + #1101 + + + 1110 + - 1.75% + #1110 + + + 1111 + - 2.00% + #1111 + + + + + REG2_TARG + no description available + 18 + 5 + read-write + + + 00000 + Power gated off + #00000 + + + 00001 + Target core voltage = 0.725V + #00001 + + + 10000 + Target core voltage = 1.100V + #10000 + + + 11110 + Target core voltage = 1.450V + #11110 + + + 11111 + Power FET switched full on. No regulation. + #11111 + + + + + REG2_ADJ + no description available + 23 + 4 + read-write + + + 0000 + No adjustment + #0000 + + + 0001 + + 0.25% + #0001 + + + 0010 + + 0.50% + #0010 + + + 0011 + + 0.75% + #0011 + + + 0100 + + 1.00% + #0100 + + + 0101 + + 1.25% + #0101 + + + 0110 + + 1.50% + #0110 + + + 0111 + + 1.75% + #0111 + + + 1000 + - 0.25% + #1000 + + + 1001 + - 0.50% + #1001 + + + 1010 + - 0.75% + #1010 + + + 1011 + - 1.00% + #1011 + + + 1100 + - 1.25% + #1100 + + + 1101 + - 1.50% + #1101 + + + 1110 + - 1.75% + #1110 + + + 1111 + - 2.00% + #1111 + + + + + RESERVED + no description available + 27 + 2 + read-only + + + FET_ODRIVE + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 2 + read-only + + + REFTOP_SELFBIASOFF + no description available + 3 + 1 + read-write + + + 0 + Uses coarse bias currents for startup + #0 + + + 1 + Uses bandgap-based bias currents for best performance. + #1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + 000 + Nominal VBG + #000 + + + 001 + VBG+0.78% + #001 + + + 010 + VBG+1.56% + #010 + + + 011 + VBG+2.34% + #011 + + + 100 + VBG-0.78% + #100 + + + 101 + VBG-1.56% + #101 + + + 110 + VBG-2.34% + #110 + + + 111 + VBG-3.12% + #111 + + + + + REFTOP_VBGUP + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 4 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + DEEP + #0 + + + 1 + LIGHT + #1 + + + + + discon_high_snvs + no description available + 13 + 1 + read-write + + + OSC_I + no description available + 14 + 2 + read-write + + + 00 + NOMINAL + #00 + + + 01 + MINUS_12_5_PERCENT + #01 + + + 10 + MINUS_25_PERCENT + #10 + + + 11 + MINUS_37_5_PERCENT + #11 + + + + + OSC_XTALOK + no description available + 16 + 1 + read-only + + + OSC_XTALOK_EN + no description available + 17 + 1 + read-write + + + WBCP_VPW_THRESH + no description available + 18 + 2 + read-write + + + 00 + NOMINAL_BIAS + #00 + + + 01 + PLUS_25MV + #01 + + + 10 + MINUS_25MV + #10 + + + 11 + MINUS_50MV + #11 + + + + + RESERVED + no description available + 20 + 5 + read-only + + + CLKGATE_CTRL + no description available + 25 + 1 + read-write + + + 0 + ALLOW_AUTO_GATE + #0 + + + 1 + NO_AUTO_GATE + #1 + + + + + CLKGATE_DELAY + no description available + 26 + 3 + read-write + + + 000 + 0.5ms + #000 + + + 001 + 1.0ms + #001 + + + 010 + 2.0ms + #010 + + + 011 + 3.0ms + #011 + + + 100 + 4.0ms + #100 + + + 101 + 5.0ms + #101 + + + 110 + 6.0ms + #110 + + + 111 + 7.0ms + #111 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + no description available + 0 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDS2_CLK_SEL + no description available + 5 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDSCLK1_OBEN + no description available + 10 + 1 + read-write + + + LVDSCLK2_OBEN + no description available + 11 + 1 + read-write + + + LVDSCLK1_IBEN + no description available + 12 + 1 + read-write + + + LVDSCLK2_IBEN + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 15 + read-only + + + IRQ_TEMPSENSE + no description available + 29 + 1 + read-write + + + IRQ_ANA_BO + no description available + 30 + 1 + read-write + + + IRQ_DIG_BO + no description available + 31 + 1 + read-write + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + no description available + 0 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDS2_CLK_SEL + no description available + 5 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDSCLK1_OBEN + no description available + 10 + 1 + read-write + + + LVDSCLK2_OBEN + no description available + 11 + 1 + read-write + + + LVDSCLK1_IBEN + no description available + 12 + 1 + read-write + + + LVDSCLK2_IBEN + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 15 + read-only + + + IRQ_TEMPSENSE + no description available + 29 + 1 + read-write + + + IRQ_ANA_BO + no description available + 30 + 1 + read-write + + + IRQ_DIG_BO + no description available + 31 + 1 + read-write + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + no description available + 0 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDS2_CLK_SEL + no description available + 5 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDSCLK1_OBEN + no description available + 10 + 1 + read-write + + + LVDSCLK2_OBEN + no description available + 11 + 1 + read-write + + + LVDSCLK1_IBEN + no description available + 12 + 1 + read-write + + + LVDSCLK2_IBEN + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 15 + read-only + + + IRQ_TEMPSENSE + no description available + 29 + 1 + read-write + + + IRQ_ANA_BO + no description available + 30 + 1 + read-write + + + IRQ_DIG_BO + no description available + 31 + 1 + read-write + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + no description available + 0 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDS2_CLK_SEL + no description available + 5 + 5 + read-write + + + 00000 + ARM_PLL + #00000 + + + 00001 + SYS_PLL + #00001 + + + 00010 + PFD4 + #00010 + + + 00011 + PFD5 + #00011 + + + 00100 + PFD6 + #00100 + + + 00101 + PFD7 + #00101 + + + 00110 + AUDIO_PLL + #00110 + + + 00111 + VIDEO_PLL + #00111 + + + 01000 + MLB_PLL + #01000 + + + 01001 + ETHERNET_REF + #01001 + + + 01010 + PCIE_REF + #01010 + + + 01100 + USB1_PLL + #01100 + + + 01101 + USB2_PLL + #01101 + + + 01110 + PFD0 + #01110 + + + 01111 + PFD1 + #01111 + + + 10000 + PFD2 + #10000 + + + 10001 + PFD3 + #10001 + + + 10010 + XTAL + #10010 + + + 10011 + LVDS1 + #10011 + + + 10100 + LVDS2 + #10100 + + + + + LVDSCLK1_OBEN + no description available + 10 + 1 + read-write + + + LVDSCLK2_OBEN + no description available + 11 + 1 + read-write + + + LVDSCLK1_IBEN + no description available + 12 + 1 + read-write + + + LVDSCLK2_IBEN + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 15 + read-only + + + IRQ_TEMPSENSE + no description available + 29 + 1 + read-write + + + IRQ_ANA_BO + no description available + 30 + 1 + read-write + + + IRQ_DIG_BO + no description available + 31 + 1 + read-write + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + + + TEMPMON + Temperature Monitor + TEMPMON_ + 0x20C8000 + + 0x180 + 0x20 + registers + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0x180 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + no description available + 0 + 1 + read-write + + + 0 + POWER_UP + #0 + + + 1 + POWER_DOWN + #1 + + + + + MEASURE_TEMP + no description available + 1 + 1 + read-write + + + 0 + STOP + #0 + + + 1 + START + #1 + + + + + FINISHED + no description available + 2 + 1 + read-only + + + 0 + INVALID + #0 + + + 1 + VALID + #1 + + + + + RESERVED + no description available + 3 + 3 + read-only + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + TEMP_CNT + no description available + 8 + 12 + read-only + + + ALARM_VALUE + no description available + 20 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x184 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + no description available + 0 + 1 + read-write + + + 0 + POWER_UP + #0 + + + 1 + POWER_DOWN + #1 + + + + + MEASURE_TEMP + no description available + 1 + 1 + read-write + + + 0 + STOP + #0 + + + 1 + START + #1 + + + + + FINISHED + no description available + 2 + 1 + read-only + + + 0 + INVALID + #0 + + + 1 + VALID + #1 + + + + + RESERVED + no description available + 3 + 3 + read-only + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + TEMP_CNT + no description available + 8 + 12 + read-only + + + ALARM_VALUE + no description available + 20 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x188 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + no description available + 0 + 1 + read-write + + + 0 + POWER_UP + #0 + + + 1 + POWER_DOWN + #1 + + + + + MEASURE_TEMP + no description available + 1 + 1 + read-write + + + 0 + STOP + #0 + + + 1 + START + #1 + + + + + FINISHED + no description available + 2 + 1 + read-only + + + 0 + INVALID + #0 + + + 1 + VALID + #1 + + + + + RESERVED + no description available + 3 + 3 + read-only + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + TEMP_CNT + no description available + 8 + 12 + read-only + + + ALARM_VALUE + no description available + 20 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0x18C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + no description available + 0 + 1 + read-write + + + 0 + POWER_UP + #0 + + + 1 + POWER_DOWN + #1 + + + + + MEASURE_TEMP + no description available + 1 + 1 + read-write + + + 0 + STOP + #0 + + + 1 + START + #1 + + + + + FINISHED + no description available + 2 + 1 + read-only + + + 0 + INVALID + #0 + + + 1 + VALID + #1 + + + + + RESERVED + no description available + 3 + 3 + read-only + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + TEMP_CNT + no description available + 8 + 12 + read-only + + + ALARM_VALUE + no description available + 20 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x190 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + no description available + 0 + 16 + read-write + + + 0 + Defines a single measurement with no repeat. + #0 + + + 1 + Updates the temperature value at a RTC clock rate. + #1 + + + 10 + Updates the temperature value at a RTC/2 clock rate. + #10 + + + 1111111111111111 + Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + #1111111111111111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x194 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + no description available + 0 + 16 + read-write + + + 0 + Defines a single measurement with no repeat. + #0 + + + 1 + Updates the temperature value at a RTC clock rate. + #1 + + + 10 + Updates the temperature value at a RTC/2 clock rate. + #10 + + + 1111111111111111 + Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + #1111111111111111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x198 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + no description available + 0 + 16 + read-write + + + 0 + Defines a single measurement with no repeat. + #0 + + + 1 + Updates the temperature value at a RTC clock rate. + #1 + + + 10 + Updates the temperature value at a RTC/2 clock rate. + #10 + + + 1111111111111111 + Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + #1111111111111111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x19C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + no description available + 0 + 16 + read-write + + + 0 + Defines a single measurement with no repeat. + #0 + + + 1 + Updates the temperature value at a RTC clock rate. + #1 + + + 10 + Updates the temperature value at a RTC/2 clock rate. + #10 + + + 1111111111111111 + Determines a two second sample period with a 32.768KHz RTC clock. Exact timings depend on the accuracy of the RTC clock. + #1111111111111111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + USB_ANALOG + USB Analog + USB_ANALOG_ + 0x20C8000 + + 0x1A0 + 0xC4 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0x1A0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x1A4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x1A8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x1AC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x1C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + no description available + 0 + 1 + read-only + + + BVALID + no description available + 1 + 1 + read-only + + + AVALID + no description available + 2 + 1 + read-only + + + VBUS_VALID + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x1D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + no description available + 0 + 1 + read-only + + + 0 + NO_CONTACT + #0 + + + 1 + GOOD_CONTACT + #1 + + + + + CHRG_DETECTED + no description available + 1 + 1 + read-only + + + 0 + CHARGER_NOT_PRESENT + #0 + + + 1 + CHARGER_PRESENT + #1 + + + + + DM_STATE + no description available + 2 + 1 + read-only + + + DP_STATE + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + USB1_MISC + USB Misc Register + 0x1F0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + no description available + 0 + 1 + read-write + + + EN_DEGLITCH + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 28 + read-only + + + EN_CLK_UTMI + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + USB1_MISC_SET + USB Misc Register + 0x1F4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + no description available + 0 + 1 + read-write + + + EN_DEGLITCH + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 28 + read-only + + + EN_CLK_UTMI + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + USB1_MISC_CLR + USB Misc Register + 0x1F8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + no description available + 0 + 1 + read-write + + + EN_DEGLITCH + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 28 + read-only + + + EN_CLK_UTMI + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + USB1_MISC_TOG + USB Misc Register + 0x1FC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + no description available + 0 + 1 + read-write + + + EN_DEGLITCH + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 28 + read-only + + + EN_CLK_UTMI + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x200 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x204 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x208 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x20C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + no description available + 0 + 3 + read-write + + + 000 + 4V0 + #000 + + + 001 + 4V1 + #001 + + + 010 + 4V2 + #010 + + + 011 + 4V3 + #011 + + + 100 + 4V4 + #100 + + + 101 + 4V5 + #101 + + + 110 + 4V6 + #110 + + + 111 + 4V7 + #111 + + + + + RESERVED + no description available + 3 + 17 + read-only + + + VBUSVALID_PWRUP_CMPS + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 5 + read-only + + + DISCHARGE_VBUS + no description available + 26 + 1 + read-write + + + CHARGE_VBUS + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 18 + read-only + + + CHK_CONTACT + no description available + 18 + 1 + read-write + + + 0 + NO_CHECK + #0 + + + 1 + CHECK + #1 + + + + + CHK_CHRG_B + no description available + 19 + 1 + read-write + + + 0 + CHECK + #0 + + + 1 + NO_CHECK + #1 + + + + + EN_B + no description available + 20 + 1 + read-write + + + 0 + ENABLE + #0 + + + 1 + DISABLE + #1 + + + + + RESERVED + no description available + 21 + 2 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + no description available + 0 + 1 + read-only + + + BVALID + no description available + 1 + 1 + read-only + + + AVALID + no description available + 2 + 1 + read-only + + + VBUS_VALID + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + no description available + 0 + 1 + read-only + + + 0 + NO_CONTACT + #0 + + + 1 + GOOD_CONTACT + #1 + + + + + CHRG_DETECTED + no description available + 1 + 1 + read-only + + + 0 + CHARGER_NOT_PRESENT + #0 + + + 1 + CHARGER_PRESENT + #1 + + + + + DM_STATE + no description available + 2 + 1 + read-only + + + DP_STATE + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + USB2_MISC + USB Misc Register + 0x250 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + no description available + 0 + 1 + read-write + + + EN_DEGLITCH + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 28 + read-only + + + EN_CLK_UTMI + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 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1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + LVDS_SEL + no description available + 17 + 1 + read-write + + + LVDS_24MHZ_SEL + no description available + 18 + 1 + read-write + + + PLL_SEL + no description available + 19 + 1 + read-write + + + RESERVED + no description available + 20 + 11 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13042 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + LVDS_SEL + no description available + 17 + 1 + read-write + + + LVDS_24MHZ_SEL + no description available + 18 + 1 + read-write + + + PLL_SEL + no description available + 19 + 1 + read-write + + + RESERVED + no description available + 20 + 11 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13042 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + LVDS_SEL + no description available + 17 + 1 + read-write + + + LVDS_24MHZ_SEL + no description available + 18 + 1 + read-write + + + PLL_SEL + no description available + 19 + 1 + read-write + + + RESERVED + no description available + 20 + 11 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + 0 + PLL outputs for USBPHYn off. + #0 + + + 1 + PLL outputs for USBPHYn on. + #1 + + + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + 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RESERVED + no description available + 17 + 14 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + 0 + PLL outputs for USBPHYn off. + #0 + + + 1 + PLL outputs for USBPHYn on. + #1 + + + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 14 + read-only + + + LOCK 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Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 14 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 14 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 14 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 4 + read-only + + + EN_USB_CLKS + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWER + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 14 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 6 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 12 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 6 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 12 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 6 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 12 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 6 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 12 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + no description available + 0 + 15 + read-write + + + ENABLE + no description available + 15 + 1 + read-write + + + 0 + Spread spectrum modulation disabled + #0 + + + 1 + Soread spectrum modulation enabled + #1 + + + + + STOP + no description available + 16 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + POST_DIV_SELECT + no description available + 19 + 2 + read-write + + + 00 + Divide by 4. + #00 + + + 01 + Divide by 2. + #01 + + + 10 + Divide by 1. + #10 + + + 11 + Reserved + #11 + + + + + SSC_EN + no description available + 21 + 1 + read-write + + + RESERVED + no description available + 22 + 9 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + PLL_MLB + MLB PLL Control Register + 0xD0 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + HOLD_RING_OFF + no description available + 11 + 1 + read-write + + + PHASE_SEL + no description available + 12 + 2 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + BYPASS + no description available + 16 + 1 + read-write + + + VDDA_DELAY_CFG + no description available + 17 + 3 + read-write + + + VDDD_DELAY_CFG + no description available + 20 + 3 + read-write + + + RX_CLK_DELAY_CFG + no description available + 23 + 3 + read-write + + + MLB_FLT_RES_CFG + no description available + 26 + 3 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + 0 + PLL is not currently locked + #0 + + + 1 + PLL is currently locked. + #1 + + + + + + + PLL_MLB_SET + MLB PLL Control Register + 0xD4 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + HOLD_RING_OFF + no description available + 11 + 1 + read-write + + + PHASE_SEL + no description available + 12 + 2 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + BYPASS + no description available + 16 + 1 + read-write + + + VDDA_DELAY_CFG + no description available + 17 + 3 + read-write + + + VDDD_DELAY_CFG + no description available + 20 + 3 + read-write + + + RX_CLK_DELAY_CFG + no description available + 23 + 3 + read-write + + + MLB_FLT_RES_CFG + no description available + 26 + 3 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + 0 + PLL is not currently locked + #0 + + + 1 + PLL is currently locked. + #1 + + + + + + + PLL_MLB_CLR + MLB PLL Control Register + 0xD8 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + HOLD_RING_OFF + no description available + 11 + 1 + read-write + + + PHASE_SEL + no description available + 12 + 2 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + BYPASS + no description available + 16 + 1 + read-write + + + VDDA_DELAY_CFG + no description available + 17 + 3 + read-write + + + VDDD_DELAY_CFG + no description available + 20 + 3 + read-write + + + RX_CLK_DELAY_CFG + no description available + 23 + 3 + read-write + + + MLB_FLT_RES_CFG + no description available + 26 + 3 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + 0 + PLL is not currently locked + #0 + + + 1 + PLL is currently locked. + #1 + + + + + + + PLL_MLB_TOG + MLB PLL Control Register + 0xDC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + HOLD_RING_OFF + no description available + 11 + 1 + read-write + + + PHASE_SEL + no description available + 12 + 2 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + BYPASS + no description available + 16 + 1 + read-write + + + VDDA_DELAY_CFG + no description available + 17 + 3 + read-write + + + VDDD_DELAY_CFG + no description available + 20 + 3 + read-write + + + RX_CLK_DELAY_CFG + no description available + 23 + 3 + read-write + + + MLB_FLT_RES_CFG + no description available + 26 + 3 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + 0 + PLL is not currently locked + #0 + + + 1 + PLL is currently locked. + #1 + + + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 5 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + ENABLE_125M + no description available + 19 + 1 + read-write + + + ENABLE_100M + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 10 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 5 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + ENABLE_125M + no description available + 19 + 1 + read-write + + + ENABLE_100M + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 10 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 5 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + ENABLE_125M + no description available + 19 + 1 + read-write + + + ENABLE_100M + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 10 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + no description available + 0 + 2 + read-write + + + RESERVED + no description available + 2 + 5 + read-only + + + RESERVED + no description available + 7 + 5 + read-only + + + POWERDOWN + no description available + 12 + 1 + read-write + + + ENABLE + no description available + 13 + 1 + read-write + + + BYPASS_CLK_SRC + no description available + 14 + 2 + read-write + + + 0 + REF_CLK_24M + #0 + + + 1 + CLK1 + #1 + + + 10 + CLK2 + #10 + + + 11 + XOR + #11 + + + + + BYPASS + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + PFD_OFFSET_EN + no description available + 18 + 1 + read-write + + + ENABLE_125M + no description available + 19 + 1 + read-write + + + ENABLE_100M + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 10 + read-only + + + LOCK + no description available + 31 + 1 + read-only + + + + + PFD_480 + 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + PFD3_FRAC + no description available + 24 + 6 + read-write + + + PFD3_STABLE + no description available + 30 + 1 + read-only + + + PFD3_CLKGATE + no description available + 31 + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + PFD3_FRAC + no description available + 24 + 6 + read-write + + + PFD3_STABLE + no description available + 30 + 1 + read-only + + + PFD3_CLKGATE + no description available + 31 + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + PFD3_FRAC + no description available + 24 + 6 + read-write + + + PFD3_STABLE + no description available + 30 + 1 + read-only + + + PFD3_CLKGATE + no description available + 31 + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + PFD3_FRAC + no description available + 24 + 6 + read-write + + + PFD3_STABLE + no description available + 30 + 1 + read-only + + + PFD3_CLKGATE + no description available + 31 + 1 + read-write + + + + + PFD_528 + 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + PFD_528_SET + 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + PFD_528_CLR + 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + PFD_528_TOG + 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + no description available + 0 + 6 + read-write + + + PFD0_STABLE + no description available + 6 + 1 + read-only + + + PFD0_CLKGATE + no description available + 7 + 1 + read-write + + + PFD1_FRAC + no description available + 8 + 6 + read-write + + + PFD1_STABLE + no description available + 14 + 1 + read-only + + + PFD1_CLKGATE + no description available + 15 + 1 + read-write + + + PFD2_FRAC + no description available + 16 + 6 + read-write + + + PFD2_STABLE + no description available + 22 + 1 + read-only + + + PFD2_CLKGATE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + MISC0 + Miscellaneous Control Register + 0x150 + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + All the analog domain except the RTC is powered down on STOP mode assertion + #0 + + + 1 + All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + MISC0_SET + Miscellaneous Control Register + 0x154 + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + All the analog domain except the RTC is powered down on STOP mode assertion + #0 + + + 1 + All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + MISC0_CLR + Miscellaneous Control Register + 0x158 + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + All the analog domain except the RTC is powered down on STOP mode assertion + #0 + + + 1 + All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + MISC0_TOG + Miscellaneous Control Register + 0x15C + 32 + read-write + 0x2000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + All the analog domain except the RTC is powered down on STOP mode assertion + #0 + + + 1 + All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + no description available + 0 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG0_BO_STATUS + no description available + 3 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + REG0_ENABLE_BO + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-only + + + PLL3_disable + no description available + 7 + 1 + read-write + + + REG1_BO_OFFSET + no description available + 8 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG1_BO_STATUS + no description available + 11 + 1 + read-only + + + 1 + Brownout, supply is below target minus brownout offset. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + REG1_ENABLE_BO + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 1 + read-only + + + AUDIO_DIV_LSB + no description available + 15 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG2_BO_OFFSET + no description available + 16 + 3 + read-only + + + 100 + Brownout offset = 0.100V + #100 + + + 111 + Brownout offset = 0.175V + #111 + + + + + REG2_BO_STATUS + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + REG2_ENABLE_BO + no description available + 21 + 1 + read-write + + + REG2_OK + no description available + 22 + 1 + read-only + + + AUDIO_DIV_MSB + no description available + 23 + 1 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + + + REG0_STEP_TIME + no description available + 24 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG1_STEP_TIME + no description available + 26 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + REG2_STEP_TIME + no description available + 28 + 2 + read-write + + + 00 + 64_CLOCKS + #00 + + + 01 + 128_CLOCKS + #01 + + + 10 + 256_CLOCKS + #10 + + + 11 + 512_CLOCKS + #11 + + + + + VIDEO_DIV + no description available + 30 + 2 + read-write + + + 00 + divide by 1 (Default) + #00 + + + 01 + divide by 2 + #01 + + + 10 + divide by 1 + #10 + + + 11 + divide by 4 + #11 + + + + + + + + + XTALOSC24M + XTALOSC24M + XTALOSC24M_ + 0x20C8000 + + 0x150 + 0x4 + registers + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + no description available + 0 + 1 + read-write + + + 0 + Bandgap reference is enabled. + #0 + + + 1 + Bandgap reference is disabled. Current consumption is removed from the supply via internal configuration. + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + REFTOP_SELFBIASOFF + no description available + 3 + 1 + read-write + + + 0 + Uses coarse bias currents for startup + #0 + + + 1 + Uses bandgap based bias currents for best performance. + #1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + 000 + Nominal VBG + #000 + + + 001 + VBG+0.78% + #001 + + + 010 + VBG+1.56% + #010 + + + 011 + VBG+2.34% + #011 + + + 100 + VBG-0.78% + #100 + + + 101 + VBG-1.56% + #101 + + + 110 + VBG-2.34% + #110 + + + 111 + VBG-3.12% + #111 + + + + + REFTOP_VBGUP + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 4 + read-only + + + STOP_MODE_CONFIG + no description available + 12 + 1 + read-write + + + 0 + All the analog domain except the RTC is powered down on STOP mode assertion + #0 + + + 1 + All the analog domain except the LDO_1P1 and LDO_2P5 regulators are powered down on STOP mode assertion. If required the CCM can be configured to not power down the oscillator (XTALOSC). + #1 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + OSC_I + no description available + 14 + 2 + read-write + + + 00 + Nominal + #00 + + + 01 + Decrease current by 12.5% + #01 + + + 10 + Decrease current by 25.0% + #10 + + + 11 + Decrease current by 37.5% + #11 + + + + + OSC_XTALOK + no description available + 16 + 1 + read-only + + + 0 + Xtal clock not ok for use. + #0 + + + 1 + Xtal clock ok for use. + #1 + + + + + OSC_XTALOK_EN + no description available + 17 + 1 + read-write + + + 0 + Xtal_ok function disabled + #0 + + + 1 + Xtal_ok function enabled + #1 + + + + + WBCP_VPW_THRESH + no description available + 18 + 2 + read-write + + + 00 + Nominal output pwell bias voltage. + #00 + + + 01 + Increase pwell output voltage by 25mV. + #01 + + + 10 + Decrease pwell output pwell voltage by 25mV. + #10 + + + 11 + Decrease pwell output pwell voltage by 50mV. + #11 + + + + + RESERVED + no description available + 20 + 5 + read-only + + + CLKGATE_CTRL + no description available + 25 + 1 + read-write + + + 0 + Allow the logic to automatically gate the clock when the XTAL is powered down. + #0 + + + 1 + Prevent the logic from ever gating off the clock. + #1 + + + + + CLKGATE_DELAY + no description available + 26 + 3 + read-write + + + 000 + 0.5ms + #000 + + + 001 + 1.0ms + #001 + + + 010 + 2.0ms + #010 + + + 011 + 3.0ms + #011 + + + 100 + 4.0ms + #100 + + + 101 + 5.0ms + #101 + + + 110 + 6.0ms + #110 + + + 111 + 7.0ms + #111 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + 0x20C9000 + + 0 + 0x84 + registers + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 10 + read-only + + + TXPWDFS + no description available + 10 + 1 + read-write + + + TXPWDIBIAS + no description available + 11 + 1 + read-write + + + TXPWDV2I + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 4 + read-only + + + RXPWDENV + no description available + 17 + 1 + read-write + + + RXPWD1PT1 + no description available + 18 + 1 + read-write + + + RXPWDDIFF + no description available + 19 + 1 + read-write + + + RXPWDRX + no description available + 20 + 1 + read-write + + + RSVD2 + no description available + 21 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 10 + read-only + + + TXPWDFS + no description available + 10 + 1 + read-write + + + TXPWDIBIAS + no description available + 11 + 1 + read-write + + + TXPWDV2I + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 4 + read-only + + + RXPWDENV + no description available + 17 + 1 + read-write + + + RXPWD1PT1 + no description available + 18 + 1 + read-write + + + RXPWDDIFF + no description available + 19 + 1 + read-write + + + RXPWDRX + no description available + 20 + 1 + read-write + + + RSVD2 + no description available + 21 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 10 + read-only + + + TXPWDFS + no description available + 10 + 1 + read-write + + + TXPWDIBIAS + no description available + 11 + 1 + read-write + + + TXPWDV2I + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 4 + read-only + + + RXPWDENV + no description available + 17 + 1 + read-write + + + RXPWD1PT1 + no description available + 18 + 1 + read-write + + + RXPWDDIFF + no description available + 19 + 1 + read-write + + + RXPWDRX + no description available + 20 + 1 + read-write + + + RSVD2 + no description available + 21 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 10 + read-only + + + TXPWDFS + no description available + 10 + 1 + read-write + + + TXPWDIBIAS + no description available + 11 + 1 + read-write + + + TXPWDV2I + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 4 + read-only + + + RXPWDENV + no description available + 17 + 1 + read-write + + + RXPWD1PT1 + no description available + 18 + 1 + read-write + + + RXPWDDIFF + no description available + 19 + 1 + read-write + + + RXPWDRX + no description available + 20 + 1 + read-write + + + RSVD2 + no description available + 21 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + no description available + 0 + 4 + read-write + + + RSVD0 + no description available + 4 + 4 + read-write + + + TXCAL45DN + no description available + 8 + 4 + read-write + + + RSVD1 + no description available + 12 + 4 + read-write + + + TXCAL45DP + no description available + 16 + 4 + read-write + + + RSVD2 + no description available + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + no description available + 26 + 3 + read-write + + + RSVD5 + no description available + 29 + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + no description available + 0 + 4 + read-write + + + RSVD0 + no description available + 4 + 4 + read-write + + + TXCAL45DN + no description available + 8 + 4 + read-write + + + RSVD1 + no description available + 12 + 4 + read-write + + + TXCAL45DP + no description available + 16 + 4 + read-write + + + RSVD2 + no description available + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + no description available + 26 + 3 + read-write + + + RSVD5 + no description available + 29 + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + no description available + 0 + 4 + read-write + + + RSVD0 + no description available + 4 + 4 + read-write + + + TXCAL45DN + no description available + 8 + 4 + read-write + + + RSVD1 + no description available + 12 + 4 + read-write + + + TXCAL45DP + no description available + 16 + 4 + read-write + + + RSVD2 + no description available + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + no description available + 26 + 3 + read-write + + + RSVD5 + no description available + 29 + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + no description available + 0 + 4 + read-write + + + RSVD0 + no description available + 4 + 4 + read-write + + + TXCAL45DN + no description available + 8 + 4 + read-write + + + RSVD1 + no description available + 12 + 4 + read-write + + + TXCAL45DP + no description available + 16 + 4 + read-write + + + RSVD2 + no description available + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + no description available + 26 + 3 + read-write + + + RSVD5 + no description available + 29 + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + no description available + 0 + 3 + read-write + + + RSVD0 + no description available + 3 + 1 + read-only + + + DISCONADJ + no description available + 4 + 3 + read-write + + + RSVD1 + no description available + 7 + 15 + read-only + + + RXDBYPASS + no description available + 22 + 1 + read-write + + + RSVD2 + no description available + 23 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + no description available + 0 + 3 + read-write + + + RSVD0 + no description available + 3 + 1 + read-only + + + DISCONADJ + no description available + 4 + 3 + read-write + + + RSVD1 + no description available + 7 + 15 + read-only + + + RXDBYPASS + no description available + 22 + 1 + read-write + + + RSVD2 + no description available + 23 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + no description available + 0 + 3 + read-write + + + RSVD0 + no description available + 3 + 1 + read-only + + + DISCONADJ + no description available + 4 + 3 + read-write + + + RSVD1 + no description available + 7 + 15 + read-only + + + RXDBYPASS + no description available + 22 + 1 + read-write + + + RSVD2 + no description available + 23 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + no description available + 0 + 3 + read-write + + + RSVD0 + no description available + 3 + 1 + read-only + + + DISCONADJ + no description available + 4 + 3 + read-write + + + RSVD1 + no description available + 7 + 15 + read-only + + + RXDBYPASS + no description available + 22 + 1 + read-write + + + RSVD2 + no description available + 23 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + no description available + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + no description available + 1 + 1 + read-write + + + ENIRQHOSTDISCON + no description available + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + no description available + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + no description available + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + no description available + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + no description available + 6 + 1 + read-write + + + ENOTGIDDETECT + no description available + 7 + 1 + read-write + + + RESUMEIRQSTICKY + no description available + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + no description available + 9 + 1 + read-write + + + RESUME_IRQ + no description available + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + no description available + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + no description available + 12 + 1 + read-write + + + DATA_ON_LRADC + no description available + 13 + 1 + read-write + + + ENUTMILEVEL2 + no description available + 14 + 1 + read-write + + + ENUTMILEVEL3 + no description available + 15 + 1 + read-write + + + ENIRQWAKEUP + no description available + 16 + 1 + read-write + + + WAKEUP_IRQ + no description available + 17 + 1 + read-write + + + RSVD0 + no description available + 18 + 1 + read-only + + + ENAUTOCLR_CLKGATE + no description available + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + no description available + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + no description available + 21 + 1 + read-write + + + ENIDCHG_WKUP + no description available + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + no description available + 23 + 1 + read-write + + + FSDLL_RST_EN + no description available + 24 + 1 + read-write + + + RSVD1 + no description available + 25 + 2 + read-only + + + OTG_ID_VALUE + no description available + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + no description available + 28 + 1 + read-write + + + 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DEVPLUGIN_IRQ + no description available + 12 + 1 + read-write + + + DATA_ON_LRADC + no description available + 13 + 1 + read-write + + + ENUTMILEVEL2 + no description available + 14 + 1 + read-write + + + ENUTMILEVEL3 + no description available + 15 + 1 + read-write + + + ENIRQWAKEUP + no description available + 16 + 1 + read-write + + + WAKEUP_IRQ + no description available + 17 + 1 + read-write + + + RSVD0 + no description available + 18 + 1 + read-only + + + ENAUTOCLR_CLKGATE + no description available + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + no description available + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + no description available + 21 + 1 + read-write + + + ENIDCHG_WKUP + no description available + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + no description available + 23 + 1 + read-write + + + FSDLL_RST_EN + no description available + 24 + 1 + read-write + + + RSVD1 + no description available + 25 + 2 + read-only + + + OTG_ID_VALUE + no description available + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + no description available + 28 + 1 + read-write + + + UTMI_SUSPENDM + no description available + 29 + 1 + read-only + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + no description available + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + no description available + 1 + 1 + read-write + + + ENIRQHOSTDISCON + no description available + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + no description available + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + no description available + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + no description available + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + no description available + 6 + 1 + read-write + + + ENOTGIDDETECT + no description available + 7 + 1 + read-write + + + RESUMEIRQSTICKY + no description available + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + no description available + 9 + 1 + read-write + + + RESUME_IRQ + no description available + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + no description available + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + no description available + 12 + 1 + read-write + + + DATA_ON_LRADC + no description available + 13 + 1 + read-write + + + ENUTMILEVEL2 + no description available + 14 + 1 + read-write + + + ENUTMILEVEL3 + no description available + 15 + 1 + read-write + + + ENIRQWAKEUP + no description available + 16 + 1 + read-write + + + WAKEUP_IRQ + no description available + 17 + 1 + read-write + + + RSVD0 + no description available + 18 + 1 + read-only + + + ENAUTOCLR_CLKGATE + no description available + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + no description available + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + no description available + 21 + 1 + read-write + + + ENIDCHG_WKUP + no description available + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + no description available + 23 + 1 + read-write + + + FSDLL_RST_EN + no description available + 24 + 1 + read-write + + + RSVD1 + no description available + 25 + 2 + read-only + + + OTG_ID_VALUE + no description available + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + no description available + 28 + 1 + read-write + + + UTMI_SUSPENDM + no description available + 29 + 1 + read-only + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + no description available + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + no description available + 1 + 1 + read-write + + + ENIRQHOSTDISCON + no description available + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + no description available + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + no description available + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + no description available + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + no description available + 6 + 1 + read-write + + + ENOTGIDDETECT + no description available + 7 + 1 + read-write + + + RESUMEIRQSTICKY + no description available + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + no description available + 9 + 1 + read-write + + + RESUME_IRQ + no description available + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + no description available + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + no description available + 12 + 1 + read-write + + + DATA_ON_LRADC + no description available + 13 + 1 + read-write + + + ENUTMILEVEL2 + no description available + 14 + 1 + read-write + + + ENUTMILEVEL3 + no description available + 15 + 1 + read-write + + + ENIRQWAKEUP + no description available + 16 + 1 + read-write + + + WAKEUP_IRQ + no description available + 17 + 1 + read-write + + + RSVD0 + no description available + 18 + 1 + read-only + + + ENAUTOCLR_CLKGATE + no description available + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + no description available + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + no description available + 21 + 1 + read-write + + + ENIDCHG_WKUP + no description available + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + no description available + 23 + 1 + read-write + + + FSDLL_RST_EN + no description available + 24 + 1 + read-write + + + RSVD1 + no description available + 25 + 2 + read-only + + + OTG_ID_VALUE + no description available + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + no description available + 28 + 1 + read-write + + + UTMI_SUSPENDM + no description available + 29 + 1 + read-only + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + no description available + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + no description available + 1 + 1 + read-write + + + ENIRQHOSTDISCON + no description available + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + no description available + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + no description available + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + no description available + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + no description available + 6 + 1 + read-write + + + ENOTGIDDETECT + no description available + 7 + 1 + read-write + + + RESUMEIRQSTICKY + no description available + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + no description available + 9 + 1 + read-write + + + RESUME_IRQ + no description available + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + no description available + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + no description available + 12 + 1 + read-write + + + DATA_ON_LRADC + no description available + 13 + 1 + read-write + + + ENUTMILEVEL2 + no description available + 14 + 1 + read-write + + + ENUTMILEVEL3 + no description available + 15 + 1 + read-write + + + ENIRQWAKEUP + no description available + 16 + 1 + read-write + + + WAKEUP_IRQ + no description available + 17 + 1 + read-write + + + RSVD0 + no description available + 18 + 1 + read-only + + + ENAUTOCLR_CLKGATE + no description available + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + no description available + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + no description available + 21 + 1 + read-write + + + ENIDCHG_WKUP + no description available + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + no description available + 23 + 1 + read-write + + + FSDLL_RST_EN + no description available + 24 + 1 + read-write + + + RSVD1 + no description available + 25 + 2 + read-only + + + OTG_ID_VALUE + no description available + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + no description available + 28 + 1 + read-write + + + UTMI_SUSPENDM + no description available + 29 + 1 + read-only + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + no description available + 3 + 1 + read-only + + + RSVD1 + no description available + 4 + 2 + read-only + + + DEVPLUGIN_STATUS + no description available + 6 + 1 + read-only + + + RSVD2 + no description available + 7 + 1 + read-only + + + OTGID_STATUS + no description available + 8 + 1 + read-write + + + RSVD3 + no description available + 9 + 1 + read-only + + + RESUME_STATUS + no description available + 10 + 1 + read-only + + + RSVD4 + no description available + 11 + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + no description available + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + no description available + 1 + 1 + read-write + + + HSTPULLDOWN + no description available + 2 + 2 + read-write + + + ENHSTPULLDOWN + no description available + 4 + 2 + read-write + + + RSVD0 + no description available + 6 + 2 + read-only + + + TX2RXCOUNT + no description available + 8 + 4 + read-write + + + ENTX2RXCOUNT + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + ENSQUELCHRESET + no description available + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + no description available + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + RSVD3 + no description available + 31 + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + no description available + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + no description available + 1 + 1 + read-write + + + HSTPULLDOWN + no description available + 2 + 2 + read-write + + + ENHSTPULLDOWN + no description available + 4 + 2 + read-write + + + RSVD0 + no description available + 6 + 2 + read-only + + + TX2RXCOUNT + no description available + 8 + 4 + read-write + + + ENTX2RXCOUNT + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + ENSQUELCHRESET + no description available + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + no description available + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + RSVD3 + no description available + 31 + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + no description available + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + no description available + 1 + 1 + read-write + + + HSTPULLDOWN + no description available + 2 + 2 + read-write + + + ENHSTPULLDOWN + no description available + 4 + 2 + read-write + + + RSVD0 + no description available + 6 + 2 + read-only + + + TX2RXCOUNT + no description available + 8 + 4 + read-write + + + ENTX2RXCOUNT + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + ENSQUELCHRESET + no description available + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + no description available + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + RSVD3 + no description available + 31 + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + no description available + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + no description available + 1 + 1 + read-write + + + HSTPULLDOWN + no description available + 2 + 2 + read-write + + + ENHSTPULLDOWN + no description available + 4 + 2 + read-write + + + RSVD0 + no description available + 6 + 2 + read-only + + + TX2RXCOUNT + no description available + 8 + 4 + read-write + + + ENTX2RXCOUNT + no description available + 12 + 1 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + ENSQUELCHRESET + no description available + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + no description available + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + no description available + 29 + 1 + read-write + + + CLKGATE + no description available + 30 + 1 + read-write + + + RSVD3 + no description available + 31 + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + no description available + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + no description available + 16 + 10 + read-only + + + SQUELCH_COUNT + no description available + 26 + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 13 + read-write + + + ENTAILADJVD + no description available + 13 + 2 + read-write + + + RSVD1 + no description available + 15 + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 13 + read-write + + + ENTAILADJVD + no description available + 13 + 2 + read-write + + + RSVD1 + no description available + 15 + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 13 + read-write + + + ENTAILADJVD + no description available + 13 + 2 + read-write + + + RSVD1 + no description available + 15 + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 13 + read-write + + + ENTAILADJVD + no description available + 13 + 2 + read-write + + + RSVD1 + no description available + 15 + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4020000 + 0xFFFFFFFF + + + STEP + no description available + 0 + 16 + read-only + + + MINOR + no description available + 16 + 8 + read-only + + + MAJOR + no description available + 24 + 8 + read-only + + + + + + + SNVS + SNVS + SNVS_ + 0x20CC000 + + 0 + 0xC00 + registers + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 1 + read-write + + + SRTC_SL + no description available + 2 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + LPCALB_SL + no description available + 3 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + MC_SL + no description available + 4 + 1 + read-write + + + 0 + Write access (increment) is allowed + #0 + + + 1 + Write access (increment) is not allowed + #1 + + + + + GPR_SL + no description available + 5 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-write + + + LPTDCR_SL + no description available + 8 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + HPSVCR_L + no description available + 16 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + HPSICR_L + no description available + 17 + 1 + read-write + + + 0 + Write access is allowed + #0 + + + 1 + Write access is not allowed + #1 + + + + + RESERVED + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 1 + read-only + + + LP_SWR + no description available + 4 + 1 + write-only + + + 0 + No Action + #0 + + + 1 + Reset LP section + #1 + + + + + LP_SWR_DIS + no description available + 5 + 1 + read-write + + + 0 + LP software reset is enabled + #0 + + + 1 + LP software reset is disabled + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + RESERVED + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 2 + read-write + + + RESERVED + no description available + 13 + 1 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + RESERVED + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-write + + + RESERVED + no description available + 18 + 1 + read-write + + + RESERVED + no description available + 19 + 1 + read-write + + + RESERVED + no description available + 20 + 11 + read-only + + + NPSWA_EN + no description available + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + no description available + 0 + 1 + read-write + + + 0 + RTC is disabled + #0 + + + 1 + RTC is enabled + #1 + + + + + HPTA_EN + no description available + 1 + 1 + read-write + + + 0 + HP Time Alarm Interrupt is disabled + #0 + + + 1 + HP Time Alarm Interrupt is enabled + #1 + + + + + RESERVED + no description available + 2 + 1 + read-only + + + PI_EN + no description available + 3 + 1 + read-write + + + 0 + HP Periodic Interrupt is disabled + #0 + + + 1 + HP Periodic Interrupt is enabled + #1 + + + + + PI_FREQ + no description available + 4 + 4 + read-write + + + 0000 + - bit 0 of the RTC is selected as a source of the periodic interrupt + #0000 + + + 0001 + - bit 1 of the RTC is selected as a source of the periodic interrupt + #0001 + + + 0010 + - bit 2 of the RTC is selected as a source of the periodic interrupt + #0010 + + + 0011 + - bit 3 of the RTC is selected as a source of the periodic interrupt + #0011 + + + 0100 + - bit 4 of the RTC is selected as a source of the periodic interrupt + #0100 + + + 0101 + - bit 5 of the RTC is selected as a source of the periodic interrupt + #0101 + + + 0110 + - bit 6 of the RTC is selected as a source of the periodic interrupt + #0110 + + + 0111 + - bit 7 of the RTC is selected as a source of the periodic interrupt + #0111 + + + 1000 + - bit 8 of the RTC is selected as a source of the periodic interrupt + #1000 + + + 1001 + - bit 9 of the RTC is selected as a source of the periodic interrupt + #1001 + + + 1010 + - bit 10 of the RTC is selected as a source of the periodic interrupt + #1010 + + + 1011 + - bit 11 of the RTC is selected as a source of the periodic interrupt + #1011 + + + 1100 + - bit 12 of the RTC is selected as a source of the periodic interrupt + #1100 + + + 1101 + - bit 13 of the RTC is selected as a source of the periodic interrupt + #1101 + + + 1110 + - bit 14 of the RTC is selected as a source of the periodic interrupt + #1110 + + + 1111 + - bit 15 of the RTC is selected as a source of the periodic interrupt + #1111 + + + + + HPCALB_EN + no description available + 8 + 1 + read-write + + + 0 + HP Timer calibration disabled + #0 + + + 1 + HP Timer calibration enabled + #1 + + + + + RESERVED + no description available + 9 + 1 + read-only + + + HPCALB_VAL + no description available + 10 + 5 + read-write + + + 00000 + +0 counts per each 32768 ticks of the counter + #00000 + + + 00001 + +1 counts per each 32768 ticks of the counter + #00001 + + + 00010 + +2 counts per each 32768 ticks of the counter + #00010 + + + 01111 + +15 counts per each 32768 ticks of the counter + #01111 + + + 10000 + -16 counts per each 32768 ticks of the counter + #10000 + + + 10001 + -15 counts per each 32768 ticks of the counter + #10001 + + + 11110 + -2 counts per each 32768 ticks of the counter + #11110 + + + 11111 + -1 counts per each 32768 ticks of the counter + #11111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + HP_TS + no description available + 16 + 1 + read-write + + + 0 + No Action + #0 + + + 1 + Synchronize the HP Time Counter to the LP Time Counter + #1 + + + + + RESERVED + no description available + 17 + 15 + read-only + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + HPTA + no description available + 0 + 1 + read-write + + + 0 + No time alarm interrupt occurred. + #0 + + + 1 + A time alarm interrupt occurred. + #1 + + + + + PI + no description available + 1 + 1 + read-write + + + 0 + No periodic interrupt occurred. + #0 + + + 1 + A periodic interrupt occurred. + #1 + + + + + RESERVED + no description available + 2 + 3 + read-only + + + RESERVED + no description available + 5 + 1 + read-only + + + BTN + no description available + 6 + 1 + read-only + + + BI + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 4 + read-write + + + RESERVED + no description available + 12 + 3 + read-write + + + RESERVED + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-write + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + no description available + 0 + 15 + read-write + + + RESERVED + no description available + 15 + 17 + read-only + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + no description available + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + no description available + 0 + 15 + read-write + + + RESERVED + no description available + 15 + 17 + read-only + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA + no description available + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 1 + read-write + + + SRTC_HL + no description available + 2 + 1 + read-write + + + 0 + Write access is allowed. + #0 + + + 1 + Write access is not allowed. + #1 + + + + + LPCALB_HL + no description available + 3 + 1 + read-write + + + 0 + Write access is allowed. + #0 + + + 1 + Write access is not allowed. + #1 + + + + + MC_HL + no description available + 4 + 1 + read-write + + + 0 + Write access (increment) is allowed. + #0 + + + 1 + Write access (increment) is not allowed. + #1 + + + + + GPR_HL + no description available + 5 + 1 + read-write + + + 0 + Write access is allowed. + #0 + + + 1 + Write access is not allowed. + #1 + + + + + RESERVED + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + RESERVED + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 22 + read-only + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC_ENV + no description available + 0 + 1 + read-write + + + 0 + SRTC is disabled or invalid. + #0 + + + 1 + SRTC is enabled and valid. + #1 + + + + + LPTA_EN + no description available + 1 + 1 + read-write + + + 0 + LP time alarm interrupt is disabled. + #0 + + + 1 + LP time alarm interrupt is enabled. + #1 + + + + + MC_ENV + no description available + 2 + 1 + read-write + + + 0 + MC is disabled or invalid. + #0 + + + 1 + MC is enabled and valid. + #1 + + + + + LPWUI_EN + no description available + 3 + 1 + read-write + + + SRTC_INV_EN + no description available + 4 + 1 + read-write + + + 0 + SRTC stays valid in the case of security violation. + #0 + + + 1 + SRTC is invalidated in the case of security violation. + #1 + + + + + DP_EN + no description available + 5 + 1 + read-write + + + 0 + Smart PMIC enabled. + #0 + + + 1 + Dumb PMIC enabled. + #1 + + + + + TOP + no description available + 6 + 1 + read-write + + + 0 + Leave system power on. + #0 + + + 1 + Turn off system power. + #1 + + + + + PWR_GLITCH_EN + no description available + 7 + 1 + read-write + + + LPCALB_EN + no description available + 8 + 1 + read-write + + + 0 + SRTC Time calibration is disabled. + #0 + + + 1 + SRTC Time calibration is enabled. + #1 + + + + + RESERVED + no description available + 9 + 1 + read-only + + + LPCALB_VAL + no description available + 10 + 5 + read-write + + + 00000 + +0 counts per each 32768 ticks of the counter clock + #00000 + + + 00001 + +1 counts per each 32768 ticks of the counter clock + #00001 + + + 00010 + +2 counts per each 32768 ticks of the counter clock + #00010 + + + 01111 + +15 counts per each 32768 ticks of the counter clock + #01111 + + + 10000 + -16 counts per each 32768 ticks of the counter clock + #10000 + + + 10001 + -15 counts per each 32768 ticks of the counter clock + #10001 + + + 11110 + -2 counts per each 32768 ticks of the counter clock + #11110 + + + 11111 + -1 counts per each 32768 ticks of the counter clock + #11111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + BTN_PRESS_TIME + no description available + 16 + 2 + read-write + + + DEBOUNCE + no description available + 18 + 2 + read-write + + + ON_TIME + no description available + 20 + 2 + read-write + + + PK_EN + no description available + 22 + 1 + read-write + + + PK_OVERRIDE + no description available + 23 + 1 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + no description available + 0 + 1 + read-write + + + 0 + No time alarm interrupt occurred. + #0 + + + 1 + A time alarm interrupt occurred. + #1 + + + + + SRTCR + no description available + 1 + 1 + read-write + + + 0 + SRTC has not reached its maximum value. + #0 + + + 1 + SRTC has reached its maximum value. + #1 + + + + + MCR + no description available + 2 + 1 + read-write + + + 0 + MC has not reached its maximum value. + #0 + + + 1 + MC has reached its maximum value. + #1 + + + + + RESERVED + no description available + 3 + 1 + read-write + + + RESERVED + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + RESERVED + no description available + 16 + 1 + read-write + + + EO + no description available + 17 + 1 + read-write + + + 0 + Emergency off was not detected. + #0 + + + 1 + Emergency off was detected. + #1 + + + + + SPO + no description available + 18 + 1 + read-write + + + 0 + Emergency Off was not detected. + #0 + + + 1 + Emergency Off was detected.. + #1 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + RESERVED + no description available + 20 + 10 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-write + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + no description available + 0 + 15 + read-write + + + RESERVED + no description available + 15 + 17 + read-only + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + no description available + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + no description available + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + no description available + 0 + 16 + read-write + + + MC_ERA_BITS + no description available + 16 + 16 + read-write + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MON_COUNTER + no description available + 0 + 32 + read-write + + + + + LPGPR + SNVS_LP General Purpose Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + no description available + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0100 + 0xFFFFFFFF + + + MINOR_REV + no description available + 0 + 8 + read-only + + + MAJOR_REV + no description available + 8 + 8 + read-only + + + IP_ID + no description available + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + no description available + 0 + 8 + read-only + + + ECO_REV + no description available + 8 + 8 + read-only + + + INTG_OPT + no description available + 16 + 8 + read-only + + + IP_ERA + Era of the IP design + 24 + 8 + read-only + + + + + + + EPIT1 + EPIT + EPIT + EPIT1_ + 0x20D0000 + + 0 + 0x14 + registers + + + + CR + Control register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + EPIT is disabled + #0 + + + 1 + EPIT is enabled + #1 + + + + + ENMOD + no description available + 1 + 1 + read-write + + + 0 + Counter starts counting from the value it had when it was disabled. + #0 + + + 1 + Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) + #1 + + + + + OCIEN + no description available + 2 + 1 + read-write + + + 0 + Compare interrupt disabled + #0 + + + 1 + Compare interrupt enabled + #1 + + + + + RLD + no description available + 3 + 1 + read-write + + + 0 + When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode) + #0 + + + 1 + When the counter reaches zero it reloads from the modulus register (set-and-forget mode) + #1 + + + + + PRESCALAR + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2... + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + SWR + no description available + 16 + 1 + read-write + + + 0 + EPIT is out of reset + #0 + + + 1 + EPIT is undergoing reset + #1 + + + + + IOVW + no description available + 17 + 1 + read-write + + + 0 + Write to load register does not result in counter value being overwritten. + #0 + + + 1 + Write to load register results in immediate overwriting of counter value. + #1 + + + + + DBGEN + no description available + 18 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 19 + 1 + read-write + + + 0 + EPIT is disabled in wait mode + #0 + + + 1 + EPIT is enabled in wait mode + #1 + + + + + RESERVED + no description available + 20 + 1 + read-only + + + STOPEN + no description available + 21 + 1 + read-write + + + 0 + EPIT is disabled in stop mode + #0 + + + 1 + EPIT is enabled in stop mode + #1 + + + + + OM + no description available + 22 + 2 + read-write + + + 00 + EPIT output is disconnected from pad + #00 + + + 01 + Toggle output pin + #01 + + + 10 + Clear output pin + #10 + + + 11 + Set output pin + #11 + + + + + CLKSRC + no description available + 24 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + Peripheral clock + #01 + + + 10 + High-frequency reference clock + #10 + + + 11 + Low-frequency reference clock + #11 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + SR + Status register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCIF + no description available + 0 + 1 + read-write + + + 0 + Compare event has not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + LR + Load register + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + LOAD + no description available + 0 + 32 + read-write + + + + + CMPR + Compare register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + no description available + 0 + 32 + read-write + + + + + CNR + Counter register + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + COUNT + no description available + 0 + 32 + read-only + + + + + + + EPIT2 + EPIT + EPIT + EPIT2_ + 0x20D4000 + + 0 + 0x14 + registers + + + + CR + Control register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + 0 + EPIT is disabled + #0 + + + 1 + EPIT is enabled + #1 + + + + + ENMOD + no description available + 1 + 1 + read-write + + + 0 + Counter starts counting from the value it had when it was disabled. + #0 + + + 1 + Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) + #1 + + + + + OCIEN + no description available + 2 + 1 + read-write + + + 0 + Compare interrupt disabled + #0 + + + 1 + Compare interrupt enabled + #1 + + + + + RLD + no description available + 3 + 1 + read-write + + + 0 + When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode) + #0 + + + 1 + When the counter reaches zero it reloads from the modulus register (set-and-forget mode) + #1 + + + + + PRESCALAR + no description available + 4 + 12 + read-write + + + 0 + Divide by 1 + #0 + + + 1 + Divide by 2... + #1 + + + 111111111111 + Divide by 4096 + #111111111111 + + + + + SWR + no description available + 16 + 1 + read-write + + + 0 + EPIT is out of reset + #0 + + + 1 + EPIT is undergoing reset + #1 + + + + + IOVW + no description available + 17 + 1 + read-write + + + 0 + Write to load register does not result in counter value being overwritten. + #0 + + + 1 + Write to load register results in immediate overwriting of counter value. + #1 + + + + + DBGEN + no description available + 18 + 1 + read-write + + + 0 + Inactive in debug mode + #0 + + + 1 + Active in debug mode + #1 + + + + + WAITEN + no description available + 19 + 1 + read-write + + + 0 + EPIT is disabled in wait mode + #0 + + + 1 + EPIT is enabled in wait mode + #1 + + + + + RESERVED + no description available + 20 + 1 + read-only + + + STOPEN + no description available + 21 + 1 + read-write + + + 0 + EPIT is disabled in stop mode + #0 + + + 1 + EPIT is enabled in stop mode + #1 + + + + + OM + no description available + 22 + 2 + read-write + + + 00 + EPIT output is disconnected from pad + #00 + + + 01 + Toggle output pin + #01 + + + 10 + Clear output pin + #10 + + + 11 + Set output pin + #11 + + + + + CLKSRC + no description available + 24 + 2 + read-write + + + 00 + Clock is off + #00 + + + 01 + Peripheral clock + #01 + + + 10 + High-frequency reference clock + #10 + + + 11 + Low-frequency reference clock + #11 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + SR + Status register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + OCIF + no description available + 0 + 1 + read-write + + + 0 + Compare event has not occurred + #0 + + + 1 + Compare event occurred + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + LR + Load register + 0x8 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + LOAD + no description available + 0 + 32 + read-write + + + + + CMPR + Compare register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + COMPARE + no description available + 0 + 32 + read-write + + + + + CNR + Counter register + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + COUNT + no description available + 0 + 32 + read-only + + + + + + + SRC + SRC + SRC_ + 0x20D8000 + + 0 + 0x48 + registers + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0x521 + 0xFFFFFFFF + + + warm_reset_enable + no description available + 0 + 1 + read-write + + + 0 + WARM reset disabled + #0 + + + 1 + WARM reset enabled + #1 + + + + + sw_gpu_rst + no description available + 1 + 1 + read-write + + + 0 + do not assert GPU reset + #0 + + + 1 + assert GPU reset + #1 + + + + + sw_vpu_rst + no description available + 2 + 1 + read-write + + + 0 + do not assert VPU reset + #0 + + + 1 + assert VPU reset + #1 + + + + + sw_ipu1_rst + no description available + 3 + 1 + read-write + + + 0 + do not assert IPU1 reset + #0 + + + 1 + assert IPU1 reset + #1 + + + + + sw_open_vg_rst + no description available + 4 + 1 + read-write + + + 0 + do not assert open_vg reset + #0 + + + 1 + assert open_vg reset + #1 + + + + + warm_rst_bypass_count + no description available + 5 + 2 + read-write + + + 00 + Counter not to be used - system will wait until MMDC acknowledge until it is asserted. + #00 + + + 01 + Wait 16 XTALI cycles before changing WARM reset to a COLD reset. + #01 + + + 10 + Wait 32 XTALI cycles before changing WARM reset to a COLD reset. + #10 + + + 11 + Wait 64 XTALI cycles before changing WARM reset to a COLD reset + #11 + + + + + mask_wdog_rst + no description available + 7 + 4 + read-write + + + 0101 + wdog_rst_b is masked + #0101 + + + 1010 + wdog_rst_b is not masked (default) + #1010 + + + + + eim_rst + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 1 + read-only + + + core0_rst + no description available + 13 + 1 + read-write + + + 0 + do not assert core0 reset + #0 + + + 1 + assert core0 reset + #1 + + + + + core1_rst + no description available + 14 + 1 + read-write + + + 0 + do not assert core1 reset + #0 + + + 1 + assert core1 reset + #1 + + + + + RESERVED + no description available + 15 + 2 + read-only + + + core0_dbg_rst + no description available + 17 + 1 + read-write + + + 0 + do not assert core0 debug reset + #0 + + + 1 + assert core0 debug reset + #1 + + + + + core1_dbg_rst + no description available + 18 + 1 + read-write + + + 0 + do not assert core1 debug reset + #0 + + + 1 + assert core1 debug reset + #1 + + + + + RESERVED + no description available + 19 + 2 + read-only + + + cores_dbg_rst + no description available + 21 + 1 + read-write + + + 0 + do not assert arm platform debug reset + #0 + + + 1 + assert arm platform debug reset + #1 + + + + + core1_enable + no description available + 22 + 1 + read-write + + + 0 + core1 is disabled + #0 + + + 1 + core1 is enabled + #1 + + + + + RESERVED + no description available + 23 + 2 + read-only + + + dbg_rst_msk_pg + no description available + 25 + 1 + read-write + + + 0 + do not mask core debug resets (debug resets will be asserted after power gating event) + #0 + + + 1 + mask core debug resets (debug resets won't be asserted after power gating event) + #1 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + no description available + 0 + 8 + read-only + + + BOOT_CFG2 + no description available + 8 + 8 + read-only + + + BOOT_CFG3 + no description available + 16 + 8 + read-only + + + BOOT_CFG4 + no description available + 24 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + no description available + 0 + 1 + read-write + + + 0 + Reset is not a result of ipp_reset_b pin. + #0 + + + 1 + Reset is a result of ipp_reset_b pin. + #1 + + + + + RESERVED + no description available + 1 + 1 + read-only + + + csu_reset_b + no description available + 2 + 1 + read-write + + + 0 + Reset is not a result of the csu_reset_b event. + #0 + + + 1 + Reset is a result of the csu_reset_b event. + #1 + + + + + ipp_user_reset_b + no description available + 3 + 1 + read-write + + + 0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + #0 + + + 1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + #1 + + + + + wdog_rst_b + no description available + 4 + 1 + read-write + + + 0 + Reset is not a result of the watchdog time-out event. + #0 + + + 1 + Reset is a result of the watchdog time-out event. + #1 + + + + + jtag_rst_b + no description available + 5 + 1 + read-write + + + 0 + Reset is not a result of HIGH-Z reset from JTAG. + #0 + + + 1 + Reset is a result of HIGH-Z reset from JTAG. + #1 + + + + + jtag_sw_rst + no description available + 6 + 1 + read-write + + + 0 + Reset is not a result of software reset from JTAG. + #0 + + + 1 + Reset is a result of software reset from JTAG. + #1 + + + + + RESERVED + no description available + 7 + 9 + read-only + + + warm_boot + no description available + 16 + 1 + read-write + + + 0 + WARM boot process not initiated by software. + #0 + + + 1 + WARM boot initiated by software. + #1 + + + + + RESERVED + no description available + 17 + 15 + read-only + + + + + SISR + SRC Interrupt Status Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + gpu_passed_reset + no description available + 0 + 1 + read-only + + + 0 + interrupt generated not due to GPU passed reset + #0 + + + 1 + interrupt generated due to GPU passed reset + #1 + + + + + vpu_passed_reset + no description available + 1 + 1 + read-only + + + 0 + interrupt generated not due to VPU passed reset + #0 + + + 1 + interrupt generated due to VPU passed reset + #1 + + + + + ipu1_passed_reset + no description available + 2 + 1 + read-only + + + 0 + interrupt generated not due to ipu passed reset + #0 + + + 1 + interrupt generated due to ipu passed reset + #1 + + + + + open_vg_passed_reset + no description available + 3 + 1 + read-only + + + 0 + interrupt generated not due to open_vg passed reset + #0 + + + 1 + interrupt generated due to open_vg passed reset + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + core0_wdog_rst_req + no description available + 5 + 1 + read-only + + + core1_wdog_rst_req + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 2 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + SIMR + SRC Interrupt Mask Register + 0x18 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + mask_gpu_passed_reset + no description available + 0 + 1 + read-write + + + 0 + do not mask interrupt due to GPU passed reset - interrupt will be created + #0 + + + 1 + mask interrupt due to GPU passed reset + #1 + + + + + mask_vpu_passed_reset + no description available + 1 + 1 + read-write + + + 0 + do not mask interrupt due to VPU passed reset - interrupt will be created + #0 + + + 1 + mask interrupt due to VPU passed reset + #1 + + + + + mask_ipu_passed_reset + no description available + 2 + 1 + read-write + + + 0 + do not mask interrupt due to ipu passed reset - interrupt will be created + #0 + + + 1 + mask interrupt due to ipu passed reset + #1 + + + + + mask_open_vg_passed_reset + no description available + 3 + 1 + read-write + + + 0 + do not mask interrupt due to open_vg passed reset - interrupt will be created + #0 + + + 1 + mask interrupt due to open_vg passed reset + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + no description available + 0 + 2 + read-only + + + RESERVED + no description available + 2 + 1 + read-only + + + DIR_BT_DIS + no description available + 3 + 1 + read-only + + + BT_FUSE_SEL + no description available + 4 + 1 + read-only + + + RESERVED + no description available + 5 + 19 + read-only + + + BMOD + no description available + 24 + 2 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + no description available + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + no description available + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY1 + no description available + 0 + 32 + read-write + + + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG1 + no description available + 0 + 32 + read-write + + + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-write + + + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-write + + + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-write + + + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-write + + + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 25 + read-write + + + core1_ERROR_STATUS + no description available + 25 + 1 + read-only + + + RESERVED + no description available + 26 + 6 + read-write + + + + + + + GPC + GPC + GPC_ + 0x20DC000 + + 0 + 0x28 + registers + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x100000 + 0xFFFFFFFF + + + gpu_vpu_pdn_req + no description available + 0 + 1 + read-write + + + 1 + Request Power Down sequence to start for GPU/VPU + #1 + + + 0 + no request + #0 + + + + + gpu_vpu_pup_req + no description available + 1 + 1 + read-write + + + 1 + Request Power Up sequence to start for GPU/VPU + #1 + + + 0 + no request + #0 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + RESERVED + no description available + 4 + 1 + read-only + + + RESERVED + no description available + 5 + 1 + read-only + + + RESERVED + no description available + 6 + 10 + read-only + + + DVFS0CR + no description available + 16 + 1 + read-only + + + 1 + DVFS0 is requesting for frequency/voltage update + #1 + + + 0 + DVFS0 has no request + #0 + + + + + RESERVED + no description available + 17 + 3 + read-only + + + RESERVED + no description available + 20 + 1 + read-only + + + GPCIRQM + no description available + 21 + 1 + read-write + + + 1 + interrupt/event is masked + #1 + + + 0 + not masked + #0 + + + + + RESERVED + no description available + 22 + 1 + read-only + + + RESERVED + no description available + 23 + 9 + read-only + + + + + PGR + GPC Power Gating Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 29 + read-only + + + DRCIC + no description available + 29 + 2 + read-write + + + 00 + ccm_cosr_1_clk_in + #00 + + + 01 + ccm_cosr_2_clk_in + #01 + + + 10 + restricted + #10 + + + 11 + restricted + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + no description available + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + no description available + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + no description available + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + no description available + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + no description available + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + no description available + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + no description available + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + no description available + 0 + 32 + read-only + + + + + + + PGC + PGC + PGC_ + 0x20DC000 + + 0x260 + 0x50 + registers + + + + GPU_CTRL + PGC Control Register + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + no description available + 0 + 1 + read-write + + + 0 + Do not switch off power even if pdn_req is asserted. + #0 + + + 1 + Switch off power when pdn_req is asserted. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + GPU_PUPSCR + Power Up Sequence Control Register + 0x264 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + SW2ISO + no description available + 8 + 6 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + GPU_PDNSCR + Pull Down Sequence Control Register + 0x268 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + ISO2SW + no description available + 8 + 6 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + GPU_SR + Power Gating Controller Status Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + no description available + 0 + 1 + read-write + + + 0 + The target subsystem was not powered down for the previous power-down request. + #0 + + + 1 + The target subsystem was powered down for the previous power-down request. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CPU_CTRL + PGC Control Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + no description available + 0 + 1 + read-write + + + 0 + Do not switch off power even if pdn_req is asserted. + #0 + + + 1 + Switch off power when pdn_req is asserted. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CPU_PUPSCR + Power Up Sequence Control Register + 0x2A4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + SW2ISO + no description available + 8 + 6 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + CPU_PDNSCR + Pull Down Sequence Control Register + 0x2A8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + ISO2SW + no description available + 8 + 6 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + CPU_SR + Power Gating Controller Status Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + no description available + 0 + 1 + read-write + + + 0 + The target subsystem was not powered down for the previous power-down request. + #0 + + + 1 + The target subsystem was powered down for the previous power-down request. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + + + DVFSC + DVFSC + DVFSC_ + 0x20DC180 + + 0 + 0x44 + registers + + + + THRS + DVFS Thresholds + 0 + 32 + read-write + 0xFAF003E + 0xFFFFFFFF + + + PNCTHR + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + DWTHR + no description available + 16 + 6 + read-write + + + UPTHR + no description available + 22 + 6 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + COUN + DVFS Counters thresholds + 0x4 + 32 + read-write + 0x70020 + 0xFFFFFFFF + + + UPCNT + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + DN_CNT + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + SIG1 + DVFS general purpose bits weight + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + WSW6 + no description available + 2 + 3 + read-write + + + WSW7 + no description available + 5 + 3 + read-write + + + WSW8 + no description available + 8 + 3 + read-write + + + WSW9 + no description available + 11 + 3 + read-write + + + WSW10 + no description available + 14 + 3 + read-write + + + WSW11 + no description available + 17 + 3 + read-write + + + WSW12 + no description available + 20 + 3 + read-write + + + WSW13 + no description available + 23 + 3 + read-write + + + WSW14 + no description available + 26 + 3 + read-write + + + WSW15 + no description available + 29 + 3 + read-write + + + + + DVFSSIG0 + DVFS general purpose bits weight + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WSW0 + no description available + 0 + 6 + read-write + + + WSW1 + no description available + 6 + 6 + read-write + + + RESERVED + no description available + 12 + 8 + read-only + + + WSW2 + no description available + 20 + 3 + read-write + + + WSW3 + no description available + 23 + 3 + read-write + + + WSW4 + no description available + 26 + 3 + read-write + + + WSW5 + no description available + 29 + 3 + read-write + + + + + DVFSGPC0 + DVFS general purpose bit 0 weight counter + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC0 + no description available + 0 + 17 + read-write + + + RESERVED + no description available + 17 + 13 + read-only + + + C0ACT + no description available + 30 + 1 + read-only + + + 1 + General Purpose bit0 counter didn't reach value of "0" - the WSW0 is provided to DVFS calculation + #1 + + + 0 + General Purpose bit0 counter reached value of "0" - the instead of WSW0, "0" (zero) is provided to DVFS calculation + #0 + + + + + C0STRT + no description available + 31 + 1 + read-write + + + + + DVFSGPC1 + DVFS general purpose bit 1 weight counter + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPBC1 + no description available + 0 + 17 + read-write + + + RESERVED + no description available + 17 + 13 + read-only + + + C1ACT + no description available + 30 + 1 + read-only + + + 1 + General Purpose bit1 counter didn't reach value of "0" - the WSW1 is provided to DVFS calculation + #1 + + + 0 + General Purpose bit1 counter reached value of "0" - the instead of WSW1, "0" (zero) is provided to DVFS calculation + #0 + + + + + C1STRT + no description available + 31 + 1 + read-write + + + + + DVFSGPBT + DVFS general purpose bits enables + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPB0 + no description available + 0 + 1 + read-write + + + GPB1 + no description available + 1 + 1 + read-write + + + GPB2 + no description available + 2 + 1 + read-write + + + GPB3 + no description available + 3 + 1 + read-write + + + GPB4 + no description available + 4 + 1 + read-write + + + GPB5 + no description available + 5 + 1 + read-write + + + GPB6 + no description available + 6 + 1 + read-write + + + GPB7 + no description available + 7 + 1 + read-write + + + GPB8 + no description available + 8 + 1 + read-write + + + GPB9 + no description available + 9 + 1 + read-write + + + GPB10 + no description available + 10 + 1 + read-write + + + GPB11 + no description available + 11 + 1 + read-write + + + GPB12 + no description available + 12 + 1 + read-write + + + GPB13 + no description available + 13 + 1 + read-write + + + GPB14 + no description available + 14 + 1 + read-write + + + GPB15 + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DVFSEMAC + DVFS EMAC settings + 0x1C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + EMAC + no description available + 0 + 9 + read-write + + + DVFEN0 + no description available + 9 + 1 + read-write + + + 1 + DVFS enabled. + #1 + + + 0 + DVFS disabled. + #0 + + + + + DVFEN1 + no description available + 10 + 1 + read-write + + + 1 + DVFS enabled. + #1 + + + 0 + DVFS disabled. + #0 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + FSVAI0 + no description available + 16 + 2 + read-only + + + 00 + no change + #00 + + + 01 + frequency should be increased. Low priority source for interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #01 + + + 10 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + #10 + + + 11 + frequency should be increased immediately. High priority source of interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #11 + + + + + FSVAI1 + no description available + 18 + 2 + read-only + + + 00 + no change + #00 + + + 01 + frequency should be increased. Low priority source for interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #01 + + + 10 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + #10 + + + 11 + frequency should be increased immediately. High priority source of interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #11 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + WFIM0 + no description available + 24 + 1 + read-write + + + 0 + Wait for interrupt of core 0 isn't masked + #0 + + + 1 + Wait for interrupt of core 0 is masked. + #1 + + + + + WFIM1 + no description available + 25 + 1 + read-write + + + 0 + Wait for interrupt of core 1 isn't masked + #0 + + + 1 + Wait for interrupt of core 1 is masked. + #1 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + CNTR + DVFS Control + 0x20 + 32 + read-write + 0x900000E + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + LTBRSR + no description available + 3 + 2 + read-write + + + 00 + pre_ld_add + #00 + + + 01 + ld_add + #01 + + + 10 + ema_ld + #10 + + + 11 + reserved + #11 + + + + + LTBRSH + no description available + 5 + 1 + read-write + + + 0 + values of [5:2] of the selected input are saving in Load Tracking Buffer + #0 + + + 1 + values of [4:1] of the selected input are saving in Load Tracking Buffer + #1 + + + + + PFUS + no description available + 6 + 3 + read-only + + + 000 + no update + #000 + + + 100 + DVFSPT0 period, previous finished(can be performance level decrease) + #100 + + + 101 + DVFSPT1 period, previous finished(can be EMA-detected performance level) + #101 + + + 110 + DVFSPT2 period, previous finished(can be performance level increase) + #110 + + + 111 + DVFSPT3 period, previous finished (can be EMA-detected performance level) + #111 + + + + + PFUE + no description available + 9 + 1 + read-write + + + 1 + enabled + #1 + + + 0 + disabled + #0 + + + + + RESERVED + no description available + 10 + 1 + read-only + + + DIV_RATIO + no description available + 11 + 6 + read-write + + + MINF + no description available + 17 + 1 + read-write + + + 1 + min frequency reached + #1 + + + 0 + min frequency not reached + #0 + + + + + MAXF + no description available + 18 + 1 + read-write + + + 1 + max frequency reached + #1 + + + 0 + max frequency not reached + #0 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + FSVAI + no description available + 20 + 2 + read-only + + + 00 + no interrupt + #00 + + + 01 + frequency should be increased. Low priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #01 + + + 10 + frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MINF= 1 (lowest frequency). + #10 + + + 11 + frequency should be increased immediately. High priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if MAXF = 1 (highest frequency). + #11 + + + + + FSVAIM + no description available + 22 + 1 + read-write + + + 1 + interrupt is masked. + #1 + + + 0 + interrupt is enabled. + #0 + + + + + PIRQS + no description available + 23 + 1 + read-write + + + 1 + DVFS IRQ source was from pattern + #1 + + + 0 + DVFS IRQ source was not from pattern + #0 + + + + + DVFIS + no description available + 24 + 1 + read-write + + + 1 + MCU interrupt will be generated for DVFS events. + #1 + + + 0 + SDMA interrupt will be generated for DVFS events. + #0 + + + + + LBFL0 + no description available + 25 + 1 + read-write + + + 1 + Load buffer1 is full. + #1 + + + 0 + Load buffer1 is not full. + #0 + + + + + LBFL1 + no description available + 26 + 1 + read-write + + + 1 + Load buffer0 is full. + #1 + + + 0 + Load buffer0 is not full. + #0 + + + + + LBMI + no description available + 27 + 1 + read-write + + + DVFEV + no description available + 28 + 1 + read-write + + + 0 + Do not give an event always. + #0 + + + 1 + Always give event. + #1 + + + + + DIV3CK + no description available + 29 + 3 + read-write + + + + + DVFSLTR0_0 + DVFS Load Tracking Register 0, portion 0 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_0 + no description available + 0 + 4 + read-only + + + LTS0_1 + no description available + 4 + 4 + read-only + + + LTS0_2 + no description available + 8 + 4 + read-only + + + LTS0_3 + no description available + 12 + 4 + read-only + + + LTS0_4 + no description available + 16 + 4 + read-only + + + LTS0_5 + no description available + 20 + 4 + read-only + + + LTS0_6 + no description available + 24 + 4 + read-only + + + LTS0_7 + no description available + 28 + 4 + read-only + + + + + DVFSLTR0_1 + DVFS Load Tracking Register 0, portion 1 + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS0_8 + no description available + 0 + 4 + read-only + + + LTS0_9 + no description available + 4 + 4 + read-only + + + LTS0_10 + no description available + 8 + 4 + read-only + + + LTS0_11 + no description available + 12 + 4 + read-only + + + LTS0_12 + no description available + 16 + 4 + read-only + + + LTS0_13 + no description available + 20 + 4 + read-only + + + LTS0_14 + no description available + 24 + 4 + read-only + + + LTS0_15 + no description available + 28 + 4 + read-only + + + + + DVFSLTR1_0 + DVFS Load Tracking Register 1, portion 0 + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_0 + no description available + 0 + 4 + read-only + + + LTS1_1 + no description available + 4 + 4 + read-only + + + LTS1_2 + no description available + 8 + 4 + read-only + + + LTS1_3 + no description available + 12 + 4 + read-only + + + LTS1_4 + no description available + 16 + 4 + read-only + + + LTS1_5 + no description available + 20 + 4 + read-only + + + LTS1_6 + no description available + 24 + 4 + read-only + + + LTS1_7 + no description available + 28 + 4 + read-only + + + + + DVFSLTR1_1 + DVFS Load Tracking Register 3, portion 1 + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTS1_8 + no description available + 0 + 4 + read-only + + + LTS1_9 + no description available + 4 + 4 + read-only + + + LTS1_10 + no description available + 8 + 4 + read-only + + + LTS1_11 + no description available + 12 + 4 + read-only + + + LTS1_12 + no description available + 16 + 4 + read-only + + + LTS1_13 + no description available + 20 + 4 + read-only + + + LTS1_14 + no description available + 24 + 4 + read-only + + + LTS1_15 + no description available + 28 + 4 + read-only + + + + + DVFSPT0 + DVFS pattern 0 length + 0x34 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN0 + no description available + 0 + 17 + read-write + + + PT0A + no description available + 17 + 1 + read-only + + + 1 + active + #1 + + + 0 + non-active + #0 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + DVFSPT1 + DVFS pattern 1 length + 0x38 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN1 + no description available + 0 + 17 + read-write + + + PT1A + no description available + 17 + 1 + read-only + + + 1 + active + #1 + + + 0 + non-active + #0 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + DVFSPT2 + DVFS pattern 2 length + 0x3C + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN2 + no description available + 0 + 17 + read-write + + + PT2A + no description available + 17 + 1 + read-only + + + 1 + active + #1 + + + 0 + non-active + #0 + + + + + RESERVED + no description available + 18 + 8 + read-only + + + P2THR + no description available + 26 + 6 + read-write + + + + + DVFSPT3 + DVFS pattern 3 length + 0x40 + 32 + read-write + 0x10 + 0xFFFFFFFF + + + FPTN3 + no description available + 0 + 17 + read-write + + + PT3A + no description available + 17 + 1 + read-only + + + 1 + active + #1 + + + 0 + non-active + #0 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + + + IOMUXC + IOMUXC + IOMUXC_ + 0x20E0000 + + 0 + 0x93C + registers + + + + GPR0 + GPR0 + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMAREQ_MUX_SEL0 + no description available + 0 + 1 + read-write + + + 0 + ipu1. + #0 + + + 1 + iomux.sdma_events[0] - External DMA Request from pad DISP0_DAT16 or GPIO_17 + #1 + + + + + DMAREQ_MUX_SEL1 + no description available + 1 + 1 + read-write + + + 0 + ecspi1.ipd_req_cspi_rdma_b + #0 + + + 1 + i2c3.ipi_int_b + #1 + + + + + DMAREQ_MUX_SEL2 + no description available + 2 + 1 + read-write + + + 0 + ecspi1.ipd_req_cspi_tdma_b + #0 + + + 1 + i2c2.ipi_int_b + #1 + + + + + DMAREQ_MUX_SEL3 + no description available + 3 + 1 + read-write + + + 0 + ecspi2.ipd_req_cspi_rdma_b + #0 + + + 1 + i2c1.ipi_int_b + #1 + + + + + DMAREQ_MUX_SEL4 + no description available + 4 + 1 + read-write + + + 0 + ecspi4.ipd_req_cspi_tdma_b + #0 + + + 1 + i2c1.ipi_int_b + #1 + + + + + DMAREQ_MUX_SEL5 + no description available + 5 + 1 + read-write + + + 0 + ecspi4.ipd_req_cspi_rdma_b + #0 + + + 1 + epit2.ipi_int_epit_oc + #1 + + + + + DMAREQ_MUX_SEL6 + no description available + 6 + 1 + read-write + + + 0 + esai. + #0 + + + 1 + i2c3.ipi_int_b + #1 + + + + + DMAREQ_MUX_SEL7 + no description available + 7 + 1 + read-write + + + 0 + spdif.drq0_spdif_b + #0 + + + 1 + iomux.sdma_ext_events[1] - External DMA Request via DISP0_DAT17 or GPIO_18 + #1 + + + + + PCIE_RX0_EQ + no description available + 8 + 3 + read-write + + + RESERVED + no description available + 11 + 3 + read-write + + + TX_CLK2_MUX_SEL + no description available + 14 + 2 + read-write + + + 00 + same source as for asrc.asrck_clock_1 + #00 + + + 01 + same source as for asrc.asrck_clock_2 + #01 + + + 10 + same source as for asrc.asrck_clock_3 + #10 + + + 11 + Reserved + #11 + + + + + CLOCK_1_MUX_SEL + no description available + 16 + 2 + read-write + + + 00 + audmux.amx_output_rxclk_p1 muxed with ssi1.ssi_srck + #00 + + + 01 + audmux.amx_output_rxclk_p1 + #01 + + + 10 + ssi1.ssi_srck + #10 + + + 11 + ssi1.rx_bit_clk + #11 + + + + + CLOCK_9_MUX_SEL + no description available + 18 + 2 + read-write + + + 00 + audmux.amx_output_txclk_p1 muxed with ssi1.ssi_stck + #00 + + + 01 + audmux.amx_output_txclk_p1 + #01 + + + 10 + ssi1.ssi_stck + #10 + + + 11 + ssi1.tx_bit_clk + #11 + + + + + CLOCK_2_MUX_SEL + no description available + 20 + 2 + read-write + + + 00 + audmux.amx_output_rxclk_p2 muxed with ssi2.ssi_srck + #00 + + + 01 + audmux.amx_output_rxclk_p2 + #01 + + + 10 + ssi2.ssi_srck + #10 + + + 11 + ssi2.rx_bit_clk + #11 + + + + + CLOCK_A_MUX_SEL + no description available + 22 + 2 + read-write + + + 00 + audmux.amx_output_txclk_p2 muxed with ssi2.ssi_stck + #00 + + + 01 + audmux.amx_output_txclk_p2 + #01 + + + 10 + ssi2.ssi_stck + #10 + + + 11 + ssi2.tx_bit_clk + #11 + + + + + CLOCK_3_MUX_SEL + no description available + 24 + 2 + read-write + + + 00 + audmux.amx_output_rxclk_p7 muxed with ssi3.ssi_srck + #00 + + + 01 + audmux.amx_output_rxclk_p7 + #01 + + + 10 + ssi3.ssi_srck + #10 + + + 11 + ssi3.rx_bit_clk + #11 + + + + + CLOCK_B_MUX_SEL + no description available + 26 + 2 + read-write + + + 00 + audmux.amx_output_txclk_p7 muxed with ssi3.ssi_stck + #00 + + + 01 + audmux.amx_output_txclk_p7 + #01 + + + 10 + ssi3.ssi_stck + #10 + + + 11 + ssi3.tx_bit_clk + #11 + + + + + CLOCK_0_MUX_SEL + no description available + 28 + 2 + read-write + + + 00 + esai.ipp_ind_sckr muxed with esai.ipp_do_sckr + #00 + + + 01 + esai.ipp_ind_sckr + #01 + + + 10 + esai.ipp_do_sckr + #10 + + + 11 + Reserved + #11 + + + + + CLOCK_8_MUX_SEL + no description available + 30 + 2 + read-write + + + 00 + audmux.amx_output_rxclk_p7 muxed with ssi3.ssi_srck + #00 + + + 01 + audmux.amx_output_rxclk_p7 + #01 + + + 10 + ssi3.ssi_srck + #10 + + + 11 + ssi3.rx_bit_clk + #11 + + + + + + + GPR1 + GPR1 + 0x4 + 32 + read-write + 0x48400005 + 0xFFFFFFFF + + + ACT_CS0 + no description available + 0 + 1 + read-write + + + ADDRS0 + no description available + 1 + 2 + read-write + + + ACT_CS1 + no description available + 3 + 1 + read-write + + + ADDRS1 + no description available + 4 + 2 + read-write + + + ACT_CS2 + no description available + 6 + 1 + read-write + + + ADDRS2 + no description available + 7 + 2 + read-write + + + ACT_CS3 + no description available + 9 + 1 + read-write + + + ADDRS3 + no description available + 10 + 2 + read-write + + + 00 + 32 MByte + #00 + + + 01 + 64 MByte + #01 + + + 10 + 128 MByte + #10 + + + 11 + Reserved + #11 + + + + + GINT + no description available + 12 + 1 + read-write + + + 0 + Global interrupt request is not asserted + #0 + + + 1 + Global interrupt request is asserted + #1 + + + + + RESERVED + no description available + 13 + 1 + read-write + + + 0 + selects ENET_RX_ER + #0 + + + 1 + selects GPIO_1. + #1 + + + + + SYS_INT + no description available + 14 + 1 + read-write + + + 0 + PCIe system interrupt request is not asserted + #0 + + + 1 + PCIe system interrupt request is asserted + #1 + + + + + USB_EXP_MODE + no description available + 15 + 1 + read-write + + + 0 + Exposure mode is disabled. + #0 + + + 1 + Exposure mode is enabled. + #1 + + + + + REF_SSP_EN + no description available + 16 + 1 + read-write + + + 0 + PCIe PHY reference clock is disabled + #0 + + + 1 + PCIe PHY reference clock is enabled + #1 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + TEST_POWERDOWN + no description available + 18 + 1 + read-write + + + 0 + Power down is not requested + #0 + + + 1 + Power down is requested + #1 + + + + + RESERVED + no description available + 19 + 2 + read-write + + + 0 + Gasket is selected + #0 + + + 1 + IOMUX is selected + #1 + + + + + ENET_CLK_SEL + no description available + 21 + 1 + read-write + + + 0 + get enet tx reference clk from pad (external OSC for both external PHY and Internal Controller) + #0 + + + 1 + get enet tx reference clk from internal clock from anatop (loopback through pad), this clock also sent out to external PHY + #1 + + + + + EXC_MON + no description available + 22 + 1 + read-write + + + 0 + OKEY response + #0 + + + 1 + SLVError (default) + #1 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + MIPI_DPI_OFF + no description available + 24 + 1 + read-write + + + 0 + MIPI DPI shutdown request is not set + #0 + + + 1 + MIPI DPI shutdown request is set + #1 + + + + + MIPI_COLOR_SW + no description available + 25 + 1 + read-write + + + 0 + MIPI color switch request is not set + #0 + + + 1 + MIPI color switch request is set + #1 + + + + + APP_REQ_ENTR_L1 + no description available + 26 + 1 + read-write + + + 0 + PCIe application request is not set + #0 + + + 1 + PCIe application request is set + #1 + + + + + APP_READY_ENTR_L23 + no description available + 27 + 1 + read-write + + + 0 + PCIe application is not ready to enter L23 + #0 + + + 1 + PCIe application is ready to enter L23 + #1 + + + + + APP_REQ_EXIT_L1 + no description available + 28 + 1 + read-write + + + 0 + PCIe application request is not set + #0 + + + 1 + PCIe application request is set + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + APP_CLK_REQ_N + no description available + 30 + 1 + read-write + + + CFG_L1_CLK_REMOVAL_EN + no description available + 31 + 1 + read-write + + + + + GPR2 + GPR2 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CH0_MODE + no description available + 0 + 2 + read-write + + + 00 + Channel disabled. + #00 + + + 01 + Channel enabled, routed to DI0 + #01 + + + 10 + Channel disabled. + #10 + + + 11 + Channel enabled, routed to DI1. + #11 + + + + + CH1_MODE + no description available + 2 + 2 + read-write + + + 00 + Channel disabled. + #00 + + + 01 + Channel enabled, routed to DI0 + #01 + + + 10 + Channel disabled. + #10 + + + 11 + Channel enabled, routed to DI1. + #11 + + + + + SPLIT_MODE_EN + no description available + 4 + 1 + read-write + + + 0 + Split mode is disabled. + #0 + + + 1 + Split mode is enabled. In this mode both channels should be enabled and working with the same DI (ch0_mode and ch1_mode should both be either '01' or '11') + #1 + + + + + DATA_WIDTH_CH0 + no description available + 5 + 1 + read-write + + + 0 + Data width is 18 bits wide (lvds0_tx3 is not used) + #0 + + + 1 + Data width is 24 bits wide. + #1 + + + + + BIT_MAPPING_CH0 + no description available + 6 + 1 + read-write + + + 0 + Use SPWG standard. + #0 + + + 1 + Use JEIDA standard. + #1 + + + + + DATA_WIDTH_CH1 + no description available + 7 + 1 + read-write + + + 0 + Data width is 18 bits wide (lvds1_tx3 is not used) + #0 + + + 1 + Data width is 24 bits wide. + #1 + + + + + BIT_MAPPING_CH1 + no description available + 8 + 1 + read-write + + + 0 + Use SPWG standard. + #0 + + + 1 + Use JEIDA standard. + #1 + + + + + DI0_VS_POLARITY + no description available + 9 + 1 + read-write + + + 0 + ipu_di0_vsync is active high. + #0 + + + 1 + ipu_di0_vsync is active low. + #1 + + + + + DI1_VS_POLARITY + no description available + 10 + 1 + read-write + + + 0 + ipu_di1_vsync is active high. + #0 + + + 1 + ipu_di1_vsync is active low. + #1 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + LVDS_CLK_SHIFT + no description available + 16 + 3 + read-write + + + 000 + Output clock is '1100011' (normal operation) + #000 + + + 001 + Output clock is '1110001' + #001 + + + 010 + Output clock is '1111000' + #010 + + + 011 + Output clock is '1000111' + #011 + + + 100 + Output clock is '0001111' + #100 + + + 101 + Output clock is '0011111' + #101 + + + 110 + Output clock is '0111100' + #110 + + + 111 + Output clock is '1100011' + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + COUNTER_RESET_VAL + no description available + 20 + 2 + read-write + + + 00 + Reset value is 5 + #00 + + + 01 + Reset value is 3 + #01 + + + 10 + Reset value is 4 + #10 + + + 11 + Reset value is 6 + #11 + + + + + RESERVED + no description available + 22 + 10 + read-only + + + + + GPR3 + GPR3 + 0xC + 32 + read-write + 0x1E00000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + HDMI_MUX_CTL + no description available + 2 + 2 + read-write + + + 00 + HDMI source is IPU1 DI0 port + #00 + + + 01 + HDMI source is IPU1 DI1 port + #01 + + + 10 + HDMI source is LCDIF + #10 + + + + + MIPI_MUX_CTL + no description available + 4 + 2 + read-write + + + 00 + MIPI source is IPU1 DI0 port + #00 + + + 01 + MIPI source is IPU1 DI1 port + #01 + + + 10 + MIPI source is LCDIF + #10 + + + + + LVDS0_MUX_CTL + no description available + 6 + 2 + read-write + + + 00 + LVDS0 source is IPU1 DI0 port + #00 + + + 01 + LVDS0 source is IPU1 DI1 port + #01 + + + 10 + LVDS0 source is LCDIF + #10 + + + + + LVDS1_MUX_CTL + no description available + 8 + 2 + read-write + + + 00 + LVDS1 source is IPU1 DI0 port + #00 + + + 01 + LVDS1 source is IPU1 DI1 port + #01 + + + 10 + LVDS1 source is LCDIF + #10 + + + + + MIPI_DBI_MUX_CTL + no description available + 10 + 1 + read-write + + + 0 + IPU1 DI_1 input source is MIPI DBI + #0 + + + 1 + IPU1 DI_1 input source is itself (from IPU1 DI_1 pad/mux) + #1 + + + + + TZASC1_BOOT_LOCK + no description available + 11 + 1 + read-write + + + 0 + secure boot lock is disabled. + #0 + + + 1 + secure boot lock is enabled + #1 + + + + + TZASC2_BOOT_LOCK + no description available + 12 + 1 + read-write + + + 0 + secure boot lock is disabled. + #0 + + + 1 + secure boot lock is enabled + #1 + + + + + CORE0_DBG_ACK_EN + no description available + 13 + 1 + read-write + + + 0 + Core 0 debug acknowledge is part of global acknowledge. + #0 + + + 1 + Core 0 debug acknowledge is masked by this bit, and it is not part of global acknowledge. + #1 + + + + + CORE1_DBG_ACK_EN + no description available + 14 + 1 + read-write + + + 0 + Core 1 debug acknowledge is part of global acknowledge. + #0 + + + 1 + Core 1 debug acknowledge is masked by this bit, and it is not part of global acknowledge. + #1 + + + + + RESERVED + no description available + 15 + 2 + read-write + + + 0 + Core 2 debug acknowledge is part of global acknowledge. + #0 + + + 1 + Core 2 debug acknowledge is masked by this bit, and it is not part of global acknowledge. + #1 + + + + + OCRAM_STATUS + no description available + 17 + 4 + read-only + + + 0 + read data pipeline configuration valid + #0 + + + 1 + read data pipeline control bit changed + #1 + + + + + OCRAM_CTL + no description available + 21 + 4 + read-write + + + 0 + read data pipeline is disabled + #0 + + + 1 + read data pipeline is enabled + #1 + + + + + uSDHCx_RD_CACHE_CTL + no description available + 25 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + uSDHCx_WR_CACHE_CTL + no description available + 26 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + BCH_RD_CACHE_CTL + no description available + 27 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + BCH_WR_CACHE_CTL + no description available + 28 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + GPU_DBG + no description available + 29 + 2 + read-write + + + 00 + GPU3D + #00 + + + 01 + GPU2D + #01 + + + 10 + OpenVG + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + GPR4 + GPR4 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPU_RD_CACHE_CTL + no description available + 0 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + IPU_WR_CACHE_CTL + no description available + 1 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + VPU_P_RD_CACHE_VAL + no description available + 2 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + VPU_P_WR_CACHE_VAL + no description available + 3 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + VPU_S_RD_CACHE_VAL + no description available + 4 + 1 + read-write + + + VPU_S_WR_CACHE_VAL + no description available + 5 + 1 + read-write + + + VPU_RD_CACHE_SEL + no description available + 6 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the VPU core + #0 + + + 1 + The read transaction cacheable attribute is driven by VPU_SEC_RD_CACHE_VAL for secondary bus and VPU_P_RD_CACHE_VAL for primary bus. + #1 + + + + + VPU_WR_CACHE_SEL + no description available + 7 + 1 + read-write + + + 0 + The write transactions cacheable attribute is driven by the VPU core + #0 + + + 1 + The write transactions cacheable attribute is driven by VPU_SEC_WR_CACHE_VAL for secondary bus and VPU_P_WR_CACHE_VAL for primary bus. + #1 + + + + + SOC_VERSION + no description available + 8 + 8 + read-only + + + ENET_STOP_ACK + no description available + 16 + 1 + read-only + + + 0 + ENET stop acknowledge is not asserted. + #0 + + + 1 + ENET stop acknowledge is asserted, ENET is in STOP mode. + #1 + + + + + CAN1_STOP_ACK + no description available + 17 + 1 + read-only + + + 0 + CAN-1 stop acknowledge is not asserted. + #0 + + + 1 + CAN-1 stop acknowledge is asserted, CAN-1 is in STOP mode. + #1 + + + + + CAN2_STOP_ACK + no description available + 18 + 1 + read-only + + + 0 + CAN-2 stop acknowledge is not asserted. + #0 + + + 1 + CAN-2 stop acknowledge is asserted, CAN-2 is in STOP mode. + #1 + + + + + SDMA_STOP_ACK + no description available + 19 + 1 + read-only + + + 0 + SDMA stop acknowledge is not asserted. + #0 + + + 1 + SDMA stop acknowledge is asserted, SDMA is in STOP mode. + #1 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + PCIe_RD_CACHE_VAL + no description available + 24 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + PCIe_WR_CACHE_VAL + no description available + 25 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + PCIe_RD_CACHE_SEL + no description available + 26 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the PCIe core + #0 + + + 1 + The read transaction cacheable attribute is driven by PCIe_RD_CACHE_VAL. + #1 + + + + + PCIe_WR_CACHE_SEL + no description available + 27 + 1 + read-write + + + 0 + The write transactions cacheable attribute is driven by the PCIe core + #0 + + + 1 + The write transactions cacheable attribute is driven by PCIe_WR_CACHE_VAL. + #1 + + + + + VDOA_RD_CACHE_VAL + no description available + 28 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + VDOA_WR_CACHE_VAL + no description available + 29 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + VDOA_RD_CACHE_SEL + no description available + 30 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the VDOA core + #0 + + + 1 + The read transaction cacheable attribute is driven by VDOA_RD_CACHE_VAL. + #1 + + + + + VDOA_WR_CACHE_SEL + no description available + 31 + 1 + read-write + + + 0 + The write transactions cacheable attribute is driven by the VDOA core + #0 + + + 1 + The write transactions cacheable attribute is driven by VDOA_WR_CACHE_VAL. + #1 + + + + + + + GPR5 + GPR5 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + ARM_WFI + no description available + 0 + 2 + read-only + + + 0 + ARM Core[GPR5-index] is not in “Wait for Interrupt� mode + #0 + + + 1 + ARM Core[GPR5-index] is in “Wait for Interrupt� mode + #1 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + ARM_WFE + no description available + 4 + 2 + read-only + + + 0 + ARM Core[GPR5-index - 4] is not in “Wait for Event� mode + #0 + + + 1 + ARM Core[GPR5-index - 4] is in “Wait for Event� mode + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + L2_CLK_STOP + no description available + 8 + 1 + read-only + + + 0 + L2 cache clock is running + #0 + + + 1 + L2 cache clock stopped + #1 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + GPR6 + GPR6 + 0x18 + 32 + read-write + 0x22222222 + 0xFFFFFFFF + + + IPU1_ID00_WR_QoS + no description available + 0 + 4 + read-write + + + 0000 + 0xxx -3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID01_WR_QoS + no description available + 4 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID10_WR_QoS + no description available + 8 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID11_WR_QoS + no description available + 12 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID00_RD_QoS + no description available + 16 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID01_RD_QoS + no description available + 20 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID10_RD_QoS + no description available + 24 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + IPU1_ID11_RD_QoS + no description available + 28 + 4 + read-write + + + 0000 + 0xxx - 3 lsb’s will be passed as configured + #0000 + + + 1000 + 1xxx - 1111 + #1000 + + + + + + + GPR7 + GPR7 + 0x1C + 32 + read-write + 0x22222222 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + + + GPR8 + GPR8 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCS_TX_DEEMPH_GEN1 + no description available + 0 + 6 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + PCS_TX_DEEMPH_GEN2_3P5DB + no description available + 6 + 6 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + PCS_TX_DEEMPH_GEN2_6DB + no description available + 12 + 6 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + PCS_TX_SWING_FULL + no description available + 18 + 7 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + PCS_TX_SWING_LOW + no description available + 25 + 7 + read-write + + + 0 + TBD + #0 + + + 1 + TBD + #1 + + + + + + + GPR9 + GPR9 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + TZASC1_BYP + no description available + 0 + 1 + read-only + + + 0 + The TZASC-1 is bypassed and the transactions to DDR are not being checked. + #0 + + + 1 + The TZASC-1 is not bypassed and the transactions to DDR are being monitored / checked. + #1 + + + + + TZASC2_BYP + no description available + 1 + 1 + read-only + + + 0 + The TZASC-2 is bypassed and the transactions to DDR are not being checked. + #0 + + + 1 + The TZASC-2 is not bypassed and the transactions to DDR are being monitored / checked. + #1 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + GPR10 + GPR10 + 0x28 + 32 + read-write + 0x3800 + 0xFFFFFFFF + + + DCIC1_MUX_CTL + no description available + 0 + 2 + read-write + + + 00 + DCIC-1 source is IPU1 DI0 port + #00 + + + 01 + DCIC-1 source is LVDS0 + #01 + + + 10 + DCIC-1 source is LVDS1 + #10 + + + 11 + DCIC-1 source is HDMI + #11 + + + + + DCIC2_MUX_CTL + no description available + 2 + 2 + read-write + + + 00 + DCIC-2 source is IPU1 DI1 port + #00 + + + 01 + DCIC-2 source is LVDS0 port + #01 + + + 10 + DCIC-2 source is LVDS1 port + #10 + + + 11 + DCIC-2 source is MIPI DPI port + #11 + + + + + OCRAM_TZ_EN + no description available + 4 + 1 + read-write + + + 0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + #0 + + + 1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + #1 + + + + + OCRAM_TZ_ADDR + no description available + 5 + 5 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + SEC_ERR_RESP + no description available + 11 + 1 + read-write + + + 0 + OKEY response + #0 + + + 1 + SLVError (default) + #1 + + + + + DBG_CLK_EN + no description available + 12 + 1 + read-write + + + 0 + Debug turned off. + #0 + + + 1 + Debug enabled (default). + #1 + + + + + DBG_EN + no description available + 13 + 1 + read-write + + + 0 + Debug turned off. + #0 + + + 1 + Debug enabled (default). + #1 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + LOCK_DCIC1_MUX_CTL + no description available + 16 + 2 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + LOCK_DCIC2_MUX_CTL + no description available + 18 + 2 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + LOCK_OCRAM_TZ_EN + no description available + 20 + 1 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + LOCK_OCRAM_TZ_ADDR + no description available + 21 + 5 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + RESERVED + no description available + 26 + 1 + read-write + + + LOCK_SEC_ERR_RESP + no description available + 27 + 1 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + LOCK_DBG_CLK_EN + no description available + 28 + 1 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + LOCK_DBG_EN + no description available + 29 + 1 + read-write + + + 0 + Field is not locked + #0 + + + 1 + Field is locked (read access only) + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + GPR11 + GPR11 + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + RESERVED + no description available + 1 + 15 + read-only + + + RESERVED + no description available + 16 + 1 + read-only + + + RESERVED + no description available + 17 + 15 + read-only + + + + + GPR12 + GPR12 + 0x30 + 32 + read-write + 0xF000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + uSDHC_DBG_MUX + no description available + 2 + 2 + read-write + + + LOS_LEVEL + no description available + 4 + 5 + read-write + + + APPS_PM_XMT_PME + no description available + 9 + 1 + read-write + + + APP_LTSSM_ENABLE + no description available + 10 + 1 + read-write + + + 0 + Application is not ready. + #0 + + + 1 + Application is not ready. + #1 + + + + + APP_INIT_RST + no description available + 11 + 1 + read-write + + + DEVICE_TYPE + no description available + 12 + 4 + read-write + + + 0000 + PCIE_EP + #0000 + + + 0010 + PCIE_RC + #0010 + + + + + APPS_PM_XMT_TURNOFF + no description available + 16 + 1 + read-write + + + DIAG_STATUS_BUS_SELECT + no description available + 17 + 4 + read-write + + + PCIe_CTL_7 + no description available + 21 + 3 + read-write + + + ARMP_APB_CLK_EN + no description available + 24 + 1 + read-write + + + 0 + IPG clock is not running (gated). + #0 + + + 1 + IPG clock is running (enabled). + #1 + + + + + ARMP_ATB_CLK_EN + no description available + 25 + 1 + read-write + + + 0 + IPG clock is not running (gated). + #0 + + + 1 + IPG clock is running (enabled). + #1 + + + + + ARMP_AHB_CLK_EN + no description available + 26 + 1 + read-write + + + 0 + IPG clock is not running (gated). + #0 + + + 1 + IPG clock is running (enabled). + #1 + + + + + ARMP_IPG_CLK_EN + no description available + 27 + 1 + read-write + + + 0 + IPG clock is not running (gated). + #0 + + + 1 + IPG clock is running (enabled). + #1 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + GPR13 + GPR13 + 0x34 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + IPU_CSI0_MUX + no description available + 0 + 3 + read-write + + + 000 + MIPI_CSI0 + #000 + + + 001 + MIPI_CSI1 + #001 + + + 010 + MIPI_CSI2 + #010 + + + 011 + MIPI_CSI3 + #011 + + + 100 + IPU CSI0 + #100 + + + + + IPU_CSI1_MUX + no description available + 3 + 3 + read-write + + + 000 + MIPI CSI0 + #000 + + + 001 + MIPI CSI1 + #001 + + + 010 + MIPI CSI2 + #010 + + + 011 + MIPI CSI3 + #011 + + + 100 + IPU CSI1 + #100 + + + + + RESERVED + no description available + 6 + 2 + read-write + + + PXP_RD_CACHE_VAL + no description available + 8 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + PXP_WR_CACHE_VAL + no description available + 9 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + PXP_RD_CACHE_SEL + no description available + 10 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the PXP core + #0 + + + 1 + The read transaction cacheable attribute is driven by PXP_RD_CACHE_VAL. + #1 + + + + + PXP_WR_CACHE_SEL + no description available + 11 + 1 + read-write + + + 0 + The write transactions cacheable attribute is driven by the PXP core + #0 + + + 1 + The write transactions cacheable attribute is driven by PXP_WR_CACHE_VAL. + #1 + + + + + EPDC_RD_CACHE_VAL + no description available + 12 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + EPDC_WR_CACHE_VAL + no description available + 13 + 1 + read-write + + + 0 + Cacheable attribute is off for write transactions. + #0 + + + 1 + Cacheable attribute is on for write transactions. + #1 + + + + + EPDC_RD_CACHE_SEL + no description available + 14 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the EPDC core + #0 + + + 1 + The read transaction cacheable attribute is driven by EPDC_RD_CACHE_VAL. + #1 + + + + + EPDC_WR_CACHE_SEL + no description available + 15 + 1 + read-write + + + 0 + The write transactions cacheable attribute is driven by the EPDC core + #0 + + + 1 + The write transactions cacheable attribute is driven by EPDC_WR_CACHE_VAL. + #1 + + + + + LCDIF_RD_CACHE_VAL + no description available + 16 + 1 + read-write + + + 0 + Cacheable attribute is off for read transactions. + #0 + + + 1 + Cacheable attribute is on for read transactions. + #1 + + + + + RESERVED + no description available + 17 + 1 + read-write + + + LCDIF_RD_CACHE_SEL + no description available + 18 + 1 + read-write + + + 0 + The read transaction cacheable attribute is driven by the LCDIF core + #0 + + + 1 + The read transaction cacheable attribute is driven by LCDIF_RD_CACHE_VAL. + #1 + + + + + RESERVED + no description available + 19 + 8 + read-write + + + ENET_STOP_REQ + no description available + 27 + 1 + read-write + + + 0 + Stop request off. + #0 + + + 1 + Stop request on. + #1 + + + + + CAN1_STOP_REQ + no description available + 28 + 1 + read-write + + + 0 + Stop request off. + #0 + + + 1 + Stop request on. + #1 + + + + + CAN2_STOP_REQ + no description available + 29 + 1 + read-write + + + 0 + Stop request off. + #0 + + + 1 + Stop request on. + #1 + + + + + SDMA_STOP_REQ + no description available + 30 + 1 + read-write + + + 0 + Stop request off. + #0 + + + 1 + Stop request on. + #1 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA10 + Pad Mux Register + 0x4C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA11 + Pad Mux Register + 0x50 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA12 + Pad Mux Register + 0x54 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 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RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA15 + Pad Mux Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA16 + Pad Mux Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA17 + Pad Mux Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA18 + Pad Mux Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA19 + Pad Mux Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA04 + Pad Mux Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA05 + Pad Mux Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA06 + Pad Mux Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA07 + Pad Mux Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA08 + Pad Mux Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA09 + Pad Mux Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 010 + ALT2 + #010 + + + 011 + ALT3 + #011 + + + 100 + ALT4 + #100 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_DATA_EN + Pad Mux Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_HSYNC + Pad Mux Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 011 + ALT3 + #011 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_PIXCLK + Pad Mux Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_CSI0_VSYNC + Pad Mux Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 001 + ALT1 + #001 + + + 101 + ALT5 + #101 + + + 111 + ALT7 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DI0_DISP_CLK + Pad Mux Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + 0000 + ALT0 + #0000 + + + 0101 + ALT5 + #0101 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DI0_PIN15 + Pad Mux Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + 0000 + ALT0 + #0000 + + + 0010 + ALT2 + #0010 + + + 0101 + ALT5 + #0101 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DI0_PIN02 + Pad Mux Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + 0000 + ALT0 + #0000 + + + 0010 + ALT2 + #0010 + + + 0101 + ALT5 + #0101 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DI0_PIN03 + Pad Mux Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + 0000 + ALT0 + #0000 + + + 0010 + ALT2 + #0010 + + + 0101 + ALT5 + #0101 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DI0_PIN04 + Pad Mux Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + 0000 + ALT0 + #0000 + + + 0010 + ALT2 + #0010 + + + 0011 + ALT3 + #0011 + + + 0101 + ALT5 + #0101 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DISP0_DATA00 + Pad Mux Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 010 + ALT2 + #010 + + + 101 + ALT5 + #101 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + SION + Software Input On Field. + 4 + 1 + read-write + + + 1 + ENABLED + #1 + + + 0 + DISABLED + #0 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + SW_MUX_CTL_PAD_DISP0_DATA01 + Pad Mux Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + 000 + ALT0 + #000 + + + 010 + ALT2 + #010 + + + 101 + ALT5 + #101 + + + + + RESERVED + no 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+ Select Input Register + 0x798 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA23_ALT3 + #0 + + + 1 + SD2_DATA0_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD4_INPUT_DB_AMX_SELECT_INPUT + Select Input Register + 0x79C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA21_ALT3 + #0 + + + 1 + SD2_DATA2_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD4_INPUT_RXCLK_AMX_SELECT_INPUT + Select Input Register + 0x7A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA19_ALT4 + #0 + + + 1 + SD2_CMD_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD4_INPUT_RXFS_AMX_SELECT_INPUT + Select Input Register + 0x7A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA18_ALT4 + #0 + + + 1 + SD2_CLK_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD4_INPUT_TXCLK_AMX_SELECT_INPUT + Select Input Register + 0x7A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA20_ALT3 + #0 + + + 1 + SD2_DATA3_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD4_INPUT_TXFS_AMX_SELECT_INPUT + Select Input Register + 0x7AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA22_ALT3 + #0 + + + 1 + SD2_DATA1_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_DA_AMX_SELECT_INPUT + Select Input Register + 0x7B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA19_ALT3 + #0 + + + 1 + KEY_ROW1_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_DB_AMX_SELECT_INPUT + Select Input Register + 0x7B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA17_ALT3 + #0 + + + 1 + KEY_ROW0_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_RXCLK_AMX_SELECT_INPUT + Select Input Register + 0x7B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA14_ALT3 + #0 + + + 1 + EIM_DATA25_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_RXFS_AMX_SELECT_INPUT + Select Input Register + 0x7BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA13_ALT3 + #0 + + + 1 + EIM_DATA24_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_TXCLK_AMX_SELECT_INPUT + Select Input Register + 0x7C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA16_ALT3 + #0 + + + 1 + KEY_COL0_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + AUD5_INPUT_TXFS_AMX_SELECT_INPUT + Select Input Register + 0x7C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA18_ALT3 + #0 + + + 1 + KEY_COL1_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + FLEXCAN1_RX_SELECT_INPUT + Select Input Register + 0x7C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + GPIO08_ALT3 + #00 + + + 01 + KEY_ROW2_ALT2 + #01 + + + 10 + SD3_CLK_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + FLEXCAN2_RX_SELECT_INPUT + Select Input Register + 0x7CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + KEY_ROW4_ALT0 + #0 + + + 1 + SD3_DATA1_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CCM_PMIC_READY_SELECT_INPUT + Select Input Register + 0x7D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_EB0_B_ALT4 + #0 + + + 1 + GPIO17_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ECSPI1_CSPI_CLK_IN_SELECT_INPUT + Select Input Register + 0x7D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA04_ALT2 + #00 + + + 01 + DISP0_DATA20_ALT2 + #01 + + + 10 + EIM_DATA16_ALT1 + #10 + + + 11 + KEY_COL0_ALT0 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI1_MISO_SELECT_INPUT + Select Input Register + 0x7DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA06_ALT2 + #00 + + + 01 + DISP0_DATA22_ALT2 + #01 + + + 10 + EIM_DATA17_ALT1 + #10 + + + 11 + KEY_COL1_ALT0 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI1_MOSI_SELECT_INPUT + Select Input Register + 0x7E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA05_ALT2 + #00 + + + 01 + DISP0_DATA21_ALT2 + #01 + + + 10 + EIM_DATA18_ALT1 + #10 + + + 11 + KEY_ROW0_ALT0 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI1_SS0_SELECT_INPUT + Select Input Register + 0x7E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA07_ALT2 + #00 + + + 01 + DISP0_DATA23_ALT2 + #01 + + + 10 + EIM_EB2_B_ALT1 + #10 + + + 11 + KEY_ROW1_ALT0 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI1_SS1_SELECT_INPUT + Select Input Register + 0x7E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + DISP0_DATA15_ALT2 + #00 + + + 01 + EIM_DATA19_ALT1 + #01 + + + 10 + KEY_COL2_ALT0 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI1_SS2_SELECT_INPUT + Select Input Register + 0x7EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA24_ALT3 + #0 + + + 1 + KEY_ROW2_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ECSPI1_SS3_SELECT_INPUT + Select Input Register + 0x7F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA25_ALT3 + #0 + + + 1 + KEY_COL3_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ECSPI2_CSPI_CLK_IN_SELECT_INPUT + Select Input Register + 0x7F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA08_ALT2 + #00 + + + 01 + DISP0_DATA19_ALT2 + #01 + + + 10 + EIM_CS0_B_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI2_MISO_SELECT_INPUT + Select Input Register + 0x7F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA10_ALT2 + #00 + + + 01 + DISP0_DATA17_ALT2 + #01 + + + 10 + EIM_OE_B_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI2_MOSI_SELECT_INPUT + Select Input Register + 0x7FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA09_ALT2 + #00 + + + 01 + DISP0_DATA16_ALT2 + #01 + + + 10 + EIM_CS1_B_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI2_SS0_SELECT_INPUT + Select Input Register + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA11_ALT2 + #00 + + + 01 + DISP0_DATA18_ALT2 + #01 + + + 10 + EIM_RW_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + ECSPI2_SS1_SELECT_INPUT + Select Input Register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA15_ALT3 + #0 + + + 1 + EIM_LBA_B_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ECSPI4_SS0_SELECT_INPUT + Select Input Register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA20_ALT1 + #0 + + + 1 + EIM_DATA29_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_REF_CLK_SELECT_INPUT + Select Input Register + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + GPIO16_ALT2 + #0 + + + 1 + RGMII_TX_CTL_ALT7 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_MDIO_SELECT_INPUT + Select Input Register + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_MDIO_ALT1 + #0 + + + 1 + KEY_COL1_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_CLK_SELECT_INPUT + Select Input Register + 0x814 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + GPIO18_ALT1 + #0 + + + 1 + RGMII_RXC_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_DATA0_SELECT_INPUT + Select Input Register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_DATA0_ALT1 + #0 + + + 1 + RGMII_RD0_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_DATA1_SELECT_INPUT + Select Input Register + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_DATA1_ALT1 + #0 + + + 1 + RGMII_RD1_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_DATA2_SELECT_INPUT + Select Input Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + KEY_COL2_ALT1 + #0 + + + 1 + RGMII_RD2_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_DATA3_SELECT_INPUT + Select Input Register + 0x824 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + KEY_COL0_ALT1 + #0 + + + 1 + RGMII_RD3_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ENET_MAC0_RX_EN_SELECT_INPUT + Select Input Register + 0x828 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_CRS_DV_ALT1 + #0 + + + 1 + RGMII_RX_CTL_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_RX_FS_SELECT_INPUT + Select Input Register + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_REF_CLK_ALT2 + #0 + + + 1 + GPIO09_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_TX_FS_SELECT_INPUT + Select Input Register + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_DATA1_ALT2 + #0 + + + 1 + GPIO02_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_RX_HF_CLK_SELECT_INPUT + Select Input Register + 0x834 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_ER_ALT2 + #0 + + + 1 + GPIO03_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_TX_HF_CLK_SELECT_INPUT + Select Input Register + 0x838 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_DATA0_ALT2 + #0 + + + 1 + GPIO04_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_RX_CLK_SELECT_INPUT + Select Input Register + 0x83C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_MDIO_ALT2 + #0 + + + 1 + GPIO01_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_TX_CLK_SELECT_INPUT + Select Input Register + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_CRS_DV_ALT2 + #0 + + + 1 + GPIO06_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO0_SELECT_INPUT + Select Input Register + 0x844 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + GPIO17_ALT0 + #0 + + + 1 + NAND_CS2_B_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO1_SELECT_INPUT + Select Input Register + 0x848 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + GPIO18_ALT0 + #0 + + + 1 + NAND_CS3_B_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO2_SDI3_SELECT_INPUT + Select Input Register + 0x84C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_TX_DATA1_ALT2 + #0 + + + 1 + GPIO05_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO3_SDI2_SELECT_INPUT + Select Input Register + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_TX_EN_ALT2 + #0 + + + 1 + GPIO16_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO4_SDI1_SELECT_INPUT + Select Input Register + 0x854 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_TX_DATA0_ALT2 + #0 + + + 1 + GPIO07_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + ESAI_SDO5_SDI0_SELECT_INPUT + Select Input Register + 0x858 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_MDC_ALT2 + #0 + + + 1 + GPIO08_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + HDMI_ICECIN_SELECT_INPUT + Select Input Register + 0x85C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR25_ALT6 + #0 + + + 1 + KEY_ROW2_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + HDMI_II2C_CLKIN_SELECT_INPUT + Select Input Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_EB2_B_ALT4 + #0 + + + 1 + KEY_COL3_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + HDMI_II2C_DATAIN_SELECT_INPUT + Select Input Register + 0x864 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA16_ALT4 + #0 + + + 1 + KEY_ROW3_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + I2C1_SCL_IN_SELECT_INPUT + Select Input Register + 0x868 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + CSI0_DATA09_ALT4 + #0 + + + 1 + EIM_DATA21_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + I2C1_SDA_IN_SELECT_INPUT + Select Input Register + 0x86C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + CSI0_DATA08_ALT4 + #0 + + + 1 + EIM_DATA28_ALT1 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + I2C2_SCL_IN_SELECT_INPUT + Select Input Register + 0x870 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_EB2_B_ALT6 + #0 + + + 1 + KEY_COL3_ALT4 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + I2C2_SDA_IN_SELECT_INPUT + Select Input Register + 0x874 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA16_ALT6 + #0 + + + 1 + KEY_ROW3_ALT4 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + I2C3_SCL_IN_SELECT_INPUT + Select Input Register + 0x878 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + EIM_DATA17_ALT6 + #00 + + + 01 + GPIO03_ALT2 + #01 + + + 10 + GPIO05_ALT6 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + I2C3_SDA_IN_SELECT_INPUT + Select Input Register + 0x87C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + EIM_DATA18_ALT6 + #00 + + + 01 + GPIO16_ALT6 + #01 + + + 10 + GPIO06_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + I2C4_SCL_IN_SELECT_INPUT + Select Input Register + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + ENET_TX_EN_ALT9 + #00 + + + 01 + GPIO07_ALT8 + #01 + + + 10 + NAND_WP_B_ALT9 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + I2C4_SDA_IN_SELECT_INPUT + Select Input Register + 0x884 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + ENET_TX_DATA1_ALT9 + #00 + + + 01 + GPIO08_ALT8 + #01 + + + 10 + NAND_CS3_B_ALT9 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + IPU1_SENS1_DATA10_SELECT_INPUT + Select Input Register + 0x888 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA22_ALT3 + #0 + + + 1 + EIM_EB1_B_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA11_SELECT_INPUT + Select Input Register + 0x88C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA21_ALT3 + #0 + + + 1 + EIM_EB0_B_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA12_SELECT_INPUT + Select Input Register + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR17_ALT2 + #0 + + + 1 + EIM_DATA28_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA13_SELECT_INPUT + Select Input Register + 0x894 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR18_ALT2 + #0 + + + 1 + EIM_DATA27_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA14_SELECT_INPUT + Select Input Register + 0x898 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR19_ALT2 + #0 + + + 1 + EIM_DATA26_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA15_SELECT_INPUT + Select Input Register + 0x89C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR20_ALT2 + #0 + + + 1 + EIM_DATA20_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA16_SELECT_INPUT + Select Input Register + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR21_ALT2 + #0 + + + 1 + EIM_DATA19_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA17_SELECT_INPUT + Select Input Register + 0x8A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR22_ALT2 + #0 + + + 1 + EIM_DATA18_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA18_SELECT_INPUT + Select Input Register + 0x8A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR23_ALT2 + #0 + + + 1 + EIM_DATA16_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA19_SELECT_INPUT + Select Input Register + 0x8AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR24_ALT2 + #0 + + + 1 + EIM_EB2_B_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_DATA_EN_SELECT_INPUT + Select Input Register + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA23_ALT4 + #0 + + + 1 + EIM_AD10_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_HSYNC_SELECT_INPUT + Select Input Register + 0x8B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_AD11_ALT2 + #0 + + + 1 + EIM_EB3_B_ALT4 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_PIX_CLK_SELECT_INPUT + Select Input Register + 0x8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_ADDR16_ALT2 + #0 + + + 1 + EIM_DATA17_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + IPU1_SENS1_VSYNC_SELECT_INPUT + Select Input Register + 0x8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA29_ALT6 + #0 + + + 1 + EIM_AD12_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + KEY_COL5_SELECT_INPUT + Select Input Register + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA04_ALT3 + #00 + + + 01 + GPIO00_ALT2 + #01 + + + 10 + GPIO19_ALT0 + #10 + + + 11 + SD2_CLK_ALT2 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + KEY_COL6_SELECT_INPUT + Select Input Register + 0x8C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA06_ALT3 + #00 + + + 01 + GPIO09_ALT2 + #01 + + + 10 + SD2_DATA3_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + KEY_COL7_SELECT_INPUT + Select Input Register + 0x8C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA08_ALT3 + #00 + + + 01 + GPIO04_ALT2 + #01 + + + 10 + SD2_DATA1_ALT4 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + KEY_ROW5_SELECT_INPUT + Select Input Register + 0x8CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA05_ALT3 + #00 + + + 01 + GPIO01_ALT2 + #01 + + + 10 + SD2_CMD_ALT2 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + KEY_ROW6_SELECT_INPUT + Select Input Register + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA07_ALT3 + #00 + + + 01 + GPIO02_ALT2 + #01 + + + 10 + SD2_DATA2_ALT4 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + KEY_ROW7_SELECT_INPUT + Select Input Register + 0x8D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA09_ALT3 + #00 + + + 01 + GPIO05_ALT2 + #01 + + + 10 + SD2_DATA0_ALT4 + #10 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + MLB_MLB_CLK_IN_SELECT_INPUT + Select Input Register + 0x8DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_TX_DATA1_ALT0 + #0 + + + 1 + GPIO03_ALT7 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + MLB_MLB_DATA_IN_SELECT_INPUT + Select Input Register + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_MDC_ALT0 + #0 + + + 1 + GPIO02_ALT7 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + MLB_MLB_SIG_IN_SELECT_INPUT + Select Input Register + 0x8E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_RX_DATA1_ALT0 + #0 + + + 1 + GPIO06_ALT7 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + SDMA_EVENTS14_SELECT_INPUT + Select Input Register + 0x8E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA16_ALT4 + #0 + + + 1 + GPIO17_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + SDMA_EVENTS15_SELECT_INPUT + Select Input Register + 0x8EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DISP0_DATA17_ALT4 + #0 + + + 1 + GPIO18_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + SPDIF_SPDIF_IN1_SELECT_INPUT + Select Input Register + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + EIM_DATA21_ALT7 + #00 + + + 01 + ENET_RX_ER_ALT3 + #01 + + + 10 + GPIO16_ALT4 + #10 + + + 11 + KEY_COL3_ALT6 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + SPDIF_TX_CLK2_SELECT_INPUT + Select Input Register + 0x8F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + ENET_CRS_DV_ALT3 + #0 + + + 1 + RGMII_TXC_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + UART1_UART_RTS_B_SELECT_INPUT + Select Input Register + 0x8F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + EIM_DATA19_ALT4 + #00 + + + 01 + EIM_DATA20_ALT4 + #01 + + + 10 + SD3_DATA0_ALT1 + #10 + + + 11 + SD3_DATA1_ALT1 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + UART1_UART_RX_DATA_SELECT_INPUT + Select Input Register + 0x8FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA10_ALT3 + #00 + + + 01 + CSI0_DATA11_ALT3 + #01 + + + 10 + SD3_DATA6_ALT1 + #10 + + + 11 + SD3_DATA7_ALT1 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + UART2_UART_RTS_B_SELECT_INPUT + Select Input Register + 0x900 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 3 + read-write + + + 000 + EIM_DATA28_ALT4 + #000 + + + 001 + EIM_DATA29_ALT4 + #001 + + + 010 + SD3_CLK_ALT1 + #010 + + + 011 + SD3_CMD_ALT1 + #011 + + + 100 + SD4_DATA5_ALT2 + #100 + + + 101 + SD4_DATA6_ALT2 + #101 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + UART2_UART_RX_DATA_SELECT_INPUT + Select Input Register + 0x904 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 3 + read-write + + + 000 + EIM_DATA26_ALT4 + #000 + + + 001 + EIM_DATA27_ALT4 + #001 + + + 010 + GPIO07_ALT4 + #010 + + + 011 + GPIO08_ALT4 + #011 + + + 100 + SD3_DATA4_ALT1 + #100 + + + 101 + SD3_DATA5_ALT1 + #101 + + + 110 + SD4_DATA4_ALT2 + #110 + + + 111 + SD4_DATA7_ALT2 + #111 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + UART3_UART_RTS_B_SELECT_INPUT + Select Input Register + 0x908 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 3 + read-write + + + 000 + EIM_DATA23_ALT2 + #000 + + + 001 + EIM_DATA30_ALT4 + #001 + + + 010 + EIM_DATA31_ALT4 + #010 + + + 011 + EIM_EB3_B_ALT2 + #011 + + + 100 + SD3_DATA3_ALT1 + #100 + + + 101 + SD3_RESET_ALT1 + #101 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + UART3_UART_RX_DATA_SELECT_INPUT + Select Input Register + 0x90C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + EIM_DATA24_ALT2 + #00 + + + 01 + EIM_DATA25_ALT2 + #01 + + + 10 + SD4_CLK_ALT2 + #10 + + + 11 + SD4_CMD_ALT2 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + UART4_UART_RTS_B_SELECT_INPUT + Select Input Register + 0x910 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + CSI0_DATA16_ALT3 + #0 + + + 1 + CSI0_DATA17_ALT3 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + UART4_UART_RX_DATA_SELECT_INPUT + Select Input Register + 0x914 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA12_ALT3 + #00 + + + 01 + CSI0_DATA13_ALT3 + #01 + + + 10 + KEY_COL0_ALT4 + #10 + + + 11 + KEY_ROW0_ALT4 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + UART5_UART_RTS_B_SELECT_INPUT + Select Input Register + 0x918 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA18_ALT3 + #00 + + + 01 + CSI0_DATA19_ALT3 + #01 + + + 10 + KEY_COL4_ALT4 + #10 + + + 11 + KEY_ROW4_ALT4 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + UART5_UART_RX_DATA_SELECT_INPUT + Select Input Register + 0x91C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 2 + read-write + + + 00 + CSI0_DATA14_ALT3 + #00 + + + 01 + CSI0_DATA15_ALT3 + #01 + + + 10 + KEY_COL1_ALT4 + #10 + + + 11 + KEY_ROW1_ALT4 + #11 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + USB_OTG_OC_SELECT_INPUT + Select Input Register + 0x920 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA21_ALT4 + #0 + + + 1 + KEY_COL4_ALT2 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USB_H1_OC_SELECT_INPUT + Select Input Register + 0x924 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + EIM_DATA30_ALT6 + #0 + + + 1 + GPIO03_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USDHC1_CARD_CLK_IN_SELECT_INPUT + Select Input Register + 0x928 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + RESERVED0 + #0 + + + 1 + SD1_CLK_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USDHC1_WP_ON_SELECT_INPUT + Select Input Register + 0x92C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + DI0_PIN04_ALT3 + #0 + + + 1 + GPIO09_ALT6 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USDHC2_CARD_CLK_IN_SELECT_INPUT + Select Input Register + 0x930 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + RESERVED0 + #0 + + + 1 + SD2_CLK_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USDHC3_CARD_CLK_IN_SELECT_INPUT + Select Input Register + 0x934 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + RESERVED0 + #0 + + + 1 + SD3_CLK_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + USDHC4_CARD_CLK_IN_SELECT_INPUT + Select Input Register + 0x938 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Input Select (DAISY) Field + 0 + 1 + read-write + + + 0 + RESERVED0 + #0 + + + 1 + SD4_CLK_ALT0 + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + + + LDB + LDB + LDB_ + 0x20E0008 + + 0 + 0x4 + registers + + + + CTRL + LDB Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ch0_mode + no description available + 0 + 2 + read-write + + + 00 + Channel disabled. + #00 + + + 01 + Channel enabled, routed to DI0 + #01 + + + 10 + Channel disabled. + #10 + + + 11 + Channel enabled, routed to DI1. + #11 + + + + + ch1_mode + no description available + 2 + 2 + read-write + + + 00 + Channel disabled. + #00 + + + 01 + Channel enabled, routed to DI0 + #01 + + + 10 + Channel disabled. + #10 + + + 11 + Channel enabled, routed to DI1. + #11 + + + + + split_mode_en + no description available + 4 + 1 + read-write + + + 0 + Split mode is disabled. + #0 + + + 1 + Split mode is enabled. + #1 + + + + + data_width_ch0 + no description available + 5 + 1 + read-write + + + 0 + Data width is 18 bits wide (lvds0_tx3 is not used) + #0 + + + 1 + Data width is 24 bits wide. + #1 + + + + + bit_mapping_ch0 + no description available + 6 + 1 + read-write + + + 0 + Use SPWG standard. + #0 + + + 1 + Use JEIDA standard. + #1 + + + + + data_width_ch1 + no description available + 7 + 1 + read-write + + + 0 + Data width is 18 bits wide (lvds1_tx3 is not used) + #0 + + + 1 + Data width is 24 bits wide. + #1 + + + + + bit_mapping_ch1 + no description available + 8 + 1 + read-write + + + 0 + Use SPWG standard. + #0 + + + 1 + Use JEIDA standard. + #1 + + + + + di0_vs_polarity + no description available + 9 + 1 + read-write + + + 0 + ipu_di0_vsync is active high. + #0 + + + 1 + ipu_di0_vsync is active low. + #1 + + + + + di1_vs_polarity + no description available + 10 + 1 + read-write + + + 0 + ipu_di1_vsync is active high. + #0 + + + 1 + ipu_di1_vsync is active low. + #1 + + + + + RESERVED + no description available + 11 + 4 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + lvds_clk_shift + no description available + 16 + 3 + read-write + + + 000 + Output clock is '1100011' (normal operation) + #000 + + + 001 + Output clock is '1110001' + #001 + + + 010 + Output clock is '1111000' + #010 + + + 011 + Output clock is '1000111' + #011 + + + 100 + Output clock is '0001111' + #100 + + + 101 + Output clock is '0011111' + #101 + + + 110 + Output clock is '0111100' + #110 + + + 111 + Output clock is '1100011' + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + counter_reset_val + no description available + 20 + 2 + read-write + + + 00 + Reset value is 5 + #00 + + + 01 + Reset value is 3 + #01 + + + 10 + Reset value is 4 + #10 + + + 11 + Reset value is 6 + #11 + + + + + RESERVED + no description available + 22 + 10 + read-only + + + + + + + DCIC1 + DCIC + DCIC + DCIC1_ + 0x20E4000 + + 0 + 0x20 + registers + + + + DCICC + DCIC Control Register + 0 + 32 + read-write + 0x70 + 0xFFFFFFFF + + + IC_EN + no description available + 0 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + RESERVED + no description available + 1 + 3 + read-only + + + DE_POL + no description available + 4 + 1 + read-write + + + 0 + Active High. + #0 + + + 1 + Active Low (default). + #1 + + + + + HSYNC_POL + no description available + 5 + 1 + read-write + + + 0 + Active High. + #0 + + + 1 + Active Low (default). + #1 + + + + + VSYNC_POL + no description available + 6 + 1 + read-write + + + 0 + Active High. + #0 + + + 1 + Active Low (default). + #1 + + + + + CLK_POL + no description available + 7 + 1 + read-write + + + 0 + Not inverted (default). + #0 + + + 1 + Inverted. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DCICIC + DCIC Interrupt Control Register + 0x4 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + EI_MASK + no description available + 0 + 1 + read-write + + + 0 + Mask disabled - Interrupt assertion enabled + #0 + + + 1 + Mask enabled - Interrupt assertion disabled (default) + #1 + + + + + FI_MASK + no description available + 1 + 1 + read-write + + + 0 + Mask disabled - Interrupt assertion enabled + #0 + + + 1 + Mask enabled - Interrupt assertion disabled (default) + #1 + + + + + RESERVED + no description available + 2 + 1 + read-only + + + FREEZE_MASK + no description available + 3 + 1 + read-write + + + 0 + Masks change allowed (default) + #0 + + + 1 + Masks are frozen + #1 + + + + + RESERVED + no description available + 4 + 12 + read-only + + + EXT_SIG_EN + no description available + 16 + 1 + read-write + + + 0 + Disabled (default) + #0 + + + 1 + Enabled + #1 + + + + + RESERVED + no description available + 17 + 15 + read-only + + + + + DCICS + DCIC Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ROI_MATCH_STAT + no description available + 0 + 16 + read-write + + + 0 + ROI calculated CRC matches expected signature + #0 + + + 1 + Mismatch at ROI calculated CRC + #1 + + + + + EI_STAT + no description available + 16 + 1 + read-only + + + 0 + No pending Interrupt + #0 + + + 1 + Pending Interrupt + #1 + + + + + FI_STAT + no description available + 17 + 1 + read-write + + + 0 + No pending Interrupt + #0 + + + 1 + Pending Interrupt + #1 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + DCICRC + DCIC ROI Config Register m + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + START_OFFSET_X + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + START_OFFSET_Y + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 2 + read-only + + + ROI_FREEZE + no description available + 30 + 1 + read-write + + + 0 + ROI configuration can be changed + #0 + + + 1 + ROI configuration is frozen + #1 + + + + + ROI_EN + no description available + 31 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + DCICRS + DCIC ROI Size Register m + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + END_OFFSET_X + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + END_OFFSET_Y + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DCICRRS + DCIC ROI Reference Signature Register m + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + REFERENCE_SIGNATURE + no description available + 0 + 32 + read-write + + + + + DCICRCS + DCIC ROI Calculated Signature m + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CALCULATED_SIGNATURE + no description available + 0 + 32 + read-only + + + + + + + DCIC2 + DCIC + DCIC + DCIC2_ + 0x20E8000 + + 0 + 0x20 + registers + + + + DCICC + DCIC Control Register + 0 + 32 + read-write + 0x70 + 0xFFFFFFFF + + + IC_EN + no description available + 0 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + 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available + 16 + 14 + read-write + + + RSVD1 + no description available + 30 + 2 + read-only + + + + + PS_CTRL + Processed Surface (PS) Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FORMAT + no description available + 0 + 5 + read-write + + + 100 + RGB888 + #100 + + + 1100 + RGB555 + #1100 + + + 1101 + RGB444 + #1101 + + + 1110 + RGB565 + #1110 + + + 10000 + YUV1P444 + #10000 + + + 10010 + UYVY1P422 + #10010 + + + 10011 + VYUY1P422 + #10011 + + + 10100 + Y8 + #10100 + + + 10101 + Y4 + #10101 + + + 11000 + YUV2P422 + #11000 + + + 11001 + YUV2P420 + #11001 + + + 11010 + YVU2P422 + #11010 + + + 11011 + YVU2P420 + #11011 + + + 11110 + YUV422 + #11110 + + + 11111 + YUV420 + #11111 + + + + + WB_SWAP + no description available + 5 + 1 + read-write + + + RSVD0 + no description available + 6 + 2 + read-only + + + DECY + no description available + 8 + 2 + read-write + + + 0 + DISABLE + #0 + + + 1 + DECY2 + #1 + + + 10 + DECY4 + #10 + + + 11 + DECY8 + #11 + + + + + DECX + no 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Color Key High + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + no description available + 0 + 24 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + AS_CTRL + Alpha Surface Control + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 1 + read-only + + + ALPHA_CTRL + no description available + 1 + 2 + read-write + + + 0 + Embedded + #0 + + + 1 + Override + #1 + + + 10 + Multiply + #10 + + + 11 + ROPs + #11 + + + + + ENABLE_COLORKEY + no description available + 3 + 1 + read-write + + + FORMAT + no description available + 4 + 4 + read-write + + + 0 + ARGB8888 + #0 + + + 100 + RGB888 + #100 + + + 1000 + ARGB1555 + #1000 + + + 1001 + ARGB4444 + #1001 + + + 1100 + RGB555 + #1100 + + + 1101 + RGB444 + #1101 + + + 1110 + RGB565 + #1110 + + + + + ALPHA + no description available + 8 + 8 + read-write + + + ROP + no description available + 16 + 4 + read-write + + + 0 + MASKAS + #0 + + + 1 + MASKNOTAS + #1 + + + 10 + MASKASNOT + #10 + + + 11 + MERGEAS + #11 + + + 100 + MERGENOTAS + #100 + + + 101 + MERGEASNOT + #101 + + + 110 + NOTCOPYAS + #110 + + + 111 + NOT + #111 + + + 1000 + NOTMASKAS + #1000 + + + 1001 + NOTMERGEAS + #1001 + + + 1010 + XORAS + #1010 + + + 1011 + NOTXORAS + #1011 + + + + + ALPHA_INVERT + no description available + 20 + 1 + read-write + + + RSVD1 + no description available + 21 + 11 + read-only + + + + + AS_BUF + Alpha Surface Buffer Pointer + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 32 + read-write + + + + + AS_PITCH + Alpha Surface Pitch + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + PITCH + no description available + 0 + 16 + read-write + + + RSVD + no description available + 16 + 16 + read-only + + + + + AS_CLRKEYLOW + Overlay Color Key Low + 0x180 + 32 + read-write + 0xFFFFFF + 0xFFFFFFFF + + + PIXEL + no description available + 0 + 24 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + AS_CLRKEYHIGH + Overlay Color Key High + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + PIXEL + no description available + 0 + 24 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + CSC1_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1A0 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + Y_OFFSET + no description available + 0 + 9 + read-write + + + UV_OFFSET + no description available + 9 + 9 + read-write + + + C0 + no description available + 18 + 11 + read-write + + + RSVD1 + no description available + 29 + 1 + read-only + + + BYPASS + no description available + 30 + 1 + read-write + + + YCBCR_MODE + no description available + 31 + 1 + read-write + + + + + CSC1_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1B0 + 32 + read-write + 0x1230208 + 0xFFFFFFFF + + + C4 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + C1 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC1_COEF2 + Color Space Conversion Coefficient Register 2 + 0x1C0 + 32 + read-write + 0x79B076C + 0xFFFFFFFF + + + C3 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + C2 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC2_CTRL + Color Space Conversion Control Register. + 0x1D0 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + BYPASS + no description available + 0 + 1 + read-write + + + CSC_MODE + no description available + 1 + 2 + read-write + + + 0 + YUV2RGB + #0 + + + 1 + YCbCr2RGB + #1 + + + 10 + RGB2YUV + #10 + + + 11 + RGB2YCbCr + #11 + + + + + RSVD + no description available + 3 + 29 + read-only + + + + + CSC2_COEF0 + Color Space Conversion Coefficient Register 0 + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A1 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + A2 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC2_COEF1 + Color Space Conversion Coefficient Register 1 + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + A3 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + B1 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC2_COEF2 + Color Space Conversion Coefficient Register 2 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + B2 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + B3 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC2_COEF3 + Color Space Conversion Coefficient Register 3 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + C1 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + C2 + no description available + 16 + 11 + read-write + + + RSVD1 + no description available + 27 + 5 + read-only + + + + + CSC2_COEF4 + Color Space Conversion Coefficient Register 4 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + C3 + no description available + 0 + 11 + read-write + + + RSVD0 + no description available + 11 + 5 + read-only + + + D1 + no description available + 16 + 9 + read-write + + + RSVD1 + no description available + 25 + 7 + read-only + + + + + CSC2_COEF5 + Color Space Conversion Coefficient Register 5 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + D2 + no description available + 0 + 9 + read-write + + + RSVD0 + no description available + 9 + 7 + read-only + + + D3 + no description available + 16 + 9 + read-write + + + RSVD1 + no description available + 25 + 7 + read-only + + + + + LUT_CTRL + Lookup Table Control Register. + 0x240 + 32 + read-write + 0x80010000 + 0xFFFFFFFF + + + DMA_START + no description available + 0 + 1 + read-write + + + RSVD0 + no description available + 1 + 7 + read-only + + + INVALID + no description available + 8 + 1 + read-write + + + LRU_UPD + no description available + 9 + 1 + read-write + + + SEL_8KB + no description available + 10 + 1 + read-write + + + RSVD1 + no description available + 11 + 5 + read-only + + + OUT_MODE + no description available + 16 + 2 + read-write + + + 0 + RESERVED + #0 + + + 1 + Y8 + #1 + + + 10 + RGBW4444CFA + #10 + + + 11 + RGB888 + #11 + + + + + RSVD2 + no description available + 18 + 6 + read-only + + + LOOKUP_MODE + no description available + 24 + 2 + read-write + + + 0 + CACHE_RGB565 + #0 + + + 1 + DIRECT_Y8 + #1 + + + 10 + DIRECT_RGB444 + #10 + + + 11 + DIRECT_RGB454 + #11 + + + + + RSVD3 + no description available + 26 + 5 + read-only + + + BYPASS + no description available + 31 + 1 + read-write + + + + + LUT_ADDR + Lookup Table Control Register. + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 14 + read-write + + + RSVD1 + no description available + 14 + 2 + read-only + + + NUM_BYTES + no description available + 16 + 15 + read-write + + + RSVD2 + no description available + 31 + 1 + read-only + + + + + LUT_DATA + Lookup Table Data Register. + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + LUT_EXTMEM + Lookup Table External Memory Address Register. + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 32 + read-write + + + + + CFA + Color Filter Array Register. + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + HIST_CTRL + Histogram Control Register. + 0x290 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + STATUS + no description available + 0 + 4 + read-write + + + PANEL_MODE + no description available + 4 + 2 + read-write + + + 0 + GRAY4 + #0 + + + 1 + GRAY8 + #1 + + + 10 + GRAY16 + #10 + + + 11 + GRAY32 + #11 + + + + + RSVD + no description available + 6 + 26 + read-only + + + + + HIST2_PARAM + 2-level Histogram Parameter Register. + 0x2A0 + 32 + read-write + 0xF00 + 0xFFFFFFFF + + + VALUE0 + no description available + 0 + 5 + read-write + + + RSVD0 + no description available + 5 + 3 + read-only + + + VALUE1 + no description available + 8 + 5 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + RSVD + no description available + 16 + 16 + read-only + + + + + HIST4_PARAM + 4-level Histogram Parameter Register. + 0x2B0 + 32 + read-write + 0xF0A0500 + 0xFFFFFFFF + + + VALUE0 + no description available + 0 + 5 + read-write + + + RSVD0 + no description available + 5 + 3 + read-only + + + VALUE1 + no description available + 8 + 5 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + VALUE2 + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + VALUE3 + no description available + 24 + 5 + read-write + + + RSVD3 + no description available + 29 + 3 + read-only + + + + + HIST8_PARAM0 + 8-level Histogram Parameter 0 Register. + 0x2C0 + 32 + read-write + 0x6044000 + 0xFFFFFFFF + + + VALUE0 + no description available + 0 + 5 + read-write + + + RSVD0 + no description available + 5 + 3 + read-only + + + VALUE1 + no description available + 8 + 5 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + VALUE2 + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + VALUE3 + no description available + 24 + 5 + read-write + + + RSVD3 + no description available + 29 + 3 + read-only + + + + + HIST8_PARAM1 + 8-level Histogram Parameter 1 Register. + 0x2D0 + 32 + read-write + 0xF0D0B09 + 0xFFFFFFFF + + + VALUE4 + no description available + 0 + 5 + read-write + + + RSVD4 + no description available + 5 + 3 + read-only + + + VALUE5 + no description available + 8 + 5 + read-write + + + RSVD5 + no description available + 13 + 3 + read-only + + + VALUE6 + no description available + 16 + 5 + read-write + + + RSVD6 + no description available + 21 + 3 + read-only + + + VALUE7 + no description available + 24 + 5 + read-write + + + RSVD7 + no description available + 29 + 3 + read-only + + + + + HIST16_PARAM0 + 16-level Histogram Parameter 0 Register. + 0x2E0 + 32 + read-write + 0x3020100 + 0xFFFFFFFF + + + VALUE0 + no description available + 0 + 5 + read-write + + + RSVD0 + no description available + 5 + 3 + read-only + + + VALUE1 + no description available + 8 + 5 + read-write + + + RSVD1 + no description available + 13 + 3 + read-only + + + VALUE2 + no description available + 16 + 5 + read-write + + + RSVD2 + no description available + 21 + 3 + read-only + + + VALUE3 + no description available + 24 + 5 + read-write + + + RSVD3 + no description available + 29 + 3 + read-only + + + + + HIST16_PARAM1 + 16-level Histogram Parameter 1 Register. + 0x2F0 + 32 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read-only + + + VALUE11 + no description available + 24 + 5 + read-write + + + RSVD11 + no description available + 29 + 3 + read-only + + + + + HIST16_PARAM3 + 16-level Histogram Parameter 3 Register. + 0x310 + 32 + read-write + 0xF0E0D0C + 0xFFFFFFFF + + + VALUE12 + no description available + 0 + 5 + read-write + + + RSVD12 + no description available + 5 + 3 + read-only + + + VALUE13 + no description available + 8 + 5 + read-write + + + RSVD13 + no description available + 13 + 3 + read-only + + + VALUE14 + no description available + 16 + 5 + read-write + + + RSVD14 + no description available + 21 + 3 + read-only + + + VALUE15 + no description available + 24 + 5 + read-write + + + RSVD15 + no description available + 29 + 3 + read-only + + + + + POWER + PXP Power Control Register. + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUT_LP_STATE_WAY0_BANK0 + no description available + 0 + 3 + read-write + + + 0 + NONE + #0 + + + 1 + LS + #1 + + + 10 + DS + #10 + + + 100 + SD + #100 + + + + + LUT_LP_STATE_WAY0_BANKN + no description available + 3 + 3 + read-write + + + 0 + NONE + #0 + + + 1 + LS + #1 + + + 10 + DS + #10 + + + 100 + SD + #100 + + + + + LUT_LP_STATE_WAY1_BANKN + no description available + 6 + 3 + read-write + + + 0 + NONE + #0 + + + 1 + LS + #1 + + + 10 + DS + #10 + + + 100 + SD + #100 + + + + + ROT_MEM_LP_STATE + no description available + 9 + 3 + read-write + + + 0 + NONE + #0 + + + 1 + LS + #1 + + + 10 + DS + #10 + + + 100 + SD + #100 + + + + + CTRL + no description available + 12 + 20 + read-write + + + + + NEXT + Next Frame Pointer + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLED + no description available + 0 + 1 + read-only + + + RSVD + no description available + 1 + 1 + read-only + + + POINTER + no description available + 2 + 30 + read-write + + + + + + + EPDC + EPDC Register Reference Index + EPDC_ + 0x20F4000 + + 0 + 0xC24 + registers + + + + CTRL + EPDC Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + BURST_LEN_8 + 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description available + 14 + 2 + read-write + + + 0 + STANDARD + #0 + + + 1 + FLIP_PIXELS + #1 + + + + + NUM_CE + no description available + 16 + 4 + read-write + + + SDSHR + no description available + 20 + 1 + read-write + + + SDCLK_HOLD + no description available + 21 + 1 + read-write + + + RSVD0 + no description available + 22 + 10 + read-only + + + + + TCE_GDCFG + EPDC Timing Control Engine Gate-Driver Config Register + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDSP_MODE + no description available + 0 + 1 + read-write + + + GDOE_MODE + no description available + 1 + 1 + read-write + + + RSVD0 + no description available + 2 + 2 + read-only + + + GDRL + no description available + 4 + 1 + read-write + + + RSVD1 + no description available + 5 + 11 + read-only + + + PERIOD_VSCAN + no description available + 16 + 16 + read-write + + + + + TCE_GDCFG_SET + EPDC Timing Control Engine Gate-Driver Config Register + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDSP_MODE + no description available + 0 + 1 + read-write + + + GDOE_MODE + no description available + 1 + 1 + read-write + + + RSVD0 + no description available + 2 + 2 + read-only + + + GDRL + no description available + 4 + 1 + read-write + + + RSVD1 + no description available + 5 + 11 + read-only + + + PERIOD_VSCAN + no description available + 16 + 16 + read-write + + + + + TCE_GDCFG_CLR + EPDC Timing Control Engine Gate-Driver Config Register + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDSP_MODE + no description available + 0 + 1 + read-write + + + GDOE_MODE + no description available + 1 + 1 + read-write + + + RSVD0 + no description available + 2 + 2 + read-only + + + GDRL + no description available + 4 + 1 + read-write + + + RSVD1 + no description available + 5 + 11 + read-only + + + PERIOD_VSCAN + no description available + 16 + 16 + read-write + + + + + TCE_GDCFG_TOG + EPDC Timing Control Engine Gate-Driver Config Register + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + GDSP_MODE + no description available + 0 + 1 + read-write + + + GDOE_MODE + no description available + 1 + 1 + read-write + + + RSVD0 + no description available + 2 + 2 + read-only + + + GDRL + no description available + 4 + 1 + read-write + + + RSVD1 + no description available + 5 + 11 + read-only + + + PERIOD_VSCAN + no description available + 16 + 16 + read-write + + + + + TCE_HSCAN1 + EPDC Timing Control Engine Horizontal Timing Register 1 + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_SYNC + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_SYNC_WIDTH + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN1_SET + EPDC Timing Control Engine Horizontal Timing Register 1 + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_SYNC + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_SYNC_WIDTH + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN1_CLR + EPDC Timing Control Engine Horizontal Timing Register 1 + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_SYNC + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_SYNC_WIDTH + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN1_TOG + EPDC Timing Control Engine Horizontal Timing Register 1 + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_SYNC + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_SYNC_WIDTH + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN2 + EPDC Timing Control Engine Horizontal Timing Register 2 + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_BEGIN + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_END + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN2_SET + EPDC Timing Control Engine Horizontal Timing Register 2 + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_BEGIN + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_END + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN2_CLR + EPDC Timing Control Engine Horizontal Timing Register 2 + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_BEGIN + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_END + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_HSCAN2_TOG + EPDC Timing Control Engine Horizontal Timing Register 2 + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + LINE_BEGIN + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LINE_END + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + TCE_VSCAN + EPDC Timing Control Engine Vertical Timing Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_SYNC + no description available + 0 + 8 + read-write + + + FRAME_BEGIN + no description available + 8 + 8 + read-write + + + FRAME_END + no description available + 16 + 8 + read-write + + + RSVD0 + no description available + 24 + 8 + read-only + + + + + TCE_VSCAN_SET + EPDC Timing Control Engine Vertical Timing Register + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_SYNC + no description available + 0 + 8 + read-write + + + FRAME_BEGIN + no description available + 8 + 8 + read-write + + + FRAME_END + no description available + 16 + 8 + read-write + + + RSVD0 + no description available + 24 + 8 + read-only + + + + + TCE_VSCAN_CLR + EPDC Timing Control Engine Vertical Timing Register + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_SYNC + no description available + 0 + 8 + read-write + + + FRAME_BEGIN + no description available + 8 + 8 + read-write + + + FRAME_END + no description available + 16 + 8 + read-write + + + RSVD0 + no description available + 24 + 8 + read-only + + + + + TCE_VSCAN_TOG + EPDC Timing Control Engine Vertical Timing Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_SYNC + no description available + 0 + 8 + read-write + + + FRAME_BEGIN + no description available + 8 + 8 + read-write + + + FRAME_END + no description available + 16 + 8 + read-write + + + RSVD0 + no description available + 24 + 8 + read-only + + + + + TCE_OE + EPDC Timing Control Engine OE timing control Register + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDOEZ_DLY + no description available + 0 + 8 + read-write + + + SDOEZ_WIDTH + no description available + 8 + 8 + read-write + + + SDOED_DLY + no description available + 16 + 8 + read-write + + + SDOED_WIDTH + no description available + 24 + 8 + read-write + + + + + TCE_OE_SET + EPDC Timing Control Engine OE timing control Register + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDOEZ_DLY + no description available + 0 + 8 + read-write + + + SDOEZ_WIDTH + no description available + 8 + 8 + read-write + + + SDOED_DLY + no description available + 16 + 8 + read-write + + + SDOED_WIDTH + no description available + 24 + 8 + read-write + + + + + TCE_OE_CLR + EPDC Timing Control Engine OE timing control Register + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDOEZ_DLY + no description available + 0 + 8 + read-write + + + SDOEZ_WIDTH + no description available + 8 + 8 + read-write + + + SDOED_DLY + no description available + 16 + 8 + read-write + + + SDOED_WIDTH + no description available + 24 + 8 + read-write + + + + + TCE_OE_TOG + EPDC Timing Control Engine OE timing control Register + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + SDOEZ_DLY + no description available + 0 + 8 + read-write + + + SDOEZ_WIDTH + no description available + 8 + 8 + read-write + + + SDOED_DLY + no description available + 16 + 8 + read-write + + + SDOED_WIDTH + no description available + 24 + 8 + read-write + + + + + TCE_POLARITY + EPDC Timing Control Engine Driver Polarity Register + 0x2E0 + 32 + read-write + 0x1E + 0xFFFFFFFF + + + SDCE_POL + no description available + 0 + 1 + read-write + + + SDLE_POL + no description available + 1 + 1 + read-write + + + SDOE_POL + no description available + 2 + 1 + read-write + + + GDOE_POL + no description available + 3 + 1 + read-write + + + GDSP_POL + no description available + 4 + 1 + read-write + + + RSVD0 + no description available + 5 + 27 + read-only + + + + + TCE_TIMING1 + EPDC Timing Control Engine Timing Register 1 + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDCLK_SHIFT + no description available + 0 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD0 + no description available + 2 + 1 + read-only + + + SDCLK_INVERT + no description available + 3 + 1 + read-write + + + SDLE_SHIFT + no description available + 4 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD1 + no description available + 6 + 26 + read-only + + + + + TCE_TIMING1_SET + EPDC Timing Control Engine Timing Register 1 + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDCLK_SHIFT + no description available + 0 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD0 + no description available + 2 + 1 + read-only + + + SDCLK_INVERT + no description available + 3 + 1 + read-write + + + SDLE_SHIFT + no description available + 4 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD1 + no description available + 6 + 26 + read-only + + + + + TCE_TIMING1_CLR + EPDC Timing Control Engine Timing Register 1 + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDCLK_SHIFT + no description available + 0 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD0 + no description available + 2 + 1 + read-only + + + SDCLK_INVERT + no description available + 3 + 1 + read-write + + + SDLE_SHIFT + no description available + 4 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD1 + no description available + 6 + 26 + read-only + + + + + TCE_TIMING1_TOG + EPDC Timing Control Engine Timing Register 1 + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + SDCLK_SHIFT + no description available + 0 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD0 + no description available + 2 + 1 + read-only + + + SDCLK_INVERT + no description available + 3 + 1 + read-write + + + SDLE_SHIFT + no description available + 4 + 2 + read-write + + + 0 + NONE + #0 + + + 1 + ONE + #1 + + + 10 + TWO + #10 + + + 11 + THREE + #11 + + + + + RSVD1 + no description available + 6 + 26 + read-only + + + + + TCE_TIMING2 + EPDC Timing Control Engine Timing Register 2 + 0x310 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDSP_OFFSET + no description available + 0 + 16 + read-write + + + GDCLK_HP + no description available + 16 + 16 + read-write + + + + + TCE_TIMING2_SET + EPDC Timing Control Engine Timing Register 2 + 0x314 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDSP_OFFSET + no description available + 0 + 16 + read-write + + + GDCLK_HP + no description available + 16 + 16 + read-write + + + + + TCE_TIMING2_CLR + EPDC Timing Control Engine Timing Register 2 + 0x318 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDSP_OFFSET + no description available + 0 + 16 + read-write + + + GDCLK_HP + no description available + 16 + 16 + read-write + + + + + TCE_TIMING2_TOG + EPDC Timing Control Engine Timing Register 2 + 0x31C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDSP_OFFSET + no description available + 0 + 16 + read-write + + + GDCLK_HP + no description available + 16 + 16 + read-write + + + + + TCE_TIMING3 + EPDC Timing Control Engine Timing Register 3 + 0x320 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDCLK_OFFSET + no description available + 0 + 16 + read-write + + + GDOE_OFFSET + no description available + 16 + 16 + read-write + + + + + TCE_TIMING3_SET + EPDC Timing Control Engine Timing Register 3 + 0x324 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDCLK_OFFSET + no description available + 0 + 16 + read-write + + + GDOE_OFFSET + no description available + 16 + 16 + read-write + + + + + TCE_TIMING3_CLR + EPDC Timing Control Engine Timing Register 3 + 0x328 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDCLK_OFFSET + no description available + 0 + 16 + read-write + + + GDOE_OFFSET + no description available + 16 + 16 + read-write + + + + + TCE_TIMING3_TOG + EPDC Timing Control Engine Timing Register 3 + 0x32C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + GDCLK_OFFSET + no description available + 0 + 16 + read-write + + + GDOE_OFFSET + no description available + 16 + 16 + read-write + + + + + PIGEON_CTRL0 + EPDC Pigeon Mode Control Register 0 + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LD_PERIOD + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL0_SET + EPDC Pigeon Mode Control Register 0 + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LD_PERIOD + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL0_CLR + EPDC Pigeon Mode Control Register 0 + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LD_PERIOD + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL0_TOG + EPDC Pigeon Mode Control Register 0 + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + FD_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + LD_PERIOD + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL1 + EPDC Pigeon Mode Control Register 1 + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + FRAME_CNT_CYCLES + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL1_SET + EPDC Pigeon Mode Control Register 1 + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + FRAME_CNT_CYCLES + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL1_CLR + EPDC Pigeon Mode Control Register 1 + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + FRAME_CNT_CYCLES + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + PIGEON_CTRL1_TOG + EPDC Pigeon Mode Control Register 1 + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRAME_CNT_PERIOD + no description available + 0 + 12 + read-write + + + RSVD0 + no description available + 12 + 4 + read-only + + + FRAME_CNT_CYCLES + no description available + 16 + 12 + read-write + + + RSVD1 + no description available + 28 + 4 + read-only + + + + + IRQ_MASK1 + EPDC IRQ Mask Register for LUT 0~31 + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK1_SET + EPDC IRQ Mask Register for LUT 0~31 + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK1_CLR + EPDC IRQ Mask Register for LUT 0~31 + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK1_TOG + EPDC IRQ Mask Register for LUT 0~31 + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK2 + EPDC IRQ Mask Register for LUT 32~63 + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK2_SET + EPDC IRQ Mask Register for LUT 32~63 + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK2_CLR + EPDC IRQ Mask Register for LUT 32~63 + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ_MASK2_TOG + EPDC IRQ Mask Register for LUT 32~63 + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ_EN + no description available + 0 + 32 + read-write + + + + + IRQ1 + EPDC Interrupt Register for LUT 0~31 + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ1_SET + EPDC Interrupt Register for LUT 0~31 + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ1_CLR + EPDC Interrupt Register for LUT 0~31 + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ1_TOG + EPDC Interrupt Register for LUT 0~31 + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ2 + EPDC Interrupt Registerr for LUT 32~63 + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ2_SET + EPDC Interrupt Registerr for LUT 32~63 + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ2_CLR + EPDC Interrupt Registerr for LUT 32~63 + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ2_TOG + EPDC Interrupt Registerr for LUT 32~63 + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + LUTN_CMPLT_IRQ + no description available + 0 + 32 + read-write + + + + + IRQ_MASK + EPDC IRQ Mask Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + COL_IRQ_EN + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ_EN + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ_EN + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ_EN + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ_EN + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ_EN + no description available + 22 + 1 + read-write + + + PWR_IRQ_EN + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ_MASK_SET + EPDC IRQ Mask Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + COL_IRQ_EN + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ_EN + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ_EN + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ_EN + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ_EN + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ_EN + no description available + 22 + 1 + read-write + + + PWR_IRQ_EN + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ_MASK_CLR + EPDC IRQ Mask Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + COL_IRQ_EN + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ_EN + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ_EN + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ_EN + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ_EN + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ_EN + no description available + 22 + 1 + read-write + + + PWR_IRQ_EN + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ_MASK_TOG + EPDC IRQ Mask Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ_EN + no description available + 16 + 1 + read-write + + + COL_IRQ_EN + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ_EN + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ_EN + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ_EN + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ_EN + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ_EN + no description available + 22 + 1 + read-write + + + PWR_IRQ_EN + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ + EPDC Interrupt Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ + no description available + 16 + 1 + read-write + + + LUT_COL_IRQ + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ + no description available + 22 + 1 + read-write + + + PWR_IRQ + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ_SET + EPDC Interrupt Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ + no description available + 16 + 1 + read-write + + + LUT_COL_IRQ + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ + no description available + 18 + 1 + read-write + + + FRAME_END_IRQ + no description available + 19 + 1 + read-write + + + BUS_ERROR_IRQ + no description available + 20 + 1 + read-write + + + TCE_IDLE_IRQ + no description available + 21 + 1 + read-write + + + UPD_DONE_IRQ + no description available + 22 + 1 + read-write + + + PWR_IRQ + no description available + 23 + 1 + read-write + + + RSVD1 + no description available + 24 + 8 + read-only + + + + + IRQ_CLR + EPDC Interrupt Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + no description available + 0 + 16 + read-only + + + WB_CMPLT_IRQ + no description available + 16 + 1 + read-write + + + LUT_COL_IRQ + no description available + 17 + 1 + read-write + + + TCE_UNDERRUN_IRQ + no description available + 18 + 1 + read-write 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description available + 2 + 2 + read-write + + + 0 + PCLK + #0 + + + 1 + LINE + #1 + + + 10 + FRAME + #10 + + + 11 + SIG_ANOTHER + #11 + + + + + OFFSET + no description available + 4 + 4 + read-write + + + MASK_CNT_SEL + no description available + 8 + 4 + read-write + + + 0 + HSTATE_CNT + #0 + + + 1 + HSTATE_CYCLE + #1 + + + 10 + VSTATE_CNT + #10 + + + 11 + VSTATE_CYCLE + #11 + + + 100 + FRAME_CNT + #100 + + + 101 + FRAME_CYCLE + #101 + + + 110 + HCNT + #110 + + + 111 + VCNT + #111 + + + + + MASK_CNT + no description available + 12 + 12 + read-write + + + STATE_MASK + no description available + 24 + 8 + read-write + + + 1 + FS + #1 + + + 10 + FB + #10 + + + 100 + FD + #100 + + + 1000 + FE + #1000 + + + 10000 + LS + #10000 + + + 100000 + LB + #100000 + + + 1000000 + LD + #1000000 + + + 10000000 + LE + #10000000 + + + + + + + PIGEON_15_1 + Panel Interface Signal Generator Register 15_1 + 0xBD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + no description available + 0 + 16 + read-write + + + 0 + START_ACTIVE + #0 + + + + + CLR_CNT + no description available + 16 + 16 + read-write + + + 0 + CLEAR_USING_MASK + #0 + + + + + + + PIGEON_15_2 + Panel Interface Signal Generator Register 15_1 + 0xBE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + no description available + 0 + 4 + read-write + + + 0 + DIS + #0 + + + 1 + AND + #1 + + + 10 + OR + #10 + + + 11 + MASK + #11 + + + + + SIG_ANOTHER + no description available + 4 + 5 + read-write + + + RSVD0 + no description available + 9 + 23 + read-only + + + + + PIGEON_16_0 + Panel Interface Signal Generator Register 16_0 + 0xC00 + 32 + read-write + 0xF00 + 0xFFFFFFFF + + + EN + no description available + 0 + 1 + read-write + + + POL + no description available + 1 + 1 + read-write + + + 0 + ACTIVE_HIGH + #0 + + + 1 + ACTIVE_LOW + #1 + + + + + INC_SEL + no description available + 2 + 2 + read-write + + + 0 + PCLK + #0 + + + 1 + LINE + #1 + + + 10 + FRAME + #10 + + + 11 + SIG_ANOTHER + #11 + + + + + OFFSET + no description available + 4 + 4 + read-write + + + MASK_CNT_SEL + no description available + 8 + 4 + read-write + + + 0 + HSTATE_CNT + #0 + + + 1 + HSTATE_CYCLE + #1 + + + 10 + VSTATE_CNT + #10 + + + 11 + VSTATE_CYCLE + #11 + + + 100 + FRAME_CNT + #100 + + + 101 + FRAME_CYCLE + #101 + + + 110 + HCNT + #110 + + + 111 + VCNT + #111 + + + + + MASK_CNT + no description available + 12 + 12 + read-write + + + STATE_MASK + no description available + 24 + 8 + read-write + + + 1 + FS + #1 + + + 10 + FB + #10 + + + 100 + FD + #100 + + + 1000 + FE + #1000 + + + 10000 + LS + #10000 + + + 100000 + LB + #100000 + + + 1000000 + LD + #1000000 + + + 10000000 + LE + #10000000 + + + + + + + PIGEON_16_1 + Panel Interface Signal Generator Register 16_1 + 0xC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SET_CNT + no description available + 0 + 16 + read-write + + + 0 + START_ACTIVE + #0 + + + + + CLR_CNT + no description available + 16 + 16 + read-write + + + 0 + CLEAR_USING_MASK + #0 + + + + + + + PIGEON_16_2 + Panel Interface Signal Generator Register 16_1 + 0xC20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIG_LOGIC + no description available + 0 + 4 + read-write + + + 0 + DIS + #0 + + + 1 + AND + #1 + + + 10 + OR + #10 + + + 11 + MASK + #11 + + + + + SIG_ANOTHER + no description available + 4 + 5 + read-write + + + RSVD0 + no description available + 9 + 23 + read-only + + + + + + + USBC + USB + USBC_ + 0x2184000 + + 0 + 0x7AC + registers + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_ID + Identification register + 0 + 32 + read-only + 0xE401FA05 + 0xFFFFFFFF + + + ID + no description available + 0 + 6 + read-only + + + RESERVED + no description available + 6 + 2 + read-only + + + NID + no description available + 8 + 6 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + REVISION + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x15 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + PHYW + no description available + 4 + 2 + read-only + + + 00 + 8 bit wide data bus Software non-programmable + #00 + + + 01 + 16 bit wide data bus Software non-programmable + #01 + + + 10 + Reset to 8 bit wide data bus Software programmable + #10 + + + 11 + Reset to 16 bit wide data bus Software programmable + #11 + + + + + PHYM + no description available + 6 + 3 + read-only + + + 000 + UTMI/UMTI+ + #000 + + + 001 + ULPI DDR + #001 + + + 010 + ULPI + #010 + + + 011 + Serial Only + #011 + + + 100 + Software programmable - reset to UTMI/UTMI+ + #100 + + + 101 + Software programmable - reset to ULPI DDR + #101 + + + 110 + Software programmable - reset to ULPI + #110 + + + 111 + Software programmable - reset to Serial + #111 + + + + + SM + no description available + 9 + 2 + read-only + + + 00 + No Serial Engine, always use parallel signalling. + #00 + + + 01 + Serial Engine present, always use serial signalling for FS/LS. + #01 + + + 10 + Software programmable - Reset to use parallel signalling for FS/LS + #10 + + + 11 + Software programmable - Reset to use serial signalling for FS/LS + #11 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + no description available + 0 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + NPORT + no description available + 1 + 3 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + _HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + no description available + 0 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + DEVEP + no description available + 1 + 5 + read-only + + + RESERVED + no description available + 6 + 26 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + no description available + 0 + 8 + read-only + + + RESERVED + no description available + 8 + 8 + read-only + + + TXCHANADD + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + no description available + 0 + 8 + read-only + + + RXADD + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + no description available + 0 + 24 + read-write + + + GPTMODE + no description available + 24 + 1 + read-write + + + 0 + One Shot Mode + #0 + + + 1 + Repeat Mode + #1 + + + + + RESERVED + no description available + 25 + 5 + read-only + + + GPTRST + no description available + 30 + 1 + read-write + + + 0 + No action + #0 + + + 1 + Load counter value from GPTLD bits in n_GPTIMER0LD + #1 + + + + + GPTRUN + no description available + 31 + 1 + read-write + + + 0 + Stop counting + #0 + + + 1 + Run + #1 + + + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + no description available + 0 + 24 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + no description available + 0 + 24 + read-write + + + GPTMODE + no description available + 24 + 1 + read-write + + + 0 + One Shot Mode + #0 + + + 1 + Repeat Mode + #1 + + + + + RESERVED + no description available + 25 + 5 + read-only + + + GPTRST + no description available + 30 + 1 + read-write + + + 0 + No action + #0 + + + 1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + #1 + + + + + GPTRUN + no description available + 31 + 1 + read-write + + + 0 + Stop counting + #0 + + + 1 + Run + #1 + + + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + no description available + 0 + 3 + read-write + + + 000 + Incremental burst of unspecified length only + #000 + + + 001 + INCR4 burst, then single transfer + #001 + + + 010 + INCR8 burst, INCR4 burst, then single transfer + #010 + + + 011 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + #011 + + + 100 + Reserved, don't use + #100 + + + 101 + INCR4 burst, then incremental burst of unspecified length + #101 + + + 110 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + #110 + + + 111 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + #111 + + + + + RESERVED + no description available + 3 + 29 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + no description available + 0 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + no description available + 0 + 16 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + no description available + 0 + 4 + read-only + + + PPC + no description available + 4 + 1 + read-only + + + RESERVED + no description available + 5 + 3 + read-only + + + N_PCC + no description available + 8 + 4 + read-only + + + N_CC + no description available + 12 + 4 + read-only + + + 0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + #0 + + + 1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + #1 + + + + + PI + no description available + 16 + 1 + read-only + + + RESERVED + no description available + 17 + 3 + read-only + + + N_PTT + no description available + 20 + 4 + read-only + + + N_TT + no description available + 24 + 4 + read-only + + + RESERVED + no description available + 28 + 4 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + no description available + 0 + 1 + read-only + + + PFL + no description available + 1 + 1 + read-only + + + ASP + no description available + 2 + 1 + read-only + + + RESERVED + no description available + 3 + 1 + read-only + + + IST + no description available + 4 + 4 + read-only + + + EECP + no description available + 8 + 8 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + _DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + no description available + 0 + 16 + read-only + + + + + _DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + no description available + 0 + 5 + read-only + + + RESERVED + no description available + 5 + 2 + read-only + + + DC + no description available + 7 + 1 + read-only + + + HC + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 23 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + no description available + 0 + 1 + read-write + + + RST + no description available + 1 + 1 + read-write + + + FS_1 + no description available + 2 + 2 + read-write + + + PSE + no description available + 4 + 1 + read-write + + + 0 + Do not process the Periodic Schedule + #0 + + + 1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + #1 + + + + + ASE + no description available + 5 + 1 + read-write + + + 0 + Do not process the Asynchronous Schedule. + #0 + + + 1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + #1 + + + + + IAA + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + ASP + no description available + 8 + 2 + read-write + + + RESERVED + no description available + 10 + 1 + read-only + + + ASPE + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 1 + read-only + + + SUTW + no description available + 13 + 1 + read-write + + + ATDTW + no description available + 14 + 1 + read-write + + + FS_2 + no description available + 15 + 1 + read-write + + + 000 + 1024 elements (4096 bytes) Default value + #000 + + + 001 + 512 elements (2048 bytes) + #001 + + + + + ITC + no description available + 16 + 8 + read-write + + + 0 + Immediate (no threshold) + #0 + + + 1 + 1 micro-frame + #1 + + + 10 + 2 micro-frames + #10 + + + 100 + 4 micro-frames + #100 + + + 1000 + 8 micro-frames + #1000 + + + 10000 + 16 micro-frames + #10000 + + + 100000 + 32 micro-frames + #100000 + + + 1000000 + 64 micro-frames + #1000000 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + no description available + 0 + 1 + read-write + + + UEI + no description available + 1 + 1 + read-write + + + PCI + no description available + 2 + 1 + read-write + + + FRI + no description available + 3 + 1 + read-write + + + SEI + no description available + 4 + 1 + read-write + + + AAI + no description available + 5 + 1 + read-write + + + URI + no description available + 6 + 1 + read-write + + + SRI + no description available + 7 + 1 + read-write + + + SLI + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 1 + read-only + + + ULPII + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 1 + read-only + + + HCH + no description available + 12 + 1 + read-write + + + RCL + no description available + 13 + 1 + read-write + + + PS + no description available + 14 + 1 + read-write + + + AS + no description available + 15 + 1 + read-write + + + NAKI + no description available + 16 + 1 + read-only + + + RESERVED + no description available + 17 + 7 + read-only + + + TI0 + no description available + 24 + 1 + read-write + + + TI1 + no description available + 25 + 1 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + no description available + 0 + 1 + read-write + + + UEE + no description available + 1 + 1 + read-write + + + PCE + no description available + 2 + 1 + read-write + + + FRE + no description available + 3 + 1 + read-write + + + SEE + no description available + 4 + 1 + read-write + + + AAE + no description available + 5 + 1 + read-write + + + URE + no description available + 6 + 1 + read-write + + + SRE + no description available + 7 + 1 + read-write + + + SLE + no description available + 8 + 1 + read-write + + + RESERVED + no description available + 9 + 1 + read-only + + + ULPIE + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 5 + read-write + + + NAKE + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 1 + read-only + + + UAIE + no description available + 18 + 1 + read-write + + + UPIE + no description available + 19 + 1 + read-write + + + RESERVED + no description available + 20 + 4 + read-only + + + TIE0 + no description available + 24 + 1 + read-write + + + TIE1 + no description available + 25 + 1 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + no description available + 0 + 14 + read-write + + + 000 + (1024) 12 + #000 + + + 001 + (512) 11 + #001 + + + 010 + (256) 10 + #010 + + + 011 + (128) 9 + #011 + + + 100 + (64) 8 + #100 + + + 101 + (32) 7 + #101 + + + 110 + (16) 6 + #110 + + + 111 + (8) 5 + #111 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_PERIODICLISTBASE + Frame List Base Address + USBC + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + read-only + + + BASEADR + no description available + 12 + 20 + read-write + + + + + _DEVICEADDR + Device Address + USBC + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + USBADRA + no description available + 24 + 1 + read-write + + + USBADR + no description available + 25 + 7 + read-write + + + + + _ENDPTLISTADDR + Endpoint List Address + USBC + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + EPBASE + no description available + 11 + 21 + read-write + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_ASYNCLISTADDR + Next Asynch. Address + USBC + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 5 + read-only + + + ASYBASE + no description available + 5 + 27 + read-write + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXPBURST + no description available + 0 + 8 + read-write + + + TXPBURST + no description available + 8 + 9 + read-write + + + RESERVED + no description available + 17 + 15 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + TXSCHOH + no description available + 0 + 8 + read-write + + + TXSCHHEALTH + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + TXFIFOTHRES + no description available + 16 + 6 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + _ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + EPTN + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + _ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + EPTNE + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + no description available + 0 + 1 + read-only + + + 0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + #0 + + + 1 + Port routing control logic default-routes all ports to this host controller. + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + 4 + 0x200 + UOG,UH1,UH2,UH3 + %s_PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + no description available + 0 + 1 + read-only + + + CSC + no description available + 1 + 1 + read-write + + + PE + no description available + 2 + 1 + read-write + + + PEC + no description available + 3 + 1 + read-write + + + OCA + no description available + 4 + 1 + read-only + + + 1 + This port currently has an over-current condition + #1 + + + 0 + This port does not have an over-current condition. + #0 + + + + + OCC + no description available + 5 + 1 + read-write + + + FPR + no description available + 6 + 1 + read-write + + + SUSP + no description available + 7 + 1 + read-write + + + PR + no description available + 8 + 1 + read-write + + + HSP + no description available + 9 + 1 + read-only + + + LS + no description available + 10 + 2 + read-write + + + 00 + SE0 + #00 + + + 10 + J-state + #10 + + + 01 + K-state + #01 + + + 11 + Undefined + #11 + + + + + PP + no description available + 12 + 1 + read-write + + + PO + no description available + 13 + 1 + read-write + + + PIC + no description available + 14 + 2 + read-write + + + 00 + Port indicators are off + #00 + + + 01 + Amber + #01 + + + 10 + Green + #10 + + + 11 + Undefined + #11 + + + + + PTC + no description available + 16 + 4 + read-write + + + 0000 + TEST_MODE_DISABLE + #0000 + + + 0001 + J_STATE + #0001 + + + 0010 + K_STATE + #0010 + + + 0011 + SE0 (host) / NAK (device) + #0011 + + + 0100 + Packet + #0100 + + + 0101 + FORCE_ENABLE_HS + #0101 + + + 0110 + FORCE_ENABLE_FS + #0110 + + + 0111 + FORCE_ENABLE_LS + #0111 + + + + + WKCN + no description available + 20 + 1 + read-write + + + WKDC + no description available + 21 + 1 + read-write + + + WKOC + no description available + 22 + 1 + read-write + + + PHCD + no description available + 23 + 1 + read-write + + + 1 + Disable PHY clock + #1 + + + 0 + Enable PHY clock + #0 + + + + + PFSC + no description available + 24 + 1 + read-write + + + 1 + Forced to full speed + #1 + + + 0 + Normal operation + #0 + + + + + PTS_2 + no description available + 25 + 1 + read-write + + + PSPD + no description available + 26 + 2 + read-write + + + 00 + Full Speed + #00 + + + 01 + Low Speed + #01 + + + 10 + High Speed + #10 + + + 11 + Undefined + #11 + + + + + PTW + no description available + 28 + 1 + read-write + + + 0 + Select the 8-bit UTMI interface [60MHz] + #0 + + + 1 + Select the 16-bit UTMI interface [30MHz] + #1 + + + + + STS + no description available + 29 + 1 + read-write + + + PTS_1 + no description available + 30 + 2 + read-write + + + + + _OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x120 + 0xFFFFFFFF + + + VD + no description available + 0 + 1 + read-write + + + VC + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 1 + read-only + + + OT + no description available + 3 + 1 + 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Interrupt + 24 + 1 + read-write + + + RXF + Receive Frame Interrupt + 25 + 1 + read-write + + + TXB + Transmit Buffer Interrupt + 26 + 1 + read-write + + + TXF + Transmit Frame Interrupt + 27 + 1 + read-write + + + GRA + Graceful Stop Complete + 28 + 1 + read-write + + + BABT + Babbling Transmit Error + 29 + 1 + read-write + + + BABR + Babbling Receive Error + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 12 + write-only + + + RESERVED + no description available + 12 + 1 + read-only + + + RESERVED + no description available + 13 + 2 + read-only + + + TS_TIMER + TS_TIMER Interrupt Mask + 15 + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 16 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 17 + 1 + read-write + + + PLR + PLR Interrupt Mask + 18 + 1 + read-write + + + UN + UN Interrupt Mask + 19 + 1 + read-write + + + RL + RL Interrupt Mask + 20 + 1 + read-write + + + LC + LC Interrupt Mask + 21 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 22 + 1 + read-write + + + MII + MII Interrupt Mask + 23 + 1 + read-write + + + RXB + RXB Interrupt Mask + 24 + 1 + read-write + + + RXF + RXF Interrupt Mask + 25 + 1 + read-write + + + TXB + TXB Interrupt Mask + 26 + 1 + read-write + + + 0 + The corresponding interrupt source is masked. + #0 + + + 1 + The corresponding interrupt source is not masked. + #1 + + + + + TXF + TXF Interrupt Mask + 27 + 1 + read-write + + + 0 + The corresponding interrupt source is masked. + #0 + + + 1 + The corresponding interrupt source is not masked. + #1 + + + + + GRA + GRA Interrupt Mask + 28 + 1 + read-write + + + 0 + The corresponding interrupt source is masked. + #0 + + + 1 + The corresponding interrupt source is not masked. + #1 + + + + + BABT + BABT Interrupt Mask + 29 + 1 + read-write + + + 0 + The corresponding interrupt source is masked. + #0 + + + 1 + The corresponding interrupt source is not masked. + #1 + + + + + BABR + BABR Interrupt Mask + 30 + 1 + read-write + + + 0 + The corresponding interrupt source is masked. + #0 + + + 1 + The corresponding interrupt source is not masked. + #1 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + RDAR + Receive Descriptor Active Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + TDAR + Transmit Descriptor Active Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0xF0000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 1 + 1 + read-write + + + 0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + #0 + + + 1 + MAC is enabled, and reception and transmission are possible. + #1 + + + + + MAGICEN + Magic Packet Detection Enable + 2 + 1 + read-write + + + 0 + Magic detection logic disabled. + #0 + + + 1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + #1 + + + + + SLEEP + Sleep Mode Enable + 3 + 1 + read-write + + + 0 + Normal operating mode. + #0 + + + 1 + Sleep mode. + #1 + + + + + EN1588 + EN1588 Enable + 4 + 1 + read-write + + + 0 + Legacy FEC buffer descriptors and functions enabled. + #0 + + + 1 + Enhanced frame time-stamping functions enabled. + #1 + + + + + SPEED + no description available + 5 + 1 + read-write + + + 0 + 10/100 Mbps mode + #0 + + + 1 + 1000 Mbps mode + #1 + + + + + DBGEN + Debug Enable + 6 + 1 + read-write + + + 0 + MAC continues operation in debug mode. + #0 + + + 1 + MAC enters hardware freeze mode when the processor is in debug mode. + #1 + + + + + STOPEN + STOPEN Signal Control + 7 + 1 + read-write + + + DBSWP + Descriptor Byte Swapping Enable + 8 + 1 + read-write + + + 0 + The buffer descriptor bytes are not swapped to support big-endian devices + #0 + + + 1 + The buffer descriptor bytes are swapped to support little-endian devices + #1 + + + + + RESERVED + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 1 + read-only + + + RESERVED + no description available + 11 + 1 + read-only + + + RESERVED + no description available + 12 + 20 + read-only + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 16 + 2 + read-write + + + RA + Register Address + 18 + 5 + read-write + + + PA + PHY Address + 23 + 5 + read-write + + + OP + Operation Code + 28 + 2 + read-write + + + 00 + Write frame operation, but not MII compliant. + #00 + + + 01 + Write frame operation for a valid MII management frame. + #01 + + + 10 + Read frame operation for a valid MII management frame. + #10 + + + 11 + Read frame operation, but not MII compliant. + #11 + + + + + ST + Start Of Frame Delimiter + 30 + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + MII_SPEED + MII Speed + 1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 7 + 1 + read-write + + + 0 + Preamble enabled. + #0 + + + 1 + Preamble (32 ones) is not prepended to the MII management frame. + #1 + + + + + HOLDTIME + Holdtime On MDIO Output + 8 + 3 + read-write + + + 000 + 1 internal module clock cycle + #000 + + + 001 + 2 internal module clock cycles + #001 + + + 010 + 3 internal module clock cycles + #010 + + + 111 + 8 internal module clock cycles + #111 + + + + + RESERVED + no description available + 11 + 21 + read-only + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 29 + read-only + + + MIB_CLEAR + MIB Clear + 29 + 1 + read-write + + + MIB_IDLE + MIB Idle + 30 + 1 + read-only + + + MIB_DIS + Disable MIB Logic + 31 + 1 + read-write + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + 0 + Loopback disabled. + #0 + + + 1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + #1 + + + + + DRT + Disable Receive On Transmit + 1 + 1 + read-write + + + 0 + Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. + #0 + + + 1 + Disable reception of frames while transmitting. Normally used for half-duplex mode. + #1 + + + + + MII_MODE + Media Independent Interface Mode + 2 + 1 + read-write + + + 0 + Reserved. + #0 + + + 1 + MII or RMII mode, as indicated by the RMII_MODE field. + #1 + + + + + PROM + Promiscuous Mode + 3 + 1 + read-write + + + 0 + Disabled. + #0 + + + 1 + Enabled. + #1 + + + + + BC_REJ + Broadcast Frame Reject + 4 + 1 + read-write + + + FCE + Flow Control Enable + 5 + 1 + read-write + + + RGMII_EN + RGMII Mode Enable + 6 + 1 + read-write + + + 0 + MAC configured for non-RGMII operation + #0 + + + 1 + MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000 Mbps mode. If ECR[SPEED] is cleared, the MAC is in RGMII 10/100 Mbps mode. + #1 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + RMII_MODE + RMII Mode Enable + 8 + 1 + read-write + + + 0 + MAC configured for MII mode. + #0 + + + 1 + MAC configured for RMII operation. + #1 + + + + + RMII_10T + no description available + 9 + 1 + read-write + + + 0 + 100 Mbps operation. + #0 + + + 1 + 10 Mbps operation. + #1 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + PADEN + Enable Frame Padding Remove On Receive + 12 + 1 + read-write + + + 0 + No padding is removed on receive by the MAC. + #0 + + + 1 + Padding is removed from received frames. + #1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 13 + 1 + read-write + + + 0 + Pause frames are terminated and discarded in the MAC. + #0 + + + 1 + Pause frames are forwarded to the user application. + #1 + + + + + CRCFWD + Terminate/Forward Received CRC + 14 + 1 + read-write + + + 0 + The CRC field of received frames is transmitted to the user application. + #0 + + + 1 + The CRC field is stripped from the frame. + #1 + + + + + CFEN + MAC Control Frame Enable + 15 + 1 + read-write + + + 0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + #0 + + + 1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + #1 + + + + + MAX_FL + Maximum Frame Length + 16 + 14 + read-write + + + NLC + Payload Length Check Disable + 30 + 1 + read-write + + + 0 + The payload length check is disabled. + #0 + + + 1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field. + #1 + + + + + GRS + Graceful Receive Stopped + 31 + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 1 + read-only + + + FDEN + Full-Duplex Enable + 2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 3 + 1 + read-write + + + 0 + No PAUSE frame transmitted. + #0 + + + 1 + The MAC stops transmission of data frames after the current transmission is complete. + #1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 5 + 3 + read-write + + + 000 + Node MAC address programmed on PADDR1/2 registers. + #000 + + + 100 + Reserved. + #100 + + + 101 + Reserved. + #101 + + + 110 + Reserved. + #110 + + + + + ADDINS + Set MAC Address On Transmit + 8 + 1 + read-write + + + 0 + The source MAC address is not modified by the MAC. + #0 + + + 1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + #1 + + + + + CRCFWD + Forward Frame From Application With CRC + 9 + 1 + read-write + + + 0 + TxBD[TC] controls whether the frame has a CRC from the application. + #0 + + + 1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + #1 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + no description available + 16 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 16 + 16 + read-only + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + no description available + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + no description available + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + no description available + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + no description available + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + 000000 + 64 bytes written. + #000000 + + + 000001 + 64 bytes written. + #000001 + + + 000010 + 128 bytes written. + #000010 + + + 000011 + 192 bytes written. + #000011 + + + 111110 + 3968 bytes written. + #111110 + + + 111111 + 4032 bytes written. + #111111 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + STRFWD + Store And Forward Enable + 8 + 1 + read-write + + + 0 + Disabled, the transmission start threshold is programmed in TFWR. + #0 + + + 1 + Enabled. + #1 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + RDSR + Receive Descriptor Ring Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + R_DES_START + no description available + 3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 3 + read-only + + + X_DES_START + no description available + 3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + R_BUF_SIZE + no description available + 4 + 10 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + RESERVED + no description available + 16 + 5 + read-only + + + RESERVED + no description available + 21 + 11 + read-only + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value of The Transmit FIFO Almost Full Threshold + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 27 + read-only + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + RESERVED + no description available + 14 + 18 + read-only + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + 0 + Disabled. + #0 + + + 1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + #1 + + + + + RESERVED + no description available + 1 + 2 + read-only + + + IPCHK + no description available + 3 + 1 + read-write + + + 0 + Checksum is not inserted. + #0 + + + 1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + #1 + + + + + PROCHK + no description available + 4 + 1 + read-write + + + 0 + Checksum not inserted. + #0 + + + 1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + #1 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + 0 + Padding not removed. + #0 + + + 1 + Any bytes following the IP payload section of the frame are removed from the frame. + #1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 1 + 1 + read-write + + + 0 + Frames with wrong IPv4 header checksum are not discarded. + #0 + + + 1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + #1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 2 + 1 + read-write + + + 0 + Frames with wrong checksum are not discarded. + #0 + + + 1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + #1 + + + + + RESERVED + no description available + 3 + 3 + read-only + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 6 + 1 + read-write + + + 0 + Frames with errors are not discarded. + #0 + + + 1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + #1 + + + + + SHIFT16 + RX FIFO Shift-16 + 7 + 1 + read-write + + + 0 + Disabled. + #0 + + + 1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + ATCR + Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + 0 + The timer stops at the current value. + #0 + + + 1 + The timer starts incrementing. + #1 + + + + + RESERVED + no description available + 1 + 1 + read-only + + + OFFEN + Enable One-Shot Offset Event + 2 + 1 + read-write + + + 0 + Disable. + #0 + + + 1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + #1 + + + + + OFFRST + Reset Timer On Offset Event + 3 + 1 + read-write + + + 0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + #0 + + + 1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + #1 + + + + + PEREN + Enable Periodical Event + 4 + 1 + read-write + + + 0 + Disable. + #0 + + + 1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + #1 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + PINPER + no description available + 7 + 1 + read-write + + + 0 + Disable. + #0 + + + 1 + Enable. + #1 + + + + + RESERVED + no description available + 8 + 1 + read-only + + + RESTART + Reset Timer + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-only + + + CAPTURE + Capture Timer Value + 11 + 1 + read-write + + + 0 + No effect. + #0 + + + 1 + The current time is captured and can be read from the ATVR register. + #1 + + + + + RESERVED + no description available + 12 + 1 + read-only + + + SLAVE + Enable Timer Slave Mode + 13 + 1 + read-write + + + 0 + The timer is active and all configuration fields in this register are relevant. + #0 + + + 1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + no description available + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + no description available + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + no description available + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + INC_CORR + Correction Increment Value + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 17 + read-only + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMESTAMP + no description available + 0 + 32 + read-write + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + + + 0 + Timer Flag for Channel 0 is clear + #0 + + + 1 + Timer Flag for Channel 0 is set + #1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 1 + 1 + read-write + + + 0 + Timer Flag for Channel 1 is clear + #0 + + + 1 + Timer Flag for Channel 1 is set + #1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 2 + 1 + read-write + + + 0 + Timer Flag for Channel 2 is clear + #0 + + + 1 + Timer Flag for Channel 2 is set + #1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 3 + 1 + read-write + + + 0 + Timer Flag for Channel 3 is clear + #0 + + + 1 + Timer Flag for Channel 3 is set + #1 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + 4 + 0x8 + 0,1,2,3 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + 0 + DMA request is disabled + #0 + + + 1 + DMA request is enabled + #1 + + + + + RESERVED + no description available + 1 + 1 + read-only + + + TMODE + Timer Mode + 2 + 4 + read-write + + + 0000 + Timer Channel is disabled. + #0000 + + + 0001 + Timer Channel is configured for Input Capture on rising edge + #0001 + + + 0010 + Timer Channel is configured for Input Capture on falling edge + #0010 + + + 0011 + Timer Channel is configured for Input Capture on both edges + #0011 + + + 0100 + Timer Channel is configured for Output Compare - software only + #0100 + + + 0101 + Timer Channel is configured for Output Compare - toggle output on compare + #0101 + + + 0110 + Timer Channel is configured for Output Compare - clear output on compare + #0110 + + + 0111 + Timer Channel is configured for Output Compare - set output on compare + #0111 + + + 1000 + Reserved + #1000 + + + 1010 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow + #1010 + + + 10x1 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow + #10x1 + + + 1100 + Reserved + #1100 + + + 1110 + Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle + #1110 + + + 1111 + Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle + #1111 + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + 0 + Interrupt is disabled + #0 + + + 1 + Interrupt is enabled + #1 + + + + + TF + Timer Flag + 7 + 1 + read-write + + + 0 + Input Capture or Output Compare has not occurred + #0 + + + 1 + Input Capture or Output Compare has occurred + #1 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + 4 + 0x8 + 0,1,2,3 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + MLB150 + MLB150 + MLB150_ + 0x218C000 + + 0 + 0x3E0 + registers + + + + MLBC0 + MediaLB Control 0 Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MLBEN + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 1 + read-only + + + MLBCLK_2_0 + no description available + 2 + 3 + read-write + + + 000 + 256xFs (for MLBPEN = 0) + #000 + + + 001 + 512xFs (for MLBPEN = 0) + #001 + + + 010 + 1024xFs (for MLBPEN = 0) + #010 + + + 011 + 2048xFs (for MLBPEN = 1) + #011 + + + 100 + 3072xFs (for MLBPEN = 1) + #100 + + + 101 + 4096xFs (for MLBPEN = 1) + #101 + + + 110 + 6144xFs (for MLBPEN = 1) + #110 + + + 111 + reserved + #111 + + + + + MLBPEN + no description available + 5 + 1 + read-write + + + 0 + MediaLB 3-pin interface enabled + #0 + + + 1 + MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case. + #1 + + + + + RESERVED + no description available + 6 + 1 + read-only + + + MLBLK + no description available + 7 + 1 + read-only + + + RESERVED + no description available + 8 + 4 + read-only + + + ASYRETRY + no description available + 12 + 1 + read-write + + + RESERVED + no description available + 13 + 1 + read-only + + + CTLRETRY + no description available + 14 + 1 + read-write + + + FCNT + no description available + 15 + 3 + read-write + + + 000 + 1 frame per sub-buffer (Operation is the same as Standard mode.) + #000 + + + 001 + 2 frames per sub-buffer + #001 + + + 010 + 4 frames per sub-buffer + #010 + + + 011 + 8 frames per sub-buffer + #011 + + + 100 + 16 frames per sub-buffer + #100 + + + 101 + 32 frames per sub-buffer + #101 + + + 110 + 64 frames per sub-buffer + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + MLBPC0 + MediaLB 6-pin Control 0 Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + MCLKHYS + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + MS0 + MediaLB Channel Status 0 Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + MCS_31_0 + no description available + 0 + 32 + read-only + + + + + MLBPC2 + MediaLB 6-pin Control 2 Register + 0xD + 32 + read-write + 0 + 0xFFFFFFFF + + + SDOPC + no description available + 0 + 1 + read-write + + + 0 + MLB_SIG / MLB_DATA launch at rising edge of MLB_CLK(default) + #0 + + + 1 + MLB_SIG / MLB_DATA launch at falling edge of MLB_CLK + #1 + + + + + SDRTO + no description available + 1 + 2 + read-write + + + RESERVED + Reserved. + 3 + 5 + read-only + + + MORCD + no description available + 8 + 7 + read-write + + + 0 + Divider factor is 1. + #0 + + + 1 + Divider factor is 2. + #1 + + + + + MORCE + no description available + 15 + 1 + read-write + + + 0 + Enable MLB output reference clock. + #0 + + + 1 + Disable MLB output reference clock. + #1 + + + + + RESERVED + Reserved. + 16 + 16 + read-only + + + + + MS1 + MediaLB Channel Status1 Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + MCS_63_32 + no description available + 0 + 32 + read-only + + + + + MSS + MediaLB System Status Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSTSYSCMD + no description available + 0 + 1 + read-only + + + LKSYSCMD + no description available + 1 + 1 + read-only + + + ULKSYSCMD + no description available + 2 + 1 + read-only + + + CSSYSCMD + no description available + 3 + 1 + read-only + + + SWSYSCMD + no description available + 4 + 1 + read-only + + + SERVREQ + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MSD + MediaLB System Data Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + SD0_7_0 + no description available + 0 + 8 + read-only + + + SD1_7_0 + no description available + 8 + 8 + read-only + + + SD2_7_0 + no description available + 16 + 8 + read-only + + + SD3_7_0 + no description available + 24 + 8 + read-only + + + + + MIEN + MediaLB Interrupt Enable Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ISOC_PE + no description available + 0 + 1 + read-write + + + ISOC_BUFO + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 14 + read-only + + + SYNC_PE + no description available + 16 + 1 + read-write + + + ARX_DONE + no description available + 17 + 1 + read-write + + + ARX_PE + no description available + 18 + 1 + read-write + + + ARX_BREAK + no description available + 19 + 1 + read-write + + + ATX_DONE + no description available + 20 + 1 + read-write + + + ATX_PE + no description available + 21 + 1 + read-write + + + ATX_BREAK + no description available + 22 + 1 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + CRX_DONE + no description available + 24 + 1 + read-write + + + CRX_PE + no description available + 25 + 1 + read-write + + + CRX_BREAK + no description available + 26 + 1 + read-write + + + CTX_DONE + no description available + 27 + 1 + read-write + + + CTX_PE + no description available + 28 + 1 + read-write + + + CTX_BREAK + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + MLBPC1 + MediaLB 6-pin Control 1 Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SDRCVBIAS_3_0 + no description available + 0 + 4 + read-write + + + SDXMTBIAS_3_0 + no description available + 4 + 4 + read-write + + + CKRCVBIAS_3_0 + no description available + 8 + 4 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + MLBC1 + MediaLB Control 1 Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 6 + read-only + + + LOCK + no description available + 6 + 1 + read-only + + + CLKM + no description available + 7 + 1 + read-only + + + NDA_7_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + HCTL + HBI Control Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST0 + no description available + 0 + 1 + read-write + + + 1 + reset + #1 + + + 0 + active + #0 + + + + + RST1 + no description available + 1 + 1 + read-write + + + 1 + reset + #1 + + + 0 + active + #0 + + + + + RESERVED + no description available + 2 + 13 + read-only + + + EN + no description available + 15 + 1 + read-write + + + 1 + enabled + #1 + + + 0 + disabled + #0 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + HCMR0 + HBI Channel Mask 0 Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHM_31_0_P + no description available + 0 + 32 + read-write + + + 0 + masked + #0 + + + 1 + unmasked + #1 + + + + + + + HCMR1 + HBI Channel Mask 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHM_63_32 + no description available + 0 + 32 + read-write + + + 0 + masked + #0 + + + 1 + unmasked + #1 + + + + + + + HCER0 + HBI Channel Error 0 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + CERR_31_0 + no description available + 0 + 32 + read-only + + + + + HCER1 + HBI Channel Error 1 Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + CERR_63_32 + no description available + 0 + 32 + read-only + + + + + HCBR0 + HBI Channel Busy 0 Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHB_31_0 + no description available + 0 + 32 + read-only + + + 0 + idle + #0 + + + 1 + busy + #1 + + + + + + + HCBR1 + HBI Channel Busy 1 Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + CHB_63_32 + no description available + 0 + 32 + read-only + + + 0 + idle + #0 + + + 1 + busy + #1 + + + + + + + MDAT0 + MIF Data 0 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_31_0 + no description available + 0 + 32 + read-write + + + + + MDAT1 + MIF Data 1 Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_63_32 + no description available + 0 + 32 + read-write + + + + + MDAT2 + MIF Data 2 Register + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_95_64 + no description available + 0 + 32 + read-write + + + + + MDAT3 + MIF Data 3 Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_127_96 + no description available + 0 + 32 + read-write + + + + + MDWE0 + MIF Data Write Enable 0 Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_31_0 + no description available + 0 + 32 + read-write + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + + + MDWE1 + MIF Data Write Enable 1 Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_63_32 + no description available + 0 + 32 + read-write + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + + + MDWE2 + MIF Data Write Enable 2 Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_95_64 + no description available + 0 + 32 + read-write + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + + + MDWE3 + MIF Data Write Enable 3 Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + MASK_127_96 + no description available + 0 + 32 + read-write + + + 0 + disabled + #0 + + + 1 + enabled + #1 + + + + + + + MCTL + MIF Control Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + XCMP + no description available + 0 + 1 + read-only + + + RESERVED + no description available + 1 + 31 + read-only + + + + + MADR + MIF Address Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR_7_0 + no description available + 0 + 8 + read-write + + + ADDR_13_8 + no description available + 8 + 6 + read-write + + + RESERVED + no description available + 14 + 16 + read-only + + + TB + no description available + 30 + 1 + read-write + + + 0 + selects CTR + #0 + + + 1 + selects DBR + #1 + + + + + WNR + no description available + 31 + 1 + read-write + + + 0 + read + #0 + + + 1 + write + #1 + + + + + + + ACTL + AHB Control Register + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCE + no description available + 0 + 1 + read-write + + + 0 + Hardware clears interrupt after a ACSRn register read + #0 + + + 1 + Software clears interrupt + #1 + + + + + SMX + no description available + 1 + 1 + read-write + + + 0 + ACSR0 generates an interrupt on ahb_int[0]; ACSR1 generates an interrupt on ahb_int[1] + #0 + + + 1 + ACSR0 and ACSR1 generate an interrupts on ahb_int[0] only + #1 + + + + + DMA_MODE + no description available + 2 + 1 + read-write + + + 0 + DMA Mode 0 + #0 + + + 1 + DMA Mode 1 + #1 + + + + + RESERVED + no description available + 3 + 1 + read-write + + + MPB + no description available + 4 + 1 + read-write + + + 0 + Single-packet mode + #0 + + + 1 + Multiple-packet mode + #1 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + ACSR0 + AHB Channel Status 0 Register + 0x3D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHS + no description available + 0 + 32 + read-only + + + 0 + None + #0 + + + 1 + Interrupt + #1 + + + + + + + ACSR1 + AHB Channel Status 1 Register + 0x3D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CHS + no description available + 0 + 32 + read-only + + + 0 + None + #0 + + + 1 + Interrupt + #1 + + + + + + + ACMR0 + AHB Channel Mask 0 Register + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHM_31_0 + no description available + 0 + 32 + read-write + + + 0 + Masked + #0 + + + 1 + Unmasked + #1 + + + + + + + ACMR1 + AHB Channel Mask 1 Register + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + CHM + no description available + 0 + 32 + read-write + + + 0 + Masked + #0 + + + 1 + Unmasked + #1 + + + + + + + + + uSDHC1 + uSDHC + uSDHC + uSDHC1_ + 0x2190000 + + 0 + 0xCC + registers + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + no description available + 0 + 13 + read-write + + + 1000 + 4096 Bytes + #1000 + + + 001 + 1 Byte + #001 + + + 000 + No data transfer + #000 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + BLKCNT + no description available + 16 + 16 + read-write + + + 0001 + 1 block + #0001 + + + 0000 + Stop Count + #0000 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + no description available + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RSPTYP + no description available + 16 + 2 + read-write + + + 00 + No Response + #00 + + + 01 + Response Length 136 + #01 + + + 10 + Response Length 48 + #10 + + + 11 + Response Length 48, check Busy after response + #11 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + CCCEN + no description available + 19 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + CICEN + no description available + 20 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DPSEL + no description available + 21 + 1 + read-write + + + 1 + Data Present + #1 + + + 0 + No Data Present + #0 + + + + + CMDTYP + no description available + 22 + 2 + read-write + + + 11 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + #11 + + + 10 + Resume CMD52 for writing Function Select in CCCR + #10 + + + 01 + Suspend CMD52 for writing Bus Suspend in CCCR + #01 + + + 00 + Normal Other commands + #00 + + + + + CMDINX + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + no description available + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + no description available + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + no description available + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + no description available + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + no description available + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIHB + no description available + 0 + 1 + read-only + + + 1 + Cannot issue command + #1 + + + 0 + Can issue command using only CMD line + #0 + + + + + CDIHB + no description available + 1 + 1 + read-only + + + 1 + Cannot issue command which uses the DATA line + #1 + + + 0 + Can issue command which uses the DATA line + #0 + + + + + DLA + no description available + 2 + 1 + read-only + + + 1 + DATA Line Active + #1 + + + 0 + DATA Line Inactive + #0 + + + + + SDSTB + no description available + 3 + 1 + read-only + + + 1 + clock is stable + #1 + + + 0 + clock is changing frequency and not stable + #0 + + + + + IPGOFF + no description available + 4 + 1 + read-only + + + 1 + ipg_clk is gated off + #1 + + + 0 + ipg_clk is active + #0 + + + + + HCKOFF + no description available + 5 + 1 + read-only + + + 1 + hclk is gated off + #1 + + + 0 + hclk is active + #0 + + + + + PEROFF + no description available + 6 + 1 + read-only + + + 1 + ipg_perclk is gated off + #1 + + + 0 + ipg_perclk is active + #0 + + + + + SDOFF + no description available + 7 + 1 + read-only + + + 1 + SD Clock is gated off + #1 + + + 0 + SD Clock is active + #0 + + + + + WTA + no description available + 8 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + RTA + no description available + 9 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + BWEN + no description available + 10 + 1 + read-only + + + 1 + Write enable + #1 + + + 0 + Write disable + #0 + + + + + BREN + no description available + 11 + 1 + read-only + + + 1 + Read enable + #1 + + + 0 + Read disable + #0 + + + + + RTR + no description available + 12 + 1 + read-only + + + 1 + Sampling clock needs re-tuning + #1 + + + 0 + Fixed or well tuned sampling clock + #0 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + CINST + no description available + 16 + 1 + read-only + + + 1 + Card Inserted + #1 + + + 0 + Power on Reset or No Card + #0 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + CDPL + no description available + 18 + 1 + read-only + + + 1 + Card present (CD_B=0) + #1 + + + 0 + No card present (CD_B=1) + #0 + + + + + WPSPL + no description available + 19 + 1 + read-only + + + 1 + Write enabled (WP=0) + #1 + + + 0 + Write protected (WP=1) + #0 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + CLSL + no description available + 23 + 1 + read-only + + + DLSL + no description available + 24 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + no description available + 0 + 1 + read-write + + + 1 + LED on + #1 + + + 0 + LED off + #0 + + + + + DTW + no description available + 1 + 2 + read-write + + + 10 + 8-bit mode + #10 + + + 01 + 4-bit mode + #01 + + + 00 + 1-bit mode + #00 + + + 11 + Reserved + #11 + + + + + D3CD + no description available + 3 + 1 + read-write + + + 1 + DATA3 as Card Detection Pin + #1 + + + 0 + DATA3 does not monitor Card Insertion + #0 + + + + + EMODE + no description available + 4 + 2 + read-write + + + 00 + Big Endian Mode + #00 + + + 01 + Half Word Big Endian Mode + #01 + + + 10 + Little Endian Mode + #10 + + + 11 + Reserved + #11 + + + + + CDTL + no description available + 6 + 1 + read-write + + + 1 + Card Detect Test Level is 1, card inserted + #1 + + + 0 + Card Detect Test Level is 0, no card inserted + #0 + + + + + CDSS + no description available + 7 + 1 + read-write + + + 1 + Card Detection Test Level is selected (for test purpose) + #1 + + + 0 + Card Detection Level is selected (for normal purpose) + #0 + + + + + DMASEL + no description available + 8 + 2 + read-write + + + 00 + No DMA or Simple DMA is selected + #00 + + + 01 + ADMA1 is selected + #01 + + + 10 + ADMA2 is selected + #10 + + + 11 + reserved + #11 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + SABGREQ + no description available + 16 + 1 + read-write + + + 1 + Stop + #1 + + + 0 + Transfer + #0 + + + + + CREQ + no description available + 17 + 1 + read-write + + + 1 + Restart + #1 + + + 0 + No effect + #0 + + + + + RWCTL + no description available + 18 + 1 + read-write + + + 1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + #1 + + + 0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + #0 + + + + + IABG + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Disabled + #0 + + + + + RD_DONE_NO_8CLK + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 3 + read-write + + + WECINT + no description available + 24 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECINS + no description available + 25 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECRM + no description available + 26 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BURST_LEN_EN + no description available + 27 + 3 + read-write + + + xx1 + Burst length is enabled for INCR + #xx1 + + + x1x + Burst length is enabled for INCR4/INCR8/INCR16 + #x1x + + + 1xx + Burst length is enabled for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP + #1xx + + + + + NON_EXACT_BLK_RD + no description available + 30 + 1 + read-write + + + 1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + #1 + + + 0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + #0 + + + + + RESERVED + no description available + 31 + 1 + read-write + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-write + + + DVS + no description available + 4 + 4 + read-write + + + 0000 + Divide-by-1 + #0000 + + + 0001 + Divide-by-2 + #0001 + + + 1110 + Divide-by-15 + #1110 + + + 1111 + Divide-by-16 + #1111 + + + + + SDCLKFS + no description available + 8 + 8 + read-write + + + DTOCV + no description available + 16 + 4 + read-write + + + 1111 + SDCLK x 2 28 + #1111 + + + 1110 + SDCLK x 2 2 7 + #1110 + + + 0001 + SDCLK x 2 14 + #0001 + + + 0000 + SDCLK x 2 1 3 + #0000 + + + + + RESERVED + no description available + 20 + 2 + read-only + + + RESERVED + no description available + 22 + 1 + read-only + + + IPP_RST_N + no description available + 23 + 1 + read-write + + + RSTA + no description available + 24 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTC + no description available + 25 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTD + no description available + 26 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + INITA + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + no description available + 0 + 1 + read-write + + + 1 + Command complete + #1 + + + 0 + Command not complete + #0 + + + + + TC + no description available + 1 + 1 + read-write + + + 1 + Transfer complete + #1 + + + 0 + Transfer not complete + #0 + + + + + BGE + no description available + 2 + 1 + read-write + + + 1 + Transaction stopped at block gap + #1 + + + 0 + No block gap event + #0 + + + + + DINT + no description available + 3 + 1 + read-write + + + 1 + DMA Interrupt is generated + #1 + + + 0 + No DMA Interrupt + #0 + + + + + BWR + no description available + 4 + 1 + read-write + + + 1 + Ready to write buffer: + #1 + + + 0 + Not ready to write buffer + #0 + + + + + BRR + no description available + 5 + 1 + read-write + + + 1 + Ready to read buffer + #1 + + + 0 + Not ready to read buffer + #0 + + + + + CINS + no description available + 6 + 1 + read-write + + + 1 + Card inserted + #1 + + + 0 + Card state unstable or removed + #0 + + + + + CRM + no description available + 7 + 1 + read-write + + + 1 + Card removed + #1 + + + 0 + Card state unstable or inserted + #0 + + + + + CINT + no description available + 8 + 1 + read-write + + + 1 + Generate Card Interrupt + #1 + + + 0 + No Card Interrupt + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTE + no description available + 12 + 1 + read-write + + + 1 + Re-Tuning should be performed + #1 + + + 0 + Re-Tuning is not required + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TP + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOE + no description available + 16 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + CCE + no description available + 17 + 1 + read-write + + + 1 + CRC Error Generated. + #1 + + + 0 + No Error + #0 + + + + + CEBE + no description available + 18 + 1 + read-write + + + 1 + End Bit Error Generated + #1 + + + 0 + No Error + #0 + + + + + CIE + no description available + 19 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DTOE + no description available + 20 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + DCE + no description available + 21 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DEBE + no description available + 22 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12E + no description available + 24 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNE + no description available + 26 + 1 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAE + no description available + 28 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0x157F413F + 0xFFFFFFFF + + + CCSEN + no description available + 0 + 1 + read-write + + + TCSEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGESEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTSEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRSEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRSEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSSEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMSEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTSEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTESEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPSEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOESEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCESEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBESEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIESEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOESEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCESEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBESEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12ESEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNESEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAESEN + no description available + 28 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + no description available + 0 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + TCIEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGEIEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTIEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRIEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRIEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSIEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMIEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTIEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTEIEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPIEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOEIEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCEIEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBEIEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIEIEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOEIEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCEIEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBEIEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12EIEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNEIEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAEIEN + no description available + 28 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + AC12NE + no description available + 0 + 1 + read-only + + + 1 + Not executed + #1 + + + 0 + Executed + #0 + + + + + AC12TOE + no description available + 1 + 1 + read-only + + + 1 + Time out + #1 + + + 0 + No error + #0 + + + + + AC12EBE + no description available + 2 + 1 + read-only + + + 1 + End Bit Error Generated + #1 + + + 0 + No error + #0 + + + + + AC12CE + no description available + 3 + 1 + read-only + + + 1 + CRC Error Met in Auto CMD12 Response + #1 + + + 0 + No CRC error + #0 + + + + + AC12IE + no description available + 4 + 1 + read-only + + + 1 + Error, the CMD index in response is not CMD12 + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + CNIBAC12E + no description available + 7 + 1 + read-only + + + 1 + Not Issued + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-only + 0x7F30000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MBL + no description available + 16 + 3 + read-only + + + 000 + 512 bytes + #000 + + + 001 + 1024 bytes + #001 + + + 010 + 2048 bytes + #010 + + + 011 + 4096 bytes + #011 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + ADMAS + no description available + 20 + 1 + read-only + + + 1 + Advanced DMA Supported + #1 + + + 0 + Advanced DMA Not supported + #0 + + + + + HSS + no description available + 21 + 1 + read-only + + + 1 + High Speed Supported + #1 + + + 0 + High Speed Not Supported + #0 + + + + + DMAS + no description available + 22 + 1 + read-only + + + 1 + DMA Supported + #1 + + + 0 + DMA not supported + #0 + + + + + SRS + no description available + 23 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + VS33 + no description available + 24 + 1 + read-only + + + 1 + 3.3V supported + #1 + + + 0 + 3.3V not supported + #0 + + + + + VS30 + no description available + 25 + 1 + read-only + + + 1 + 3.0V supported + #1 + + + 0 + 3.0V not supported + #0 + + + + + VS18 + no description available + 26 + 1 + read-only + + + 1 + 1.8V supported + #1 + + + 0 + 1.8V not supported + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + no description available + 0 + 8 + read-write + + + RD_BRST_LEN + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_WML + no description available + 16 + 8 + read-write + + + WR_BRST_LEN + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + no description available + 0 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BCEN + no description available + 1 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + AC12EN + no description available + 2 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DDR_EN + no description available + 3 + 1 + read-write + + + DTDSEL + no description available + 4 + 1 + read-write + + + 1 + Read (Card to Host) + #1 + + + 0 + Write (Host to Card) + #0 + + + + + MSBSEL + no description available + 5 + 1 + read-write + + + 1 + Multiple Blocks + #1 + + + 0 + Single Block + #0 + + + + + NIBBLE_POS + no description available + 6 + 1 + read-write + + + AC23EN + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 14 + read-only + + + EXE_TUNE + no description available + 22 + 1 + read-write + + + 1 + Execute Tuning + #1 + + + 0 + Not Tuned or Tuning Completed + #0 + + + + + SMP_CLK_SEL + no description available + 23 + 1 + read-write + + + 1 + Tuned clock is used to sample data/cmd + #1 + + + 0 + Fixed clock is used to sample data/cmd + #0 + + + + + AUTO_TUNE_EN + no description available + 24 + 1 + read-write + + + 1 + enable auto tuning + #1 + + + 0 + disable auto tuning + #0 + + + + + FBCLK_SEL + no description available + 25 + 1 + read-write + + + 1 + feedback clock comes from the ipp_card_clk_out + #1 + + + 0 + feedback clock comes from the loopback CLK + #0 + + + + + RESERVED + no description available + 26 + 3 + read-only + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-write + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + no description available + 0 + 1 + write-only + + + FEVTAC12TOE + no description available + 1 + 1 + write-only + + + FEVTAC12CE + no description available + 2 + 1 + write-only + + + FEVTAC12EBE + no description available + 3 + 1 + write-only + + + FEVTAC12IE + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 2 + read-only + + + FEVTCNIBAC12E + no description available + 7 + 1 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + FEVTCTOE + no description available + 16 + 1 + write-only + + + FEVTCCE + no description available + 17 + 1 + write-only + + + FEVTCEBE + no description available + 18 + 1 + write-only + + + FEVTCIE + no description available + 19 + 1 + write-only + + + FEVTDTOE + no description available + 20 + 1 + write-only + + + FEVTDCE + no description available + 21 + 1 + write-only + + + FEVTDEBE + no description available + 22 + 1 + write-only + + + RESERVED + no description available + 23 + 1 + read-only + + + FEVTAC12E + no description available + 24 + 1 + write-only + + + RESERVED + no description available + 25 + 1 + read-only + + + FEVTTNE + no description available + 26 + 1 + write-only + + + RESERVED + no description available + 27 + 1 + read-only + + + FEVTDMAE + no description available + 28 + 1 + write-only + + + RESERVED + no description available + 29 + 2 + read-only + + + FEVTCINT + no description available + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + no description available + 0 + 2 + read-only + + + ADMALME + no description available + 2 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + ADMADCE + no description available + 3 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + ADS_ADDR + no description available + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + no description available + 0 + 1 + read-write + + + DLL_CTRL_RESET + no description available + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + no description available + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + no description available + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + no description available + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + no description available + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + DLL_CTRL_SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + no description available + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + no description available + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + no description available + 2 + 7 + read-only + + + DLL_STS_REF_SEL + no description available + 9 + 7 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + no description available + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + no description available + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + no description available + 8 + 7 + read-write + + + NXT_ERR + no description available + 15 + 1 + read-only + + + TAP_SEL_POST + no description available + 16 + 4 + read-only + + + TAP_SEL_OUT + no description available + 20 + 4 + read-only + + + TAP_SEL_PRE + no description available + 24 + 7 + read-only + + + PRE_ERR + no description available + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + no description available + 0 + 1 + read-write + + + 0 + In any scenario, uSDHC does not send out external DMA request + #0 + + + 1 + When internal DMA is not active, the external DMA request will be sent out + #1 + + + + + VSELECT + no description available + 1 + 1 + read-write + + + 1 + Change the voltage to low voltage range, around 1.8V + #1 + + + 0 + Change the voltage to high voltage range, around 3.0V + #0 + + + + + CONFLICT_CHK_EN + no description available + 2 + 1 + read-write + + + 0 + conflict check disable + #0 + + + 1 + conflict check enable + #1 + + + + + AC12_WR_CHKBUSY_EN + no description available + 3 + 1 + read-write + + + 0 + Do not check busy after auto CMD12 for write data packet + #0 + + + 1 + Check busy after auto CMD12 for write data packet + #1 + + + + + DAT3_CD_POL + no description available + 4 + 1 + read-write + + + 0 + card detected when DATA3 is high + #0 + + + 1 + card detected when DATA3 is low + #1 + + + + + CD_POL + no description available + 5 + 1 + read-write + + + 0 + CD_B pin is low active + #0 + + + 1 + CD_B pin is high active + #1 + + + + + WP_POL + no description available + 6 + 1 + read-write + + + 0 + WP pin is high active + #0 + + + 1 + WP pin is low active + #1 + + + + + CLKONJ_IN_ABORT + no description available + 7 + 1 + read-write + + + 0 + the CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full(for read) or empty(for write) + #0 + + + 1 + the CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full(for read) or empty(for write) + #1 + + + + + FRC_SDCLK_ON + no description available + 8 + 1 + read-write + + + 0 + CLK active or inactive is fully controlled by the hardware + #0 + + + 1 + force CLK active + #1 + + + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + IPG_CLK_SOFT_EN + no description available + 11 + 1 + read-write + + + 0 + gate off the IPG_CLK + #0 + + + 1 + enable the IPG_CLK + #1 + + + + + HCLK_SOFT_EN + no description available + 12 + 1 + read-write + + + 0 + gate off the AHB clock. + #0 + + + 1 + enable the AHB clock. + #1 + + + + + IPG_PERCLK_SOFT_EN + no description available + 13 + 1 + read-write + + + 0 + gate off the ipg_perclk + #0 + + + 1 + enable the ipg_perclk + #1 + + + + + CARD_CLK_SOFT_EN + no description available + 14 + 1 + read-write + + + 0 + gate off the sd_clk + #0 + + + 1 + enable the sd_clk + #1 + + + + + CRC_CHK_DIS + no description available + 15 + 1 + read-write + + + 0 + check CRC16 for every read data packet and check CRC bits for every write data packet + #0 + + + 1 + ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + #1 + + + + + INT_ST_VAL + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + no description available + 0 + 4 + read-write + + + 0000 + SDCLK x 2^13 + #0000 + + + 0001 + SDCLK x 2^14 + #0001 + + + 0010 + SDCLK x 2^15 + #0010 + + + 0011 + SDCLK x 2^16 + #0011 + + + 0100 + SDCLK x 2^17 + #0100 + + + 0101 + SDCLK x 2^18 + #0101 + + + 0110 + SDCLK x 2^19 + #0110 + + + 0111 + SDCLK x 2^20 + #0111 + + + 1110 + SDCLK x 2^27 + #1110 + + + 1111 + SDCLK x 2^28 + #1111 + + + + + BOOT_ACK + no description available + 4 + 1 + read-write + + + 0 + No ack + #0 + + + 1 + Ack + #1 + + + + + BOOT_MODE + no description available + 5 + 1 + read-write + + + 0 + Normal boot + #0 + + + 1 + Alternative boot + #1 + + + + + BOOT_EN + no description available + 6 + 1 + read-write + + + 0 + Fast boot disable + #0 + + + 1 + Fast boot enable + #1 + + + + + AUTO_SABG_EN + no description available + 7 + 1 + read-write + + + DISABLE_TIME_OUT + no description available + 8 + 1 + read-write + + + 0 + Enable time out + #0 + + + 1 + Disable time out + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + BOOT_BLK_CNT + no description available + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + no description available + 0 + 1 + read-write + + + 0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + #0 + + + 1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + #1 + + + + + SDR104_OE_DIS + no description available + 1 + 1 + read-write + + + 0 + Drive the CMD_OE/DATA_OE for one more clock cycle after the end bit. + #0 + + + 1 + Stop to drive the CMD_OE/DATA_OE at once after driving the end bit. + #1 + + + + + SDR104_NSD_DIS + no description available + 2 + 1 + read-write + + + 0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command(or CMD12) is sent. + #0 + + + 1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command(or CMD12) is sent. + #1 + + + + + CARD_INT_D3_TEST + no description available + 3 + 1 + read-write + + + 0 + Check the card interrupt only when DATA3 is high. + #0 + + + 1 + Check the card interrupt by ignoring the status of DATA3. + #1 + + + + + TUNING_8bit_EN + no description available + 4 + 1 + read-write + + + 00 + Tuning circuit only checks the DATA[3:0]. + #00 + + + 01 + Tuning circuit only checks the DATA0. + #01 + + + + + TUNING_1bit_EN + no description available + 5 + 1 + read-write + + + TUNING_CMD_EN + no description available + 6 + 1 + read-write + + + 0 + Auto tuning circuit doesn't check the CMD line. + #0 + + + 1 + Auto tuning circuit checks the CMD line. + #1 + + + + + CARD_INT_AUTO_CLR_DIS + no description available + 7 + 1 + read-write + + + 0 + Card interrupt status bit(CINT) can be cleared when Card Interrupt status enable bit is 0. + #0 + + + 1 + Card interrupt status bit(CINT) can only be cleared by writting a 1 to CINT bit. + #1 + + + + + RESERVED + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + uSDHC2 + uSDHC + uSDHC + uSDHC2_ + 0x2194000 + + 0 + 0xCC + registers + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + no description available + 0 + 13 + read-write + + + 1000 + 4096 Bytes + #1000 + + + 001 + 1 Byte + #001 + + + 000 + No data transfer + #000 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + BLKCNT + no description available + 16 + 16 + read-write + + + 0001 + 1 block + #0001 + + + 0000 + Stop Count + #0000 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + no description available + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RSPTYP + no description available + 16 + 2 + read-write + + + 00 + No Response + #00 + + + 01 + Response Length 136 + #01 + + + 10 + Response Length 48 + #10 + + + 11 + Response Length 48, check Busy after response + #11 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + CCCEN + no description available + 19 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + CICEN + no description available + 20 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DPSEL + no description available + 21 + 1 + read-write + + + 1 + Data Present + #1 + + + 0 + No Data Present + #0 + + + + + CMDTYP + no description available + 22 + 2 + read-write + + + 11 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + #11 + + + 10 + Resume CMD52 for writing Function Select in CCCR + #10 + + + 01 + Suspend CMD52 for writing Bus Suspend in CCCR + #01 + + + 00 + Normal Other commands + #00 + + + + + CMDINX + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + no description available + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + no description available + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + no description available + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + no description available + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + no description available + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIHB + no description available + 0 + 1 + read-only + + + 1 + Cannot issue command + #1 + + + 0 + Can issue command using only CMD line + #0 + + + + + CDIHB + no description available + 1 + 1 + read-only + + + 1 + Cannot issue command which uses the DATA line + #1 + + + 0 + Can issue command which uses the DATA line + #0 + + + + + DLA + no description available + 2 + 1 + read-only + + + 1 + DATA Line Active + #1 + + + 0 + DATA Line Inactive + #0 + + + + + SDSTB + no description available + 3 + 1 + read-only + + + 1 + clock is stable + #1 + + + 0 + clock is changing frequency and not stable + #0 + + + + + IPGOFF + no description available + 4 + 1 + read-only + + + 1 + ipg_clk is gated off + #1 + + + 0 + ipg_clk is active + #0 + + + + + HCKOFF + no description available + 5 + 1 + read-only + + + 1 + hclk is gated off + #1 + + + 0 + hclk is active + #0 + + + + + PEROFF + no description available + 6 + 1 + read-only + + + 1 + ipg_perclk is gated off + #1 + + + 0 + ipg_perclk is active + #0 + + + + + SDOFF + no description available + 7 + 1 + read-only + + + 1 + SD Clock is gated off + #1 + + + 0 + SD Clock is active + #0 + + + + + WTA + no description available + 8 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + RTA + no description available + 9 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + BWEN + no description available + 10 + 1 + read-only + + + 1 + Write enable + #1 + + + 0 + Write disable + #0 + + + + + BREN + no description available + 11 + 1 + read-only + + + 1 + Read enable + #1 + + + 0 + Read disable + #0 + + + + + RTR + no description available + 12 + 1 + read-only + + + 1 + Sampling clock needs re-tuning + #1 + + + 0 + Fixed or well tuned sampling clock + #0 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + CINST + no description available + 16 + 1 + read-only + + + 1 + Card Inserted + #1 + + + 0 + Power on Reset or No Card + #0 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + CDPL + no description available + 18 + 1 + read-only + + + 1 + Card present (CD_B=0) + #1 + + + 0 + No card present (CD_B=1) + #0 + + + + + WPSPL + no description available + 19 + 1 + read-only + + + 1 + Write enabled (WP=0) + #1 + + + 0 + Write protected (WP=1) + #0 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + CLSL + no description available + 23 + 1 + read-only + + + DLSL + no description available + 24 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + no description available + 0 + 1 + read-write + + + 1 + LED on + #1 + + + 0 + LED off + #0 + + + + + DTW + no description available + 1 + 2 + read-write + + + 10 + 8-bit mode + #10 + + + 01 + 4-bit mode + #01 + + + 00 + 1-bit mode + #00 + + + 11 + Reserved + #11 + + + + + D3CD + no description available + 3 + 1 + read-write + + + 1 + DATA3 as Card Detection Pin + #1 + + + 0 + DATA3 does not monitor Card Insertion + #0 + + + + + EMODE + no description available + 4 + 2 + read-write + + + 00 + Big Endian Mode + #00 + + + 01 + Half Word Big Endian Mode + #01 + + + 10 + Little Endian Mode + #10 + + + 11 + Reserved + #11 + + + + + CDTL + no description available + 6 + 1 + read-write + + + 1 + Card Detect Test Level is 1, card inserted + #1 + + + 0 + Card Detect Test Level is 0, no card inserted + #0 + + + + + CDSS + no description available + 7 + 1 + read-write + + + 1 + Card Detection Test Level is selected (for test purpose) + #1 + + + 0 + Card Detection Level is selected (for normal purpose) + #0 + + + + + DMASEL + no description available + 8 + 2 + read-write + + + 00 + No DMA or Simple DMA is selected + #00 + + + 01 + ADMA1 is selected + #01 + + + 10 + ADMA2 is selected + #10 + + + 11 + reserved + #11 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + SABGREQ + no description available + 16 + 1 + read-write + + + 1 + Stop + #1 + + + 0 + Transfer + #0 + + + + + CREQ + no description available + 17 + 1 + read-write + + + 1 + Restart + #1 + + + 0 + No effect + #0 + + + + + RWCTL + no description available + 18 + 1 + read-write + + + 1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + #1 + + + 0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + #0 + + + + + IABG + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Disabled + #0 + + + + + RD_DONE_NO_8CLK + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 3 + read-write + + + WECINT + no description available + 24 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECINS + no description available + 25 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECRM + no description available + 26 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BURST_LEN_EN + no description available + 27 + 3 + read-write + + + xx1 + Burst length is enabled for INCR + #xx1 + + + x1x + Burst length is enabled for INCR4/INCR8/INCR16 + #x1x + + + 1xx + Burst length is enabled for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP + #1xx + + + + + NON_EXACT_BLK_RD + no description available + 30 + 1 + read-write + + + 1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + #1 + + + 0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + #0 + + + + + RESERVED + no description available + 31 + 1 + read-write + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-write + + + DVS + no description available + 4 + 4 + read-write + + + 0000 + Divide-by-1 + #0000 + + + 0001 + Divide-by-2 + #0001 + + + 1110 + Divide-by-15 + #1110 + + + 1111 + Divide-by-16 + #1111 + + + + + SDCLKFS + no description available + 8 + 8 + read-write + + + DTOCV + no description available + 16 + 4 + read-write + + + 1111 + SDCLK x 2 28 + #1111 + + + 1110 + SDCLK x 2 2 7 + #1110 + + + 0001 + SDCLK x 2 14 + #0001 + + + 0000 + SDCLK x 2 1 3 + #0000 + + + + + RESERVED + no description available + 20 + 2 + read-only + + + RESERVED + no description available + 22 + 1 + read-only + + + IPP_RST_N + no description available + 23 + 1 + read-write + + + RSTA + no description available + 24 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTC + no description available + 25 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTD + no description available + 26 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + INITA + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + no description available + 0 + 1 + read-write + + + 1 + Command complete + #1 + + + 0 + Command not complete + #0 + + + + + TC + no description available + 1 + 1 + read-write + + + 1 + Transfer complete + #1 + + + 0 + Transfer not complete + #0 + + + + + BGE + no description available + 2 + 1 + read-write + + + 1 + Transaction stopped at block gap + #1 + + + 0 + No block gap event + #0 + + + + + DINT + no description available + 3 + 1 + read-write + + + 1 + DMA Interrupt is generated + #1 + + + 0 + No DMA Interrupt + #0 + + + + + BWR + no description available + 4 + 1 + read-write + + + 1 + Ready to write buffer: + #1 + + + 0 + Not ready to write buffer + #0 + + + + + BRR + no description available + 5 + 1 + read-write + + + 1 + Ready to read buffer + #1 + + + 0 + Not ready to read buffer + #0 + + + + + CINS + no description available + 6 + 1 + read-write + + + 1 + Card inserted + #1 + + + 0 + Card state unstable or removed + #0 + + + + + CRM + no description available + 7 + 1 + read-write + + + 1 + Card removed + #1 + + + 0 + Card state unstable or inserted + #0 + + + + + CINT + no description available + 8 + 1 + read-write + + + 1 + Generate Card Interrupt + #1 + + + 0 + No Card Interrupt + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTE + no description available + 12 + 1 + read-write + + + 1 + Re-Tuning should be performed + #1 + + + 0 + Re-Tuning is not required + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TP + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOE + no description available + 16 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + CCE + no description available + 17 + 1 + read-write + + + 1 + CRC Error Generated. + #1 + + + 0 + No Error + #0 + + + + + CEBE + no description available + 18 + 1 + read-write + + + 1 + End Bit Error Generated + #1 + + + 0 + No Error + #0 + + + + + CIE + no description available + 19 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DTOE + no description available + 20 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + DCE + no description available + 21 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DEBE + no description available + 22 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12E + no description available + 24 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNE + no description available + 26 + 1 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAE + no description available + 28 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0x157F413F + 0xFFFFFFFF + + + CCSEN + no description available + 0 + 1 + read-write + + + TCSEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGESEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTSEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRSEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRSEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSSEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMSEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTSEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTESEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPSEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOESEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCESEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBESEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIESEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOESEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCESEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBESEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12ESEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNESEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAESEN + no description available + 28 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + no description available + 0 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + TCIEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGEIEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTIEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRIEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRIEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSIEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMIEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTIEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTEIEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPIEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOEIEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCEIEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBEIEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIEIEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOEIEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCEIEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBEIEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12EIEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNEIEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAEIEN + no description available + 28 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + AC12NE + no description available + 0 + 1 + read-only + + + 1 + Not executed + #1 + + + 0 + Executed + #0 + + + + + AC12TOE + no description available + 1 + 1 + read-only + + + 1 + Time out + #1 + + + 0 + No error + #0 + + + + + AC12EBE + no description available + 2 + 1 + read-only + + + 1 + End Bit Error Generated + #1 + + + 0 + No error + #0 + + + + + AC12CE + no description available + 3 + 1 + read-only + + + 1 + CRC Error Met in Auto CMD12 Response + #1 + + + 0 + No CRC error + #0 + + + + + AC12IE + no description available + 4 + 1 + read-only + + + 1 + Error, the CMD index in response is not CMD12 + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + CNIBAC12E + no description available + 7 + 1 + read-only + + + 1 + Not Issued + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-only + 0x7F30000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MBL + no description available + 16 + 3 + read-only + + + 000 + 512 bytes + #000 + + + 001 + 1024 bytes + #001 + + + 010 + 2048 bytes + #010 + + + 011 + 4096 bytes + #011 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + ADMAS + no description available + 20 + 1 + read-only + + + 1 + Advanced DMA Supported + #1 + + + 0 + Advanced DMA Not supported + #0 + + + + + HSS + no description available + 21 + 1 + read-only + + + 1 + High Speed Supported + #1 + + + 0 + High Speed Not Supported + #0 + + + + + DMAS + no description available + 22 + 1 + read-only + + + 1 + DMA Supported + #1 + + + 0 + DMA not supported + #0 + + + + + SRS + no description available + 23 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + VS33 + no description available + 24 + 1 + read-only + + + 1 + 3.3V supported + #1 + + + 0 + 3.3V not supported + #0 + + + + + VS30 + no description available + 25 + 1 + read-only + + + 1 + 3.0V supported + #1 + + + 0 + 3.0V not supported + #0 + + + + + VS18 + no description available + 26 + 1 + read-only + + + 1 + 1.8V supported + #1 + + + 0 + 1.8V not supported + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + no description available + 0 + 8 + read-write + + + RD_BRST_LEN + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_WML + no description available + 16 + 8 + read-write + + + WR_BRST_LEN + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + no description available + 0 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BCEN + no description available + 1 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + AC12EN + no description available + 2 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DDR_EN + no description available + 3 + 1 + read-write + + + DTDSEL + no description available + 4 + 1 + read-write + + + 1 + Read (Card to Host) + #1 + + + 0 + Write (Host to Card) + #0 + + + + + MSBSEL + no description available + 5 + 1 + read-write + + + 1 + Multiple Blocks + #1 + + + 0 + Single Block + #0 + + + + + NIBBLE_POS + no description available + 6 + 1 + read-write + + + AC23EN + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 14 + read-only + + + EXE_TUNE + no description available + 22 + 1 + read-write + + + 1 + Execute Tuning + #1 + + + 0 + Not Tuned or Tuning Completed + #0 + + + + + SMP_CLK_SEL + no description available + 23 + 1 + read-write + + + 1 + Tuned clock is used to sample data/cmd + #1 + + + 0 + Fixed clock is used to sample data/cmd + #0 + + + + + AUTO_TUNE_EN + no description available + 24 + 1 + read-write + + + 1 + enable auto tuning + #1 + + + 0 + disable auto tuning + #0 + + + + + FBCLK_SEL + no description available + 25 + 1 + read-write + + + 1 + feedback clock comes from the ipp_card_clk_out + #1 + + + 0 + feedback clock comes from the loopback CLK + #0 + + + + + RESERVED + no description available + 26 + 3 + read-only + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-write + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + no description available + 0 + 1 + write-only + + + FEVTAC12TOE + no description available + 1 + 1 + write-only + + + FEVTAC12CE + no description available + 2 + 1 + write-only + + + FEVTAC12EBE + no description available + 3 + 1 + write-only + + + FEVTAC12IE + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 2 + read-only + + + FEVTCNIBAC12E + no description available + 7 + 1 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + FEVTCTOE + no description available + 16 + 1 + write-only + + + FEVTCCE + no description available + 17 + 1 + write-only + + + FEVTCEBE + no description available + 18 + 1 + write-only + + + FEVTCIE + no description available + 19 + 1 + write-only + + + FEVTDTOE + no description available + 20 + 1 + write-only + + + FEVTDCE + no description available + 21 + 1 + write-only + + + FEVTDEBE + no description available + 22 + 1 + write-only + + + RESERVED + no description available + 23 + 1 + read-only + + + FEVTAC12E + no description available + 24 + 1 + write-only + + + RESERVED + no description available + 25 + 1 + read-only + + + FEVTTNE + no description available + 26 + 1 + write-only + + + RESERVED + no description available + 27 + 1 + read-only + + + FEVTDMAE + no description available + 28 + 1 + write-only + + + RESERVED + no description available + 29 + 2 + read-only + + + FEVTCINT + no description available + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + no description available + 0 + 2 + read-only + + + ADMALME + no description available + 2 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + ADMADCE + no description available + 3 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + ADS_ADDR + no description available + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + no description available + 0 + 1 + read-write + + + DLL_CTRL_RESET + no description available + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + no description available + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + no description available + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + no description available + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + no description available + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + DLL_CTRL_SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + no description available + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + no description available + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + no description available + 2 + 7 + read-only + + + DLL_STS_REF_SEL + no description available + 9 + 7 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + no description available + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + no description available + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + no description available + 8 + 7 + read-write + + + NXT_ERR + no description available + 15 + 1 + read-only + + + TAP_SEL_POST + no description available + 16 + 4 + read-only + + + TAP_SEL_OUT + no description available + 20 + 4 + read-only + + + TAP_SEL_PRE + no description available + 24 + 7 + read-only + + + PRE_ERR + no description available + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + no description available + 0 + 1 + read-write + + + 0 + In any scenario, uSDHC does not send out external DMA request + #0 + + + 1 + When internal DMA is not active, the external DMA request will be sent out + #1 + + + + + VSELECT + no description available + 1 + 1 + read-write + + + 1 + Change the voltage to low voltage range, around 1.8V + #1 + + + 0 + Change the voltage to high voltage range, around 3.0V + #0 + + + + + CONFLICT_CHK_EN + no description available + 2 + 1 + read-write + + + 0 + conflict check disable + #0 + + + 1 + conflict check enable + #1 + + + + + AC12_WR_CHKBUSY_EN + no description available + 3 + 1 + read-write + + + 0 + Do not check busy after auto CMD12 for write data packet + #0 + + + 1 + Check busy after auto CMD12 for write data packet + #1 + + + + + DAT3_CD_POL + no description available + 4 + 1 + read-write + + + 0 + card detected when DATA3 is high + #0 + + + 1 + card detected when DATA3 is low + #1 + + + + + CD_POL + no description available + 5 + 1 + read-write + + + 0 + CD_B pin is low active + #0 + + + 1 + CD_B pin is high active + #1 + + + + + WP_POL + no description available + 6 + 1 + read-write + + + 0 + WP pin is high active + #0 + + + 1 + WP pin is low active + #1 + + + + + CLKONJ_IN_ABORT + no description available + 7 + 1 + read-write + + + 0 + the CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full(for read) or empty(for write) + #0 + + + 1 + the CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full(for read) or empty(for write) + #1 + + + + + FRC_SDCLK_ON + no description available + 8 + 1 + read-write + + + 0 + CLK active or inactive is fully controlled by the hardware + #0 + + + 1 + force CLK active + #1 + + + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + IPG_CLK_SOFT_EN + no description available + 11 + 1 + read-write + + + 0 + gate off the IPG_CLK + #0 + + + 1 + enable the IPG_CLK + #1 + + + + + HCLK_SOFT_EN + no description available + 12 + 1 + read-write + + + 0 + gate off the AHB clock. + #0 + + + 1 + enable the AHB clock. + #1 + + + + + IPG_PERCLK_SOFT_EN + no description available + 13 + 1 + read-write + + + 0 + gate off the ipg_perclk + #0 + + + 1 + enable the ipg_perclk + #1 + + + + + CARD_CLK_SOFT_EN + no description available + 14 + 1 + read-write + + + 0 + gate off the sd_clk + #0 + + + 1 + enable the sd_clk + #1 + + + + + CRC_CHK_DIS + no description available + 15 + 1 + read-write + + + 0 + check CRC16 for every read data packet and check CRC bits for every write data packet + #0 + + + 1 + ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + #1 + + + + + INT_ST_VAL + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + no description available + 0 + 4 + read-write + + + 0000 + SDCLK x 2^13 + #0000 + + + 0001 + SDCLK x 2^14 + #0001 + + + 0010 + SDCLK x 2^15 + #0010 + + + 0011 + SDCLK x 2^16 + #0011 + + + 0100 + SDCLK x 2^17 + #0100 + + + 0101 + SDCLK x 2^18 + #0101 + + + 0110 + SDCLK x 2^19 + #0110 + + + 0111 + SDCLK x 2^20 + #0111 + + + 1110 + SDCLK x 2^27 + #1110 + + + 1111 + SDCLK x 2^28 + #1111 + + + + + BOOT_ACK + no description available + 4 + 1 + read-write + + + 0 + No ack + #0 + + + 1 + Ack + #1 + + + + + BOOT_MODE + no description available + 5 + 1 + read-write + + + 0 + Normal boot + #0 + + + 1 + Alternative boot + #1 + + + + + BOOT_EN + no description available + 6 + 1 + read-write + + + 0 + Fast boot disable + #0 + + + 1 + Fast boot enable + #1 + + + + + AUTO_SABG_EN + no description available + 7 + 1 + read-write + + + DISABLE_TIME_OUT + no description available + 8 + 1 + read-write + + + 0 + Enable time out + #0 + + + 1 + Disable time out + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + BOOT_BLK_CNT + no description available + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + no description available + 0 + 1 + read-write + + + 0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + #0 + + + 1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + #1 + + + + + SDR104_OE_DIS + no description available + 1 + 1 + read-write + + + 0 + Drive the CMD_OE/DATA_OE for one more clock cycle after the end bit. + #0 + + + 1 + Stop to drive the CMD_OE/DATA_OE at once after driving the end bit. + #1 + + + + + SDR104_NSD_DIS + no description available + 2 + 1 + read-write + + + 0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command(or CMD12) is sent. + #0 + + + 1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command(or CMD12) is sent. + #1 + + + + + CARD_INT_D3_TEST + no description available + 3 + 1 + read-write + + + 0 + Check the card interrupt only when DATA3 is high. + #0 + + + 1 + Check the card interrupt by ignoring the status of DATA3. + #1 + + + + + TUNING_8bit_EN + no description available + 4 + 1 + read-write + + + 00 + Tuning circuit only checks the DATA[3:0]. + #00 + + + 01 + Tuning circuit only checks the DATA0. + #01 + + + + + TUNING_1bit_EN + no description available + 5 + 1 + read-write + + + TUNING_CMD_EN + no description available + 6 + 1 + read-write + + + 0 + Auto tuning circuit doesn't check the CMD line. + #0 + + + 1 + Auto tuning circuit checks the CMD line. + #1 + + + + + CARD_INT_AUTO_CLR_DIS + no description available + 7 + 1 + read-write + + + 0 + Card interrupt status bit(CINT) can be cleared when Card Interrupt status enable bit is 0. + #0 + + + 1 + Card interrupt status bit(CINT) can only be cleared by writting a 1 to CINT bit. + #1 + + + + + RESERVED + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + uSDHC3 + uSDHC + uSDHC + uSDHC3_ + 0x2198000 + + 0 + 0xCC + registers + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + no description available + 0 + 13 + read-write + + + 1000 + 4096 Bytes + #1000 + + + 001 + 1 Byte + #001 + + + 000 + No data transfer + #000 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + BLKCNT + no description available + 16 + 16 + read-write + + + 0001 + 1 block + #0001 + + + 0000 + Stop Count + #0000 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + no description available + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RSPTYP + no description available + 16 + 2 + read-write + + + 00 + No Response + #00 + + + 01 + Response Length 136 + #01 + + + 10 + Response Length 48 + #10 + + + 11 + Response Length 48, check Busy after response + #11 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + CCCEN + no description available + 19 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + CICEN + no description available + 20 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DPSEL + no description available + 21 + 1 + read-write + + + 1 + Data Present + #1 + + + 0 + No Data Present + #0 + + + + + CMDTYP + no description available + 22 + 2 + read-write + + + 11 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + #11 + + + 10 + Resume CMD52 for writing Function Select in CCCR + #10 + + + 01 + Suspend CMD52 for writing Bus Suspend in CCCR + #01 + + + 00 + Normal Other commands + #00 + + + + + CMDINX + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + no description available + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + no description available + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + no description available + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + no description available + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + no description available + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIHB + no description available + 0 + 1 + read-only + + + 1 + Cannot issue command + #1 + + + 0 + Can issue command using only CMD line + #0 + + + + + CDIHB + no description available + 1 + 1 + read-only + + + 1 + Cannot issue command which uses the DATA line + #1 + + + 0 + Can issue command which uses the DATA line + #0 + + + + + DLA + no description available + 2 + 1 + read-only + + + 1 + DATA Line Active + #1 + + + 0 + DATA Line Inactive + #0 + + + + + SDSTB + no description available + 3 + 1 + read-only + + + 1 + clock is stable + #1 + + + 0 + clock is changing frequency and not stable + #0 + + + + + IPGOFF + no description available + 4 + 1 + read-only + + + 1 + ipg_clk is gated off + #1 + + + 0 + ipg_clk is active + #0 + + + + + HCKOFF + no description available + 5 + 1 + read-only + + + 1 + hclk is gated off + #1 + + + 0 + hclk is active + #0 + + + + + PEROFF + no description available + 6 + 1 + read-only + + + 1 + ipg_perclk is gated off + #1 + + + 0 + ipg_perclk is active + #0 + + + + + SDOFF + no description available + 7 + 1 + read-only + + + 1 + SD Clock is gated off + #1 + + + 0 + SD Clock is active + #0 + + + + + WTA + no description available + 8 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + RTA + no description available + 9 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + BWEN + no description available + 10 + 1 + read-only + + + 1 + Write enable + #1 + + + 0 + Write disable + #0 + + + + + BREN + no description available + 11 + 1 + read-only + + + 1 + Read enable + #1 + + + 0 + Read disable + #0 + + + + + RTR + no description available + 12 + 1 + read-only + + + 1 + Sampling clock needs re-tuning + #1 + + + 0 + Fixed or well tuned sampling clock + #0 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + CINST + no description available + 16 + 1 + read-only + + + 1 + Card Inserted + #1 + + + 0 + Power on Reset or No Card + #0 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + CDPL + no description available + 18 + 1 + read-only + + + 1 + Card present (CD_B=0) + #1 + + + 0 + No card present (CD_B=1) + #0 + + + + + WPSPL + no description available + 19 + 1 + read-only + + + 1 + Write enabled (WP=0) + #1 + + + 0 + Write protected (WP=1) + #0 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + CLSL + no description available + 23 + 1 + read-only + + + DLSL + no description available + 24 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + no description available + 0 + 1 + read-write + + + 1 + LED on + #1 + + + 0 + LED off + #0 + + + + + DTW + no description available + 1 + 2 + read-write + + + 10 + 8-bit mode + #10 + + + 01 + 4-bit mode + #01 + + + 00 + 1-bit mode + #00 + + + 11 + Reserved + #11 + + + + + D3CD + no description available + 3 + 1 + read-write + + + 1 + DATA3 as Card Detection Pin + #1 + + + 0 + DATA3 does not monitor Card Insertion + #0 + + + + + EMODE + no description available + 4 + 2 + read-write + + + 00 + Big Endian Mode + #00 + + + 01 + Half Word Big Endian Mode + #01 + + + 10 + Little Endian Mode + #10 + + + 11 + Reserved + #11 + + + + + CDTL + no description available + 6 + 1 + read-write + + + 1 + Card Detect Test Level is 1, card inserted + #1 + + + 0 + Card Detect Test Level is 0, no card inserted + #0 + + + + + CDSS + no description available + 7 + 1 + read-write + + + 1 + Card Detection Test Level is selected (for test purpose) + #1 + + + 0 + Card Detection Level is selected (for normal purpose) + #0 + + + + + DMASEL + no description available + 8 + 2 + read-write + + + 00 + No DMA or Simple DMA is selected + #00 + + + 01 + ADMA1 is selected + #01 + + + 10 + ADMA2 is selected + #10 + + + 11 + reserved + #11 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + SABGREQ + no description available + 16 + 1 + read-write + + + 1 + Stop + #1 + + + 0 + Transfer + #0 + + + + + CREQ + no description available + 17 + 1 + read-write + + + 1 + Restart + #1 + + + 0 + No effect + #0 + + + + + RWCTL + no description available + 18 + 1 + read-write + + + 1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + #1 + + + 0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + #0 + + + + + IABG + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Disabled + #0 + + + + + RD_DONE_NO_8CLK + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 3 + read-write + + + WECINT + no description available + 24 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECINS + no description available + 25 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECRM + no description available + 26 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BURST_LEN_EN + no description available + 27 + 3 + read-write + + + xx1 + Burst length is enabled for INCR + #xx1 + + + x1x + Burst length is enabled for INCR4/INCR8/INCR16 + #x1x + + + 1xx + Burst length is enabled for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP + #1xx + + + + + NON_EXACT_BLK_RD + no description available + 30 + 1 + read-write + + + 1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + #1 + + + 0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + #0 + + + + + RESERVED + no description available + 31 + 1 + read-write + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-write + + + DVS + no description available + 4 + 4 + read-write + + + 0000 + Divide-by-1 + #0000 + + + 0001 + Divide-by-2 + #0001 + + + 1110 + Divide-by-15 + #1110 + + + 1111 + Divide-by-16 + #1111 + + + + + SDCLKFS + no description available + 8 + 8 + read-write + + + DTOCV + no description available + 16 + 4 + read-write + + + 1111 + SDCLK x 2 28 + #1111 + + + 1110 + SDCLK x 2 2 7 + #1110 + + + 0001 + SDCLK x 2 14 + #0001 + + + 0000 + SDCLK x 2 1 3 + #0000 + + + + + RESERVED + no description available + 20 + 2 + read-only + + + RESERVED + no description available + 22 + 1 + read-only + + + IPP_RST_N + no description available + 23 + 1 + read-write + + + RSTA + no description available + 24 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTC + no description available + 25 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTD + no description available + 26 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + INITA + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + no description available + 0 + 1 + read-write + + + 1 + Command complete + #1 + + + 0 + Command not complete + #0 + + + + + TC + no description available + 1 + 1 + read-write + + + 1 + Transfer complete + #1 + + + 0 + Transfer not complete + #0 + + + + + BGE + no description available + 2 + 1 + read-write + + + 1 + Transaction stopped at block gap + #1 + + + 0 + No block gap event + #0 + + + + + DINT + no description available + 3 + 1 + read-write + + + 1 + DMA Interrupt is generated + #1 + + + 0 + No DMA Interrupt + #0 + + + + + BWR + no description available + 4 + 1 + read-write + + + 1 + Ready to write buffer: + #1 + + + 0 + Not ready to write buffer + #0 + + + + + BRR + no description available + 5 + 1 + read-write + + + 1 + Ready to read buffer + #1 + + + 0 + Not ready to read buffer + #0 + + + + + CINS + no description available + 6 + 1 + read-write + + + 1 + Card inserted + #1 + + + 0 + Card state unstable or removed + #0 + + + + + CRM + no description available + 7 + 1 + read-write + + + 1 + Card removed + #1 + + + 0 + Card state unstable or inserted + #0 + + + + + CINT + no description available + 8 + 1 + read-write + + + 1 + Generate Card Interrupt + #1 + + + 0 + No Card Interrupt + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTE + no description available + 12 + 1 + read-write + + + 1 + Re-Tuning should be performed + #1 + + + 0 + Re-Tuning is not required + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TP + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOE + no description available + 16 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + CCE + no description available + 17 + 1 + read-write + + + 1 + CRC Error Generated. + #1 + + + 0 + No Error + #0 + + + + + CEBE + no description available + 18 + 1 + read-write + + + 1 + End Bit Error Generated + #1 + + + 0 + No Error + #0 + + + + + CIE + no description available + 19 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DTOE + no description available + 20 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + DCE + no description available + 21 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DEBE + no description available + 22 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12E + no description available + 24 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNE + no description available + 26 + 1 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAE + no description available + 28 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0x157F413F + 0xFFFFFFFF + + + CCSEN + no description available + 0 + 1 + read-write + + + TCSEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGESEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTSEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRSEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRSEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSSEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMSEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTSEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTESEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPSEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOESEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCESEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBESEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIESEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOESEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCESEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBESEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12ESEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNESEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAESEN + no description available + 28 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + no description available + 0 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + TCIEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGEIEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTIEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRIEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRIEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSIEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMIEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTIEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTEIEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPIEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOEIEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCEIEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBEIEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIEIEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOEIEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCEIEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBEIEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12EIEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNEIEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAEIEN + no description available + 28 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + AC12NE + no description available + 0 + 1 + read-only + + + 1 + Not executed + #1 + + + 0 + Executed + #0 + + + + + AC12TOE + no description available + 1 + 1 + read-only + + + 1 + Time out + #1 + + + 0 + No error + #0 + + + + + AC12EBE + no description available + 2 + 1 + read-only + + + 1 + End Bit Error Generated + #1 + + + 0 + No error + #0 + + + + + AC12CE + no description available + 3 + 1 + read-only + + + 1 + CRC Error Met in Auto CMD12 Response + #1 + + + 0 + No CRC error + #0 + + + + + AC12IE + no description available + 4 + 1 + read-only + + + 1 + Error, the CMD index in response is not CMD12 + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + CNIBAC12E + no description available + 7 + 1 + read-only + + + 1 + Not Issued + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-only + 0x7F30000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MBL + no description available + 16 + 3 + read-only + + + 000 + 512 bytes + #000 + + + 001 + 1024 bytes + #001 + + + 010 + 2048 bytes + #010 + + + 011 + 4096 bytes + #011 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + ADMAS + no description available + 20 + 1 + read-only + + + 1 + Advanced DMA Supported + #1 + + + 0 + Advanced DMA Not supported + #0 + + + + + HSS + no description available + 21 + 1 + read-only + + + 1 + High Speed Supported + #1 + + + 0 + High Speed Not Supported + #0 + + + + + DMAS + no description available + 22 + 1 + read-only + + + 1 + DMA Supported + #1 + + + 0 + DMA not supported + #0 + + + + + SRS + no description available + 23 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + VS33 + no description available + 24 + 1 + read-only + + + 1 + 3.3V supported + #1 + + + 0 + 3.3V not supported + #0 + + + + + VS30 + no description available + 25 + 1 + read-only + + + 1 + 3.0V supported + #1 + + + 0 + 3.0V not supported + #0 + + + + + VS18 + no description available + 26 + 1 + read-only + + + 1 + 1.8V supported + #1 + + + 0 + 1.8V not supported + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + no description available + 0 + 8 + read-write + + + RD_BRST_LEN + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_WML + no description available + 16 + 8 + read-write + + + WR_BRST_LEN + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + no description available + 0 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BCEN + no description available + 1 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + AC12EN + no description available + 2 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DDR_EN + no description available + 3 + 1 + read-write + + + DTDSEL + no description available + 4 + 1 + read-write + + + 1 + Read (Card to Host) + #1 + + + 0 + Write (Host to Card) + #0 + + + + + MSBSEL + no description available + 5 + 1 + read-write + + + 1 + Multiple Blocks + #1 + + + 0 + Single Block + #0 + + + + + NIBBLE_POS + no description available + 6 + 1 + read-write + + + AC23EN + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 14 + read-only + + + EXE_TUNE + no description available + 22 + 1 + read-write + + + 1 + Execute Tuning + #1 + + + 0 + Not Tuned or Tuning Completed + #0 + + + + + SMP_CLK_SEL + no description available + 23 + 1 + read-write + + + 1 + Tuned clock is used to sample data/cmd + #1 + + + 0 + Fixed clock is used to sample data/cmd + #0 + + + + + AUTO_TUNE_EN + no description available + 24 + 1 + read-write + + + 1 + enable auto tuning + #1 + + + 0 + disable auto tuning + #0 + + + + + FBCLK_SEL + no description available + 25 + 1 + read-write + + + 1 + feedback clock comes from the ipp_card_clk_out + #1 + + + 0 + feedback clock comes from the loopback CLK + #0 + + + + + RESERVED + no description available + 26 + 3 + read-only + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-write + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + no description available + 0 + 1 + write-only + + + FEVTAC12TOE + no description available + 1 + 1 + write-only + + + FEVTAC12CE + no description available + 2 + 1 + write-only + + + FEVTAC12EBE + no description available + 3 + 1 + write-only + + + FEVTAC12IE + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 2 + read-only + + + FEVTCNIBAC12E + no description available + 7 + 1 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + FEVTCTOE + no description available + 16 + 1 + write-only + + + FEVTCCE + no description available + 17 + 1 + write-only + + + FEVTCEBE + no description available + 18 + 1 + write-only + + + FEVTCIE + no description available + 19 + 1 + write-only + + + FEVTDTOE + no description available + 20 + 1 + write-only + + + FEVTDCE + no description available + 21 + 1 + write-only + + + FEVTDEBE + no description available + 22 + 1 + write-only + + + RESERVED + no description available + 23 + 1 + read-only + + + FEVTAC12E + no description available + 24 + 1 + write-only + + + RESERVED + no description available + 25 + 1 + read-only + + + FEVTTNE + no description available + 26 + 1 + write-only + + + RESERVED + no description available + 27 + 1 + read-only + + + FEVTDMAE + no description available + 28 + 1 + write-only + + + RESERVED + no description available + 29 + 2 + read-only + + + FEVTCINT + no description available + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + no description available + 0 + 2 + read-only + + + ADMALME + no description available + 2 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + ADMADCE + no description available + 3 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + ADS_ADDR + no description available + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + no description available + 0 + 1 + read-write + + + DLL_CTRL_RESET + no description available + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + no description available + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + no description available + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + no description available + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + no description available + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + DLL_CTRL_SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + no description available + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + no description available + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + no description available + 2 + 7 + read-only + + + DLL_STS_REF_SEL + no description available + 9 + 7 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + no description available + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + no description available + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + no description available + 8 + 7 + read-write + + + NXT_ERR + no description available + 15 + 1 + read-only + + + TAP_SEL_POST + no description available + 16 + 4 + read-only + + + TAP_SEL_OUT + no description available + 20 + 4 + read-only + + + TAP_SEL_PRE + no description available + 24 + 7 + read-only + + + PRE_ERR + no description available + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + no description available + 0 + 1 + read-write + + + 0 + In any scenario, uSDHC does not send out external DMA request + #0 + + + 1 + When internal DMA is not active, the external DMA request will be sent out + #1 + + + + + VSELECT + no description available + 1 + 1 + read-write + + + 1 + Change the voltage to low voltage range, around 1.8V + #1 + + + 0 + Change the voltage to high voltage range, around 3.0V + #0 + + + + + CONFLICT_CHK_EN + no description available + 2 + 1 + read-write + + + 0 + conflict check disable + #0 + + + 1 + conflict check enable + #1 + + + + + AC12_WR_CHKBUSY_EN + no description available + 3 + 1 + read-write + + + 0 + Do not check busy after auto CMD12 for write data packet + #0 + + + 1 + Check busy after auto CMD12 for write data packet + #1 + + + + + DAT3_CD_POL + no description available + 4 + 1 + read-write + + + 0 + card detected when DATA3 is high + #0 + + + 1 + card detected when DATA3 is low + #1 + + + + + CD_POL + no description available + 5 + 1 + read-write + + + 0 + CD_B pin is low active + #0 + + + 1 + CD_B pin is high active + #1 + + + + + WP_POL + no description available + 6 + 1 + read-write + + + 0 + WP pin is high active + #0 + + + 1 + WP pin is low active + #1 + + + + + CLKONJ_IN_ABORT + no description available + 7 + 1 + read-write + + + 0 + the CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full(for read) or empty(for write) + #0 + + + 1 + the CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full(for read) or empty(for write) + #1 + + + + + FRC_SDCLK_ON + no description available + 8 + 1 + read-write + + + 0 + CLK active or inactive is fully controlled by the hardware + #0 + + + 1 + force CLK active + #1 + + + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + IPG_CLK_SOFT_EN + no description available + 11 + 1 + read-write + + + 0 + gate off the IPG_CLK + #0 + + + 1 + enable the IPG_CLK + #1 + + + + + HCLK_SOFT_EN + no description available + 12 + 1 + read-write + + + 0 + gate off the AHB clock. + #0 + + + 1 + enable the AHB clock. + #1 + + + + + IPG_PERCLK_SOFT_EN + no description available + 13 + 1 + read-write + + + 0 + gate off the ipg_perclk + #0 + + + 1 + enable the ipg_perclk + #1 + + + + + CARD_CLK_SOFT_EN + no description available + 14 + 1 + read-write + + + 0 + gate off the sd_clk + #0 + + + 1 + enable the sd_clk + #1 + + + + + CRC_CHK_DIS + no description available + 15 + 1 + read-write + + + 0 + check CRC16 for every read data packet and check CRC bits for every write data packet + #0 + + + 1 + ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + #1 + + + + + INT_ST_VAL + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + no description available + 0 + 4 + read-write + + + 0000 + SDCLK x 2^13 + #0000 + + + 0001 + SDCLK x 2^14 + #0001 + + + 0010 + SDCLK x 2^15 + #0010 + + + 0011 + SDCLK x 2^16 + #0011 + + + 0100 + SDCLK x 2^17 + #0100 + + + 0101 + SDCLK x 2^18 + #0101 + + + 0110 + SDCLK x 2^19 + #0110 + + + 0111 + SDCLK x 2^20 + #0111 + + + 1110 + SDCLK x 2^27 + #1110 + + + 1111 + SDCLK x 2^28 + #1111 + + + + + BOOT_ACK + no description available + 4 + 1 + read-write + + + 0 + No ack + #0 + + + 1 + Ack + #1 + + + + + BOOT_MODE + no description available + 5 + 1 + read-write + + + 0 + Normal boot + #0 + + + 1 + Alternative boot + #1 + + + + + BOOT_EN + no description available + 6 + 1 + read-write + + + 0 + Fast boot disable + #0 + + + 1 + Fast boot enable + #1 + + + + + AUTO_SABG_EN + no description available + 7 + 1 + read-write + + + DISABLE_TIME_OUT + no description available + 8 + 1 + read-write + + + 0 + Enable time out + #0 + + + 1 + Disable time out + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + BOOT_BLK_CNT + no description available + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + no description available + 0 + 1 + read-write + + + 0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + #0 + + + 1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + #1 + + + + + SDR104_OE_DIS + no description available + 1 + 1 + read-write + + + 0 + Drive the CMD_OE/DATA_OE for one more clock cycle after the end bit. + #0 + + + 1 + Stop to drive the CMD_OE/DATA_OE at once after driving the end bit. + #1 + + + + + SDR104_NSD_DIS + no description available + 2 + 1 + read-write + + + 0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command(or CMD12) is sent. + #0 + + + 1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command(or CMD12) is sent. + #1 + + + + + CARD_INT_D3_TEST + no description available + 3 + 1 + read-write + + + 0 + Check the card interrupt only when DATA3 is high. + #0 + + + 1 + Check the card interrupt by ignoring the status of DATA3. + #1 + + + + + TUNING_8bit_EN + no description available + 4 + 1 + read-write + + + 00 + Tuning circuit only checks the DATA[3:0]. + #00 + + + 01 + Tuning circuit only checks the DATA0. + #01 + + + + + TUNING_1bit_EN + no description available + 5 + 1 + read-write + + + TUNING_CMD_EN + no description available + 6 + 1 + read-write + + + 0 + Auto tuning circuit doesn't check the CMD line. + #0 + + + 1 + Auto tuning circuit checks the CMD line. + #1 + + + + + CARD_INT_AUTO_CLR_DIS + no description available + 7 + 1 + read-write + + + 0 + Card interrupt status bit(CINT) can be cleared when Card Interrupt status enable bit is 0. + #0 + + + 1 + Card interrupt status bit(CINT) can only be cleared by writting a 1 to CINT bit. + #1 + + + + + RESERVED + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + uSDHC4 + uSDHC + uSDHC + uSDHC4_ + 0x219C000 + + 0 + 0xCC + registers + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + no description available + 0 + 13 + read-write + + + 1000 + 4096 Bytes + #1000 + + + 001 + 1 Byte + #001 + + + 000 + No data transfer + #000 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + BLKCNT + no description available + 16 + 16 + read-write + + + 0001 + 1 block + #0001 + + + 0000 + Stop Count + #0000 + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + no description available + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RSPTYP + no description available + 16 + 2 + read-write + + + 00 + No Response + #00 + + + 01 + Response Length 136 + #01 + + + 10 + Response Length 48 + #10 + + + 11 + Response Length 48, check Busy after response + #11 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + CCCEN + no description available + 19 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + CICEN + no description available + 20 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DPSEL + no description available + 21 + 1 + read-write + + + 1 + Data Present + #1 + + + 0 + No Data Present + #0 + + + + + CMDTYP + no description available + 22 + 2 + read-write + + + 11 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + #11 + + + 10 + Resume CMD52 for writing Function Select in CCCR + #10 + + + 01 + Suspend CMD52 for writing Bus Suspend in CCCR + #01 + + + 00 + Normal Other commands + #00 + + + + + CMDINX + no description available + 24 + 6 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + no description available + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + no description available + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + no description available + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + no description available + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + no description available + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIHB + no description available + 0 + 1 + read-only + + + 1 + Cannot issue command + #1 + + + 0 + Can issue command using only CMD line + #0 + + + + + CDIHB + no description available + 1 + 1 + read-only + + + 1 + Cannot issue command which uses the DATA line + #1 + + + 0 + Can issue command which uses the DATA line + #0 + + + + + DLA + no description available + 2 + 1 + read-only + + + 1 + DATA Line Active + #1 + + + 0 + DATA Line Inactive + #0 + + + + + SDSTB + no description available + 3 + 1 + read-only + + + 1 + clock is stable + #1 + + + 0 + clock is changing frequency and not stable + #0 + + + + + IPGOFF + no description available + 4 + 1 + read-only + + + 1 + ipg_clk is gated off + #1 + + + 0 + ipg_clk is active + #0 + + + + + HCKOFF + no description available + 5 + 1 + read-only + + + 1 + hclk is gated off + #1 + + + 0 + hclk is active + #0 + + + + + PEROFF + no description available + 6 + 1 + read-only + + + 1 + ipg_perclk is gated off + #1 + + + 0 + ipg_perclk is active + #0 + + + + + SDOFF + no description available + 7 + 1 + read-only + + + 1 + SD Clock is gated off + #1 + + + 0 + SD Clock is active + #0 + + + + + WTA + no description available + 8 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + RTA + no description available + 9 + 1 + read-only + + + 1 + Transferring data + #1 + + + 0 + No valid data + #0 + + + + + BWEN + no description available + 10 + 1 + read-only + + + 1 + Write enable + #1 + + + 0 + Write disable + #0 + + + + + BREN + no description available + 11 + 1 + read-only + + + 1 + Read enable + #1 + + + 0 + Read disable + #0 + + + + + RTR + no description available + 12 + 1 + read-only + + + 1 + Sampling clock needs re-tuning + #1 + + + 0 + Fixed or well tuned sampling clock + #0 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + CINST + no description available + 16 + 1 + read-only + + + 1 + Card Inserted + #1 + + + 0 + Power on Reset or No Card + #0 + + + + + RESERVED + no description available + 17 + 1 + read-only + + + CDPL + no description available + 18 + 1 + read-only + + + 1 + Card present (CD_B=0) + #1 + + + 0 + No card present (CD_B=1) + #0 + + + + + WPSPL + no description available + 19 + 1 + read-only + + + 1 + Write enabled (WP=0) + #1 + + + 0 + Write protected (WP=1) + #0 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + CLSL + no description available + 23 + 1 + read-only + + + DLSL + no description available + 24 + 8 + read-only + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + no description available + 0 + 1 + read-write + + + 1 + LED on + #1 + + + 0 + LED off + #0 + + + + + DTW + no description available + 1 + 2 + read-write + + + 10 + 8-bit mode + #10 + + + 01 + 4-bit mode + #01 + + + 00 + 1-bit mode + #00 + + + 11 + Reserved + #11 + + + + + D3CD + no description available + 3 + 1 + read-write + + + 1 + DATA3 as Card Detection Pin + #1 + + + 0 + DATA3 does not monitor Card Insertion + #0 + + + + + EMODE + no description available + 4 + 2 + read-write + + + 00 + Big Endian Mode + #00 + + + 01 + Half Word Big Endian Mode + #01 + + + 10 + Little Endian Mode + #10 + + + 11 + Reserved + #11 + + + + + CDTL + no description available + 6 + 1 + read-write + + + 1 + Card Detect Test Level is 1, card inserted + #1 + + + 0 + Card Detect Test Level is 0, no card inserted + #0 + + + + + CDSS + no description available + 7 + 1 + read-write + + + 1 + Card Detection Test Level is selected (for test purpose) + #1 + + + 0 + Card Detection Level is selected (for normal purpose) + #0 + + + + + DMASEL + no description available + 8 + 2 + read-write + + + 00 + No DMA or Simple DMA is selected + #00 + + + 01 + ADMA1 is selected + #01 + + + 10 + ADMA2 is selected + #10 + + + 11 + reserved + #11 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + SABGREQ + no description available + 16 + 1 + read-write + + + 1 + Stop + #1 + + + 0 + Transfer + #0 + + + + + CREQ + no description available + 17 + 1 + read-write + + + 1 + Restart + #1 + + + 0 + No effect + #0 + + + + + RWCTL + no description available + 18 + 1 + read-write + + + 1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + #1 + + + 0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + #0 + + + + + IABG + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Disabled + #0 + + + + + RD_DONE_NO_8CLK + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 3 + read-write + + + WECINT + no description available + 24 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECINS + no description available + 25 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + WECRM + no description available + 26 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BURST_LEN_EN + no description available + 27 + 3 + read-write + + + xx1 + Burst length is enabled for INCR + #xx1 + + + x1x + Burst length is enabled for INCR4/INCR8/INCR16 + #x1x + + + 1xx + Burst length is enabled for INCR4-WRAP/INCR8-WRAP/INCR16-WRAP + #1xx + + + + + NON_EXACT_BLK_RD + no description available + 30 + 1 + read-write + + + 1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + #1 + + + 0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + #0 + + + + + RESERVED + no description available + 31 + 1 + read-write + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-write + + + DVS + no description available + 4 + 4 + read-write + + + 0000 + Divide-by-1 + #0000 + + + 0001 + Divide-by-2 + #0001 + + + 1110 + Divide-by-15 + #1110 + + + 1111 + Divide-by-16 + #1111 + + + + + SDCLKFS + no description available + 8 + 8 + read-write + + + DTOCV + no description available + 16 + 4 + read-write + + + 1111 + SDCLK x 2 28 + #1111 + + + 1110 + SDCLK x 2 2 7 + #1110 + + + 0001 + SDCLK x 2 14 + #0001 + + + 0000 + SDCLK x 2 1 3 + #0000 + + + + + RESERVED + no description available + 20 + 2 + read-only + + + RESERVED + no description available + 22 + 1 + read-only + + + IPP_RST_N + no description available + 23 + 1 + read-write + + + RSTA + no description available + 24 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTC + no description available + 25 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + RSTD + no description available + 26 + 1 + write-only + + + 1 + Reset + #1 + + + 0 + No Reset + #0 + + + + + INITA + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + no description available + 0 + 1 + read-write + + + 1 + Command complete + #1 + + + 0 + Command not complete + #0 + + + + + TC + no description available + 1 + 1 + read-write + + + 1 + Transfer complete + #1 + + + 0 + Transfer not complete + #0 + + + + + BGE + no description available + 2 + 1 + read-write + + + 1 + Transaction stopped at block gap + #1 + + + 0 + No block gap event + #0 + + + + + DINT + no description available + 3 + 1 + read-write + + + 1 + DMA Interrupt is generated + #1 + + + 0 + No DMA Interrupt + #0 + + + + + BWR + no description available + 4 + 1 + read-write + + + 1 + Ready to write buffer: + #1 + + + 0 + Not ready to write buffer + #0 + + + + + BRR + no description available + 5 + 1 + read-write + + + 1 + Ready to read buffer + #1 + + + 0 + Not ready to read buffer + #0 + + + + + CINS + no description available + 6 + 1 + read-write + + + 1 + Card inserted + #1 + + + 0 + Card state unstable or removed + #0 + + + + + CRM + no description available + 7 + 1 + read-write + + + 1 + Card removed + #1 + + + 0 + Card state unstable or inserted + #0 + + + + + CINT + no description available + 8 + 1 + read-write + + + 1 + Generate Card Interrupt + #1 + + + 0 + No Card Interrupt + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTE + no description available + 12 + 1 + read-write + + + 1 + Re-Tuning should be performed + #1 + + + 0 + Re-Tuning is not required + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TP + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOE + no description available + 16 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + CCE + no description available + 17 + 1 + read-write + + + 1 + CRC Error Generated. + #1 + + + 0 + No Error + #0 + + + + + CEBE + no description available + 18 + 1 + read-write + + + 1 + End Bit Error Generated + #1 + + + 0 + No Error + #0 + + + + + CIE + no description available + 19 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DTOE + no description available + 20 + 1 + read-write + + + 1 + Time out + #1 + + + 0 + No Error + #0 + + + + + DCE + no description available + 21 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + DEBE + no description available + 22 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12E + no description available + 24 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNE + no description available + 26 + 1 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAE + no description available + 28 + 1 + read-write + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0x157F413F + 0xFFFFFFFF + + + CCSEN + no description available + 0 + 1 + read-write + + + TCSEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGESEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTSEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRSEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRSEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSSEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMSEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTSEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTESEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPSEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOESEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCESEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBESEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIESEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOESEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCESEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBESEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12ESEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNESEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAESEN + no description available + 28 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + no description available + 0 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + TCIEN + no description available + 1 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BGEIEN + no description available + 2 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DINTIEN + no description available + 3 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BWRIEN + no description available + 4 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + BRRIEN + no description available + 5 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINSIEN + no description available + 6 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CRMIEN + no description available + 7 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CINTIEN + no description available + 8 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + RTEIEN + no description available + 12 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 13 + 1 + read-only + + + TPIEN + no description available + 14 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CTOEIEN + no description available + 16 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CCEIEN + no description available + 17 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CEBEIEN + no description available + 18 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + CIEIEN + no description available + 19 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DTOEIEN + no description available + 20 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DCEIEN + no description available + 21 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + DEBEIEN + no description available + 22 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + AC12EIEN + no description available + 24 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 25 + 1 + read-only + + + TNEIEN + no description available + 26 + 1 + read-write + + + 1 + Enabled + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + DMAEIEN + no description available + 28 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Masked + #0 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + AC12NE + no description available + 0 + 1 + read-only + + + 1 + Not executed + #1 + + + 0 + Executed + #0 + + + + + AC12TOE + no description available + 1 + 1 + read-only + + + 1 + Time out + #1 + + + 0 + No error + #0 + + + + + AC12EBE + no description available + 2 + 1 + read-only + + + 1 + End Bit Error Generated + #1 + + + 0 + No error + #0 + + + + + AC12CE + no description available + 3 + 1 + read-only + + + 1 + CRC Error Met in Auto CMD12 Response + #1 + + + 0 + No CRC error + #0 + + + + + AC12IE + no description available + 4 + 1 + read-only + + + 1 + Error, the CMD index in response is not CMD12 + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 5 + 2 + read-only + + + CNIBAC12E + no description available + 7 + 1 + read-only + + + 1 + Not Issued + #1 + + + 0 + No error + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-only + 0x7F30000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + MBL + no description available + 16 + 3 + read-only + + + 000 + 512 bytes + #000 + + + 001 + 1024 bytes + #001 + + + 010 + 2048 bytes + #010 + + + 011 + 4096 bytes + #011 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + ADMAS + no description available + 20 + 1 + read-only + + + 1 + Advanced DMA Supported + #1 + + + 0 + Advanced DMA Not supported + #0 + + + + + HSS + no description available + 21 + 1 + read-only + + + 1 + High Speed Supported + #1 + + + 0 + High Speed Not Supported + #0 + + + + + DMAS + no description available + 22 + 1 + read-only + + + 1 + DMA Supported + #1 + + + 0 + DMA not supported + #0 + + + + + SRS + no description available + 23 + 1 + read-only + + + 1 + Supported + #1 + + + 0 + Not supported + #0 + + + + + VS33 + no description available + 24 + 1 + read-only + + + 1 + 3.3V supported + #1 + + + 0 + 3.3V not supported + #0 + + + + + VS30 + no description available + 25 + 1 + read-only + + + 1 + 3.0V supported + #1 + + + 0 + 3.0V not supported + #0 + + + + + VS18 + no description available + 26 + 1 + read-only + + + 1 + 1.8V supported + #1 + + + 0 + 1.8V not supported + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + no description available + 0 + 8 + read-write + + + RD_BRST_LEN + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_WML + no description available + 16 + 8 + read-write + + + WR_BRST_LEN + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + no description available + 0 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + BCEN + no description available + 1 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + AC12EN + no description available + 2 + 1 + read-write + + + 1 + Enable + #1 + + + 0 + Disable + #0 + + + + + DDR_EN + no description available + 3 + 1 + read-write + + + DTDSEL + no description available + 4 + 1 + read-write + + + 1 + Read (Card to Host) + #1 + + + 0 + Write (Host to Card) + #0 + + + + + MSBSEL + no description available + 5 + 1 + read-write + + + 1 + Multiple Blocks + #1 + + + 0 + Single Block + #0 + + + + + NIBBLE_POS + no description available + 6 + 1 + read-write + + + AC23EN + no description available + 7 + 1 + read-write + + + RESERVED + no description available + 8 + 14 + read-only + + + EXE_TUNE + no description available + 22 + 1 + read-write + + + 1 + Execute Tuning + #1 + + + 0 + Not Tuned or Tuning Completed + #0 + + + + + SMP_CLK_SEL + no description available + 23 + 1 + read-write + + + 1 + Tuned clock is used to sample data/cmd + #1 + + + 0 + Fixed clock is used to sample data/cmd + #0 + + + + + AUTO_TUNE_EN + no description available + 24 + 1 + read-write + + + 1 + enable auto tuning + #1 + + + 0 + disable auto tuning + #0 + + + + + FBCLK_SEL + no description available + 25 + 1 + read-write + + + 1 + feedback clock comes from the ipp_card_clk_out + #1 + + + 0 + feedback clock comes from the loopback CLK + #0 + + + + + RESERVED + no description available + 26 + 3 + read-only + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-write + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + no description available + 0 + 1 + write-only + + + FEVTAC12TOE + no description available + 1 + 1 + write-only + + + FEVTAC12CE + no description available + 2 + 1 + write-only + + + FEVTAC12EBE + no description available + 3 + 1 + write-only + + + FEVTAC12IE + no description available + 4 + 1 + write-only + + + RESERVED + no description available + 5 + 2 + read-only + + + FEVTCNIBAC12E + no description available + 7 + 1 + write-only + + + RESERVED + no description available + 8 + 8 + read-only + + + FEVTCTOE + no description available + 16 + 1 + write-only + + + FEVTCCE + no description available + 17 + 1 + write-only + + + FEVTCEBE + no description available + 18 + 1 + write-only + + + FEVTCIE + no description available + 19 + 1 + write-only + + + FEVTDTOE + no description available + 20 + 1 + write-only + + + FEVTDCE + no description available + 21 + 1 + write-only + + + FEVTDEBE + no description available + 22 + 1 + write-only + + + RESERVED + no description available + 23 + 1 + read-only + + + FEVTAC12E + no description available + 24 + 1 + write-only + + + RESERVED + no description available + 25 + 1 + read-only + + + FEVTTNE + no description available + 26 + 1 + write-only + + + RESERVED + no description available + 27 + 1 + read-only + + + FEVTDMAE + no description available + 28 + 1 + write-only + + + RESERVED + no description available + 29 + 2 + read-only + + + FEVTCINT + no description available + 31 + 1 + write-only + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + no description available + 0 + 2 + read-only + + + ADMALME + no description available + 2 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + ADMADCE + no description available + 3 + 1 + read-only + + + 1 + Error + #1 + + + 0 + No Error + #0 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + ADS_ADDR + no description available + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + no description available + 0 + 1 + read-write + + + DLL_CTRL_RESET + no description available + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + no description available + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + no description available + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + no description available + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + no description available + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + DLL_CTRL_SLV_UPDATE_INT + no description available + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + no description available + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + no description available + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + no description available + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + no description available + 2 + 7 + read-only + + + DLL_STS_REF_SEL + no description available + 9 + 7 + read-only + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + no description available + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + no description available + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + no description available + 8 + 7 + read-write + + + NXT_ERR + no description available + 15 + 1 + read-only + + + TAP_SEL_POST + no description available + 16 + 4 + read-only + + + TAP_SEL_OUT + no description available + 20 + 4 + read-only + + + TAP_SEL_PRE + no description available + 24 + 7 + read-only + + + PRE_ERR + no description available + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + EXT_DMA_EN + no description available + 0 + 1 + read-write + + + 0 + In any scenario, uSDHC does not send out external DMA request + #0 + + + 1 + When internal DMA is not active, the external DMA request will be sent out + #1 + + + + + VSELECT + no description available + 1 + 1 + read-write + + + 1 + Change the voltage to low voltage range, around 1.8V + #1 + + + 0 + Change the voltage to high voltage range, around 3.0V + #0 + + + + + CONFLICT_CHK_EN + no description available + 2 + 1 + read-write + + + 0 + conflict check disable + #0 + + + 1 + conflict check enable + #1 + + + + + AC12_WR_CHKBUSY_EN + no description available + 3 + 1 + read-write + + + 0 + Do not check busy after auto CMD12 for write data packet + #0 + + + 1 + Check busy after auto CMD12 for write data packet + #1 + + + + + DAT3_CD_POL + no description available + 4 + 1 + read-write + + + 0 + card detected when DATA3 is high + #0 + + + 1 + card detected when DATA3 is low + #1 + + + + + CD_POL + no description available + 5 + 1 + read-write + + + 0 + CD_B pin is low active + #0 + + + 1 + CD_B pin is high active + #1 + + + + + WP_POL + no description available + 6 + 1 + read-write + + + 0 + WP pin is high active + #0 + + + 1 + WP pin is low active + #1 + + + + + CLKONJ_IN_ABORT + no description available + 7 + 1 + read-write + + + 0 + the CLK output is active when sending abort command while data is transmitting even if the internal FIFO is full(for read) or empty(for write) + #0 + + + 1 + the CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is full(for read) or empty(for write) + #1 + + + + + FRC_SDCLK_ON + no description available + 8 + 1 + read-write + + + 0 + CLK active or inactive is fully controlled by the hardware + #0 + + + 1 + force CLK active + #1 + + + + + RESERVED + no description available + 9 + 1 + read-write + + + RESERVED + no description available + 10 + 1 + read-write + + + IPG_CLK_SOFT_EN + no description available + 11 + 1 + read-write + + + 0 + gate off the IPG_CLK + #0 + + + 1 + enable the IPG_CLK + #1 + + + + + HCLK_SOFT_EN + no description available + 12 + 1 + read-write + + + 0 + gate off the AHB clock. + #0 + + + 1 + enable the AHB clock. + #1 + + + + + IPG_PERCLK_SOFT_EN + no description available + 13 + 1 + read-write + + + 0 + gate off the ipg_perclk + #0 + + + 1 + enable the ipg_perclk + #1 + + + + + CARD_CLK_SOFT_EN + no description available + 14 + 1 + read-write + + + 0 + gate off the sd_clk + #0 + + + 1 + enable the sd_clk + #1 + + + + + CRC_CHK_DIS + no description available + 15 + 1 + read-write + + + 0 + check CRC16 for every read data packet and check CRC bits for every write data packet + #0 + + + 1 + ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + #1 + + + + + INT_ST_VAL + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 4 + read-write + + + RESERVED + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 1 + read-write + + + RESERVED + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + no description available + 0 + 4 + read-write + + + 0000 + SDCLK x 2^13 + #0000 + + + 0001 + SDCLK x 2^14 + #0001 + + + 0010 + SDCLK x 2^15 + #0010 + + + 0011 + SDCLK x 2^16 + #0011 + + + 0100 + SDCLK x 2^17 + #0100 + + + 0101 + SDCLK x 2^18 + #0101 + + + 0110 + SDCLK x 2^19 + #0110 + + + 0111 + SDCLK x 2^20 + #0111 + + + 1110 + SDCLK x 2^27 + #1110 + + + 1111 + SDCLK x 2^28 + #1111 + + + + + BOOT_ACK + no description available + 4 + 1 + read-write + + + 0 + No ack + #0 + + + 1 + Ack + #1 + + + + + BOOT_MODE + no description available + 5 + 1 + read-write + + + 0 + Normal boot + #0 + + + 1 + Alternative boot + #1 + + + + + BOOT_EN + no description available + 6 + 1 + read-write + + + 0 + Fast boot disable + #0 + + + 1 + Fast boot enable + #1 + + + + + AUTO_SABG_EN + no description available + 7 + 1 + read-write + + + DISABLE_TIME_OUT + no description available + 8 + 1 + read-write + + + 0 + Enable time out + #0 + + + 1 + Disable time out + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + BOOT_BLK_CNT + no description available + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x6 + 0xFFFFFFFF + + + SDR104_TIMING_DIS + no description available + 0 + 1 + read-write + + + 0 + The timeout counter for Ncr changes to 80, Ncrc changes to 21. + #0 + + + 1 + The timeout counter for Ncr changes to 72, Ncrc changes to 15. + #1 + + + + + SDR104_OE_DIS + no description available + 1 + 1 + read-write + + + 0 + Drive the CMD_OE/DATA_OE for one more clock cycle after the end bit. + #0 + + + 1 + Stop to drive the CMD_OE/DATA_OE at once after driving the end bit. + #1 + + + + + SDR104_NSD_DIS + no description available + 2 + 1 + read-write + + + 0 + Enable the interrupt window 9 cycles later after the end of the I/O abort command(or CMD12) is sent. + #0 + + + 1 + Enable the interrupt window 5 cycles later after the end of the I/O abort command(or CMD12) is sent. + #1 + + + + + CARD_INT_D3_TEST + no description available + 3 + 1 + read-write + + + 0 + Check the card interrupt only when DATA3 is high. + #0 + + + 1 + Check the card interrupt by ignoring the status of DATA3. + #1 + + + + + TUNING_8bit_EN + no description available + 4 + 1 + read-write + + + 00 + Tuning circuit only checks the DATA[3:0]. + #00 + + + 01 + Tuning circuit only checks the DATA0. + #01 + + + + + TUNING_1bit_EN + no description available + 5 + 1 + read-write + + + TUNING_CMD_EN + no description available + 6 + 1 + read-write + + + 0 + Auto tuning circuit doesn't check the CMD line. + #0 + + + 1 + Auto tuning circuit checks the CMD line. + #1 + + + + + CARD_INT_AUTO_CLR_DIS + no description available + 7 + 1 + read-write + + + 0 + Card interrupt status bit(CINT) can be cleared when Card Interrupt status enable bit is 0. + #0 + + + 1 + Card interrupt status bit(CINT) can only be cleared by writting a 1 to CINT bit. + #1 + + + + + RESERVED + no description available + 8 + 1 + read-only + + + RESERVED + no description available + 9 + 1 + read-only + + + RESERVED + no description available + 10 + 22 + read-only + + + + + + + I2C1 + I2C + I2C + I2C1_ + 0x21A0000 + + 0 + 0x12 + registers + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + ADR + no description available + 1 + 7 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + RSTA + no description available + 2 + 1 + write-only + + + 0 + No repeat start + #0 + + + 1 + Generates a Repeated Start condition + #1 + + + + + TXAK + no description available + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + #0 + + + 1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + #1 + + + + + MTX + no description available + 4 + 1 + read-write + + + 0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + #0 + + + 1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + #1 + + + + + MSTA + no description available + 5 + 1 + read-write + + + 0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + #0 + + + 1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + #1 + + + + + IIEN + no description available + 6 + 1 + read-write + + + 0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + #0 + + + 1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + #1 + + + + + IEN + no description available + 7 + 1 + read-write + + + 0 + The block is disabled, but registers can still be accessed. + #0 + + + 1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + no description available + 0 + 1 + read-only + + + 0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + #0 + + + 1 + A "No acknowledge" signal was detected at the ninth clock. + #1 + + + + + IIF + no description available + 1 + 1 + read-write + + + 0 + No I2C interrupt pending. + #0 + + + 1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + #1 + + + + + SRW + no description available + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + IAL + no description available + 4 + 1 + read-write + + + 0 + No arbitration lost. + #0 + + + 1 + Arbitration is lost. + #1 + + + + + IBB + no description available + 5 + 1 + read-only + + + 0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + #0 + + + 1 + Bus is busy. When Start is detected, IBB is set. + #1 + + + + + IAAS + no description available + 6 + 1 + read-only + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + #1 + + + + + ICF + no description available + 7 + 1 + read-only + + + 0 + Transfer is in progress. + #0 + + + 1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + + + I2C2 + I2C + I2C + I2C2_ + 0x21A4000 + + 0 + 0x12 + registers + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + ADR + no description available + 1 + 7 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + RSTA + no description available + 2 + 1 + write-only + + + 0 + No repeat start + #0 + + + 1 + Generates a Repeated Start condition + #1 + + + + + TXAK + no description available + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + #0 + + + 1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + #1 + + + + + MTX + no description available + 4 + 1 + read-write + + + 0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + #0 + + + 1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + #1 + + + + + MSTA + no description available + 5 + 1 + read-write + + + 0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + #0 + + + 1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + #1 + + + + + IIEN + no description available + 6 + 1 + read-write + + + 0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + #0 + + + 1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + #1 + + + + + IEN + no description available + 7 + 1 + read-write + + + 0 + The block is disabled, but registers can still be accessed. + #0 + + + 1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + no description available + 0 + 1 + read-only + + + 0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + #0 + + + 1 + A "No acknowledge" signal was detected at the ninth clock. + #1 + + + + + IIF + no description available + 1 + 1 + read-write + + + 0 + No I2C interrupt pending. + #0 + + + 1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + #1 + + + + + SRW + no description available + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + IAL + no description available + 4 + 1 + read-write + + + 0 + No arbitration lost. + #0 + + + 1 + Arbitration is lost. + #1 + + + + + IBB + no description available + 5 + 1 + read-only + + + 0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + #0 + + + 1 + Bus is busy. When Start is detected, IBB is set. + #1 + + + + + IAAS + no description available + 6 + 1 + read-only + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + #1 + + + + + ICF + no description available + 7 + 1 + read-only + + + 0 + Transfer is in progress. + #0 + + + 1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + + + I2C3 + I2C + I2C + I2C3_ + 0x21A8000 + + 0 + 0x12 + registers + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + ADR + no description available + 1 + 7 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + RSTA + no description available + 2 + 1 + write-only + + + 0 + No repeat start + #0 + + + 1 + Generates a Repeated Start condition + #1 + + + + + TXAK + no description available + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + #0 + + + 1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + #1 + + + + + MTX + no description available + 4 + 1 + read-write + + + 0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + #0 + + + 1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + #1 + + + + + MSTA + no description available + 5 + 1 + read-write + + + 0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + #0 + + + 1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + #1 + + + + + IIEN + no description available + 6 + 1 + read-write + + + 0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + #0 + + + 1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + #1 + + + + + IEN + no description available + 7 + 1 + read-write + + + 0 + The block is disabled, but registers can still be accessed. + #0 + + + 1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + no description available + 0 + 1 + read-only + + + 0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + #0 + + + 1 + A "No acknowledge" signal was detected at the ninth clock. + #1 + + + + + IIF + no description available + 1 + 1 + read-write + + + 0 + No I2C interrupt pending. + #0 + + + 1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + #1 + + + + + SRW + no description available + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + IAL + no description available + 4 + 1 + read-write + + + 0 + No arbitration lost. + #0 + + + 1 + Arbitration is lost. + #1 + + + + + IBB + no description available + 5 + 1 + read-only + + + 0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + #0 + + + 1 + Bus is busy. When Start is detected, IBB is set. + #1 + + + + + IAAS + no description available + 6 + 1 + read-only + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + #1 + + + + + ICF + no description available + 7 + 1 + read-only + + + 0 + Transfer is in progress. + #0 + + + 1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + + + I2C4 + I2C + I2C + I2C4_ + 0x21F8000 + + 0 + 0x12 + registers + + + + IADR + I2C Address Register + 0 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + ADR + no description available + 1 + 7 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + IFDR + I2C Frequency Divider Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + IC + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + + + I2CR + I2C Control Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + RSTA + no description available + 2 + 1 + write-only + + + 0 + No repeat start + #0 + + + 1 + Generates a Repeated Start condition + #1 + + + + + TXAK + no description available + 3 + 1 + read-write + + + 0 + An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. + #0 + + + 1 + No acknowledge signal response is sent (that is, the acknowledge bit = 1). + #1 + + + + + MTX + no description available + 4 + 1 + read-write + + + 0 + Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in the I2C status register (I2C_I2SR[SRW]). + #0 + + + 1 + Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. + #1 + + + + + MSTA + no description available + 5 + 1 + read-write + + + 0 + Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode. + #0 + + + 1 + Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode. + #1 + + + + + IIEN + no description available + 6 + 1 + read-write + + + 0 + I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs. + #0 + + + 1 + I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set. + #1 + + + + + IEN + no description available + 7 + 1 + read-write + + + 0 + The block is disabled, but registers can still be accessed. + #0 + + + 1 + The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2SR + I2C Status Register + 0xC + 16 + read-write + 0x81 + 0xFFFF + + + RXAK + no description available + 0 + 1 + read-only + + + 0 + An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus. + #0 + + + 1 + A "No acknowledge" signal was detected at the ninth clock. + #1 + + + + + IIF + no description available + 1 + 1 + read-write + + + 0 + No I2C interrupt pending. + #0 + + + 1 + An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific address in Slave Receive mode. Arbitration is lost. + #1 + + + + + SRW + no description available + 2 + 1 + read-only + + + 0 + Slave receive, master writing to slave + #0 + + + 1 + Slave transmit, master reading from slave + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + IAL + no description available + 4 + 1 + read-write + + + 0 + No arbitration lost. + #0 + + + 1 + Arbitration is lost. + #1 + + + + + IBB + no description available + 5 + 1 + read-only + + + 0 + Bus is idle. If a Stop signal is detected, IBB is cleared. + #0 + + + 1 + Bus is busy. When Start is detected, IBB is set. + #1 + + + + + IAAS + no description available + 6 + 1 + read-only + + + 0 + Not addressed + #0 + + + 1 + Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address. + #1 + + + + + ICF + no description available + 7 + 1 + read-only + + + 0 + Transfer is in progress. + #0 + + + 1 + Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer. + #1 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + + + I2DR + I2C Data I/O Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + DATA + no description available + 0 + 8 + read-write + + + RESERVED + no description available + 8 + 8 + read-only + + + + + + + ROMC + ROMC + ROMC_ + 0x21AC000 + + 0xD4 + 0x138 + registers + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + no description available + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + no description available + 0 + 8 + read-write + + + 0 + Address comparator triggers a opcode patch + #0 + + + 1 + Address comparator triggers a data fix + #1 + + + + + RESERVED + no description available + 8 + 21 + read-only + + + DIS + no description available + 29 + 1 + read-write + + + 0 + Does not affect any ROMC functions (default) + #0 + + + 1 + Disable all ROMC functions: data fixing, and opcode patching + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + no description available + 0 + 16 + read-write + + + 0 + Address comparator disabled + #0 + + + 1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + #1 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + no description available + 0 + 1 + read-write + + + 0 + ARM patch + #0 + + + 1 + THUMB patch (ignore if data fix) + #1 + + + + + ADDRX + no description available + 1 + 22 + read-write + + + RESERVED + no description available + 23 + 9 + read-only + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + no description available + 0 + 6 + read-only + + + 0 + Address Comparator 0 matched + #0 + + + 1 + Address Comparator 1 matched + #1 + + + + + RESERVED + no description available + 6 + 11 + read-only + + + SW + no description available + 17 + 1 + read-write + + + 0 + no event or comparator collisions + #0 + + + 1 + a collision has occurred + #1 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + + + MMDC1 + MMDC + MMDC + MMDC1_ + 0x21B0000 + + 0 + 0x8C4 + registers + + + + MDCTL + MMDC Core Control Register + 0 + 32 + read-write + 0x3110000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + DSIZ + no description available + 16 + 2 + read-write + + + 0 + 16-bit data bus + #0 + + + 1 + 32-bit data bus + #1 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + BL + no description available + 19 + 1 + read-write + + + 0 + Burst Length 4 is used + #0 + + + 1 + Burst Length 8 is used + #1 + + + + + COL + no description available + 20 + 3 + read-write + + + 0 + 9 bits column + #0 + + + 1 + 10 bits column + #1 + + + 10 + 11 bits column + #10 + + + 11 + 8 bits column + #11 + + + 100 + 12 bits column + #100 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + ROW + no description available + 24 + 3 + read-write + + + 000 + 11 bits Row + #000 + + + 001 + 12 bits Row + #001 + + + 010 + 13 bits Row + #010 + + + 011 + 14 bits Row + #011 + + + 100 + 15 bits Row + #100 + + + 101 + 16 bits Row + #101 + + + + + RESERVED + no description available + 27 + 3 + read-only + + + SDE_1 + no description available + 30 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + SDE_0 + no description available + 31 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + MDPDC + MMDC Core Power Down Control Register + 0x4 + 32 + read-write + 0x30012 + 0xFFFFFFFF + + + tCKSRE + no description available + 0 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycles + #1 + + + 110 + 6cycles + #110 + + + 111 + 7cycles + #111 + + + + + tCKSRX + no description available + 3 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycles + #1 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + BOTH_CS_PD + no description available + 6 + 1 + read-write + + + 0 + Each chip select can enter power down independently according to its configuration. + #0 + + + 1 + Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained. + #1 + + + + + SLOW_PD + no description available + 7 + 1 + read-write + + + 0 + Fast mode. + #0 + + + 1 + Slow mode. + #1 + + + + + PWDT_0 + no description available + 8 + 4 + read-write + + + PWDT_1 + no description available + 12 + 4 + read-write + + + tCKE + no description available + 16 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 19 + 5 + read-only + + + PRCT_0 + no description available + 24 + 3 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + PRCT_1 + no description available + 28 + 3 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MDOTC + MMDC Core ODT Timing Control Register + 0x8 + 32 + read-write + 0x12272000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + tODT_idle_off + no description available + 4 + 5 + read-write + + + 0 + 0 cycle (turned off at the earliest possible time) + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11110 + 30 cycles + #11110 + + + 11111 + 31 cycles + #11111 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + tODTLon + no description available + 12 + 3 + read-write + + + 0 + - 0x1 Reserved + #0 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + tAXPD + no description available + 16 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tANPD + no description available + 20 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tAONPD + no description available + 24 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tAOFPD + no description available + 27 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + MDCFG0 + MMDC Core Timing Configuration Register 0 + 0xC + 32 + read-write + 0x323622D3 + 0xFFFFFFFF + + + tCL + no description available + 0 + 4 + read-write + + + 0 + 3 cycles + #0 + + + 1 + 4 cycles + #1 + + + 10 + 5 cycles + #10 + + + 11 + 6 cycles + #11 + + + 100 + 7 cycles + #100 + + + 101 + 8 cycles + #101 + + + 110 + 9 cycles + #110 + + + 111 + 10 cycles + #111 + + + 1000 + 11 cycles + #1000 + + + 1001 + - 0xF Reserved + #1001 + + + + + tFAW + no description available + 4 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + 32 clocks + #11111 + + + + + tXPDLL + no description available + 9 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tXP + no description available + 13 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tXS + no description available + 16 + 8 + read-write + + + 0 + - 0x15 reserved + #0 + + + 10110 + 23 clocks + #10110 + + + 10111 + 24 clocks + #10111 + + + 11111110 + 255 clocks + #11111110 + + + 11111111 + 256 clocks + #11111111 + + + + + tRFC + no description available + 24 + 8 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11111110 + 255 clocks + #11111110 + + + 11111111 + 256 clocks + #11111111 + + + + + + + MDCFG1 + MMDC Core Timing Configuration Register 1 + 0x10 + 32 + read-write + 0xB6B18A23 + 0xFFFFFFFF + + + tCWL + no description available + 0 + 3 + read-write + + + 0 + 2cycles ( DDR2/ DDR3) , 1 cycle (LPDDR2) + #0 + + + 1 + 3cycles ( DDR2/ DDR3) , 2 cycles (LPDDR2) + #1 + + + 10 + 4cycles ( DDR2/ DDR3) , 3 cycles (LPDDR2) + #10 + + + 11 + 5cycles ( DDR2/ DDR3) , 4 cycles (LPDDR2) + #11 + + + 100 + 6cycles ( DDR2/ DDR3) , 5 cycles (LPDDR2) + #100 + + + 101 + 7cycles ( DDR2/ DDR3) , 6 cycles (LPDDR2) + #101 + + + 110 + 8cycles ( DDR2/ DDR3) , 7 cycles (LPDDR2) + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 3 + 2 + read-only + + + tMRD + no description available + 5 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tWR + no description available + 9 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 12 + 3 + read-only + + + tRPA + no description available + 15 + 1 + read-write + + + 0 + Will be equal to: tRP. + #0 + + + 1 + Will be equal to: tRP+1. + #1 + + + + + tRAS + no description available + 16 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + Reserved + #11111 + + + + + tRC + no description available + 21 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + 32 clocks + #11111 + + + + + tRP + no description available + 26 + 3 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11 + 4 clocks + #11 + + + 100 + 5 clocks + #100 + + + 101 + 6 clocks + #101 + + + 110 + 7 clocks + #110 + + + 111 + 8 clocks + #111 + + + + + tRCD + no description available + 29 + 3 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11 + 4 clocks + #11 + + + 100 + 5 clocks + #100 + + + 101 + 6 clocks + #101 + + + 110 + 7 clocks + #110 + + + 111 + 8 clocks + #111 + + + + + + + MDCFG2 + MMDC Core Timing Configuration Register 2 + 0x14 + 32 + read-write + 0xC70092 + 0xFFFFFFFF + + + tRRD + no description available + 0 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + Reserved + #111 + + + + + tWTR + no description available + 3 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tRTP + no description available + 6 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + tDLLK + no description available + 16 + 9 + read-write + + + 0 + 1 cycle. + #0 + + + 1 + 2 cycles. + #1 + + + 10 + 3 cycles. + #10 + + + 11000111 + 200 cycles (JEDEC value for DDR2). + #11000111 + + + 111111110 + 511 cycles. + #111111110 + + + 111111111 + 512 cycles (JEDEC value for DDR3). + #111111111 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + MDMISC + MMDC Core Miscellaneous Register + 0x18 + 32 + read-write + 0x1600 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + RST + no description available + 1 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Assert reset to the MMDC. + #1 + + + + + LPDDR2_2CH + no description available + 2 + 1 + read-write + + + 0 + 1-channel mode (DDR3) + #0 + + + 1 + 2-channels mode (LPDDR2) + #1 + + + + + DDR_TYPE + no description available + 3 + 2 + read-write + + + 0 + DDR3 device is used. (Default) + #0 + + + 1 + LPDDR2 device is used. + #1 + + + 10 + DDR2 device is used. + #10 + + + 11 + Reserved. + #11 + + + 10 + Reserved. + #10 + + + 11 + Reserved. + #11 + + + + + DDR_4_BANK + no description available + 5 + 1 + read-write + + + 0 + 8 banks device is being used. (Default) + #0 + + + 1 + 4 banks device is being used + #1 + + + + + RALAT + no description available + 6 + 3 + read-write + + + 0 + no additional latency. + #0 + + + 1 + 1 cycle additional latency. + #1 + + + 10 + 2 cycles additional latency. + #10 + + + 11 + 3 cycles additional latency. + #11 + + + 100 + 4 cycles additional latency. + #100 + + + 101 + 5 cycles additional latency. + #101 + + + 110 + 6 cycles additional latency. + #110 + + + 111 + 7 cycles additional latency. + #111 + + + + + MIF3_MODE + no description available + 9 + 2 + read-write + + + 00 + Disable prediction. + #00 + + + 01 + Enable prediction based on : Valid access on first pipe line stage. + #01 + + + 10 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus. + #10 + + + 11 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue. + #11 + + + + + LPDDR2_S2 + no description available + 11 + 1 + read-write + + + 0 + LPDDR2-S4 device is used. + #0 + + + 1 + LPDDR2-S2 device is used. + #1 + + + + + BI_ON + no description available + 12 + 1 + read-write + + + 0 + Banks are not interleaved, and address will be decoded as bank-row-column + #0 + + + 1 + Banks are interleaved, and address will be decoded as row-bank-column + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + WALAT + no description available + 16 + 2 + read-write + + + 0 + No additional latency required. + #0 + + + 1 + 1 cycle additional delay + #1 + + + 10 + 2 cycles additional delay + #10 + + + 11 + 3 cycles additional delay + #11 + + + + + LHD + no description available + 18 + 1 + read-write + + + 0 + Latency hiding on. + #0 + + + 1 + Latency hiding disable. + #1 + + + + + ADDR_MIRROR + no description available + 19 + 1 + read-write + + + 0 + Address mirroring disabled. + #0 + + + 1 + Address mirroring enabled. + #1 + + + + + CALIB_PER_CS + no description available + 20 + 1 + read-write + + + 0 + Calibration is targetted to CS0 + #0 + + + 1 + Calibration is targetted to CS1 + #1 + + + + + RESERVED + no description available + 21 + 9 + read-only + + + CS1_RDY + no description available + 30 + 1 + read-only + + + 0 + Device in wake-up period. + #0 + + + 1 + Device is ready for initialization. + #1 + + + + + CS0_RDY + no description available + 31 + 1 + read-only + + + 0 + Device in wake-up period. + #0 + + + 1 + Device is ready for initialization. + #1 + + + + + + + MDSCR + MMDC Core Special Command Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_BA + no description available + 0 + 3 + read-write + + + 0 + bank address 0 + #0 + + + 1 + bank address 1 + #1 + + + 10 + bank address 2 + #10 + + + 111 + bank address 7 + #111 + + + + + CMD_CS + no description available + 3 + 1 + read-write + + + 0 + to Chip-select 0 + #0 + + + 1 + to Chip-select 1 + #1 + + + + + CMD + no description available + 4 + 3 + read-write + + + 0 + Normal operation + #0 + + + 1 + Precharge all, command is sent independently of bank status (set correct CMD_CS). Will be issued even if banks are closed. Mainly used for init sequence purpose. + #1 + + + 10 + Auto-Refresh Command (set correct CMD_CS). + #10 + + + 11 + Load Mode Register Command ( DDR2/ DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2, set correct CMD_CS, MR_OP, MR_ADDR) + #11 + + + 100 + ZQ calibration ( DDR2/ DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 ) + #100 + + + 101 + Precharge all, only if banks open (set correct CMD_CS). + #101 + + + 110 + MRR command (LPDDR2, set correct CMD_CS, MR_ADDR) + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + WL_EN + no description available + 9 + 1 + read-write + + + 0 + Exit write leveling mode or stay in normal mode. + #0 + + + 1 + Write leveling entry command was sent. + #1 + + + + + MRR_READ_DATA_VALID + no description available + 10 + 1 + read-only + + + 0 + Cleared upon the assertion of MRR command + #0 + + + 1 + Set after MRR data is valid and stored at MDMRR register. + #1 + + + + + RESERVED + no description available + 11 + 3 + read-only + + + CON_ACK + no description available + 14 + 1 + read-only + + + 0 + Configuration of MMDC registers is forbidden. + #0 + + + 1 + Configuration of MMDC registers is permitted. + #1 + + + + + CON_REQ + no description available + 15 + 1 + read-write + + + 0 + No request to configure MMDC. + #0 + + + 1 + A request to configure MMDC is valid + #1 + + + + + CMD_ADDR_LSB_MR_ADDR + no description available + 16 + 8 + read-write + + + CMD_ADDR_MSB_MR_OP + no description available + 24 + 8 + read-write + + + + + MDREF + MMDC Core Refresh Control Register + 0x20 + 32 + read-write + 0xC000 + 0xFFFFFFFF + + + START_REF + no description available + 0 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Start a refresh cycle. + #1 + + + + + RESERVED + no description available + 1 + 10 + read-only + + + REFR + no description available + 11 + 3 + read-write + + + 0 + 1 refresh + #0 + + + 1 + 2 refreshes + #1 + + + 10 + 3 refreshes + #10 + + + 11 + 4 refreshes + #11 + + + 100 + 5 refreshes + #100 + + + 101 + 6 refreshes + #101 + + + 110 + 7 refreshes + #110 + + + 111 + 8 refreshes + #111 + + + + + REF_SEL + no description available + 14 + 2 + read-write + + + 0 + Periodic refresh cycles will be triggered in frequency of 64KHz. + #0 + + + 1 + Periodic refresh cycles will be triggered in frequency of 32KHz. + #1 + + + + + REF_CNT + no description available + 16 + 16 + read-write + + + 0 + Reserved. + #0 + + + 1 + 1 cycle. + #1 + + + 1111111111111110 + 65534 cycles. + #1111111111111110 + + + 1111111111111111 + 65535 cycles. + #1111111111111111 + + + + + + + MDRWD + MMDC Core Read/Write Command Delay Register + 0x2C + 32 + read-write + 0xF9F26D2 + 0xFFFFFFFF + + + RTR_DIFF + no description available + 0 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RTW_DIFF + no description available + 3 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + WTW_DIFF + no description available + 6 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles (Default) + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + WTR_DIFF + no description available + 9 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles (Default) + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RTW_SAME + no description available + 12 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + tDAI + no description available + 16 + 13 + read-write + + + 0 + 1 cycle + #0 + + + 111110011111 + 4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock). + #111110011111 + + + 1111111111111 + 8192 cycles + #1111111111111 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MDOR + MMDC Core Out of Reset Delays Register + 0x30 + 32 + read-write + 0x9F0E0E + 0xFFFFFFFF + + + RST_to_CKE + no description available + 0 + 6 + read-write + + + 0 + Reserved + #0 + + + 1 + Reserved + #1 + + + 10 + Reserved + #10 + + + 11 + 1 cycles + #11 + + + 10000 + 14 cycles (JEDEC value for DDR2/LPDDR2) - total of 200 us + #10000 + + + 100011 + 33 cycles (JEDEC value for DDR3) - total of 500 us + #100011 + + + 111110 + 60 cycles + #111110 + + + 111111 + 61 cycles + #111111 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + SDE_to_RST + no description available + 8 + 6 + read-write + + + 0 + Reserved + #0 + + + 1 + Reserved + #1 + + + 10 + Reserved + #10 + + + 11 + 1 cycles + #11 + + + 100 + 2 cycles + #100 + + + 10000 + 14 cycles (Jedec value for DDR3) - total of 200 us + #10000 + + + 111110 + 60 cycles + #111110 + + + 111111 + 61 cycles + #111111 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + tXPR + no description available + 16 + 8 + read-write + + + 0 + Reserved + #0 + + + 1 + 2 cycles + #1 + + + 10 + 3 cycles + #10 + + + 11111110 + 255 cycles + #11111110 + + + 11111111 + 256 cycles + #11111111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + MDMRR + MMDC Core MRR Data Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + MRR_READ_DATA0 + no description available + 0 + 8 + read-only + + + MRR_READ_DATA1 + no description available + 8 + 8 + read-only + + + MRR_READ_DATA2 + no description available + 16 + 8 + read-only + + + MRR_READ_DATA3 + no description available + 24 + 8 + read-only + + + + + MDCFG3LP + MMDC Core Timing Configuration Register 3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + tRPab_LP + no description available + 0 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + tRPpb_LP + no description available + 4 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + tRCD_LP + no description available + 8 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + RC_LP + no description available + 16 + 6 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 111110 + 63 clocks + #111110 + + + 111111 + Reserved + #111111 + + + + + RESERVED + no description available + 22 + 10 + read-only + + + + + MDMR4 + MMDC Core MR4 Derating Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + UPDATE_DE_REQ + no description available + 0 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR + #1 + + + + + UPDATE_DE_ACK + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + tRCD_DE + no description available + 4 + 1 + read-write + + + 0 + Original tRCD is used. + #0 + + + 1 + tRCD is derated in 1 cycle. + #1 + + + + + tRC_DE + no description available + 5 + 1 + read-write + + + 0 + Original tRC is used. + #0 + + + 1 + tRC is derated in 1 cycle. + #1 + + + + + tRAS_DE + no description available + 6 + 1 + read-write + + + 0 + Original tRAS is used. + #0 + + + 1 + tRAS is derated in 1 cycle. + #1 + + + + + tRP_DE + no description available + 7 + 1 + read-write + + + 0 + Original tRP is used. + #0 + + + 1 + tRP is derated in 1 cycle. + #1 + + + + + tRRD_DE + no description available + 8 + 1 + read-write + + + 0 + Original tRRD is used. + #0 + + + 1 + tRRD is derated in 1 cycle. + #1 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + MDASP + MMDC Core Address Space Partition Register + 0x40 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + CS0_END + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 25 + read-only + + + + + MAARCR + MMDC Core AXI Reordering Control Regsiter + 0x400 + 32 + read-write + 0x514201F0 + 0xFFFFFFFF + + + ARCR_GUARD + no description available + 0 + 4 + read-write + + + 0000 + 15 (default) + #0000 + + + 0001 + 16 + #0001 + + + 1111 + 30 + #1111 + + + + + ARCR_DYN_MAX + no description available + 4 + 4 + read-write + + + 0000 + 0 + #0000 + + + 0001 + 1 + #0001 + + + 1111 + 15 (default) + #1111 + + + + + ARCR_DYN_JMP + no description available + 8 + 4 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + ARCR_ACC_HIT + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + ARCR_PAG_HIT + no description available + 20 + 3 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + ARCR_RCH_EN + no description available + 24 + 1 + read-write + + + 0 + normal prioritization, no bypassing + #0 + + + 1 + accesses with QoS=='F' bypass the arbitration + #1 + + + + + RESERVED + no description available + 25 + 3 + read-only + + + ARCR_EXC_ERR_EN + no description available + 28 + 1 + read-write + + + 0 + violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00) + #0 + + + 1 + violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10) + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + ARCR_SEC_ERR_EN + no description available + 30 + 1 + read-write + + + 0 + security violation results in OKAY response (rresp/bresp=2'b00) + #0 + + + 1 + security violation results in SLAVE Error response (rresp/bresp=2'b10) + #1 + + + + + ARCR_SEC_ERR_LOCK + no description available + 31 + 1 + read-write + + + 0 + ARCR_SEC_ERR_EN is unlocked, so can be updated any moment + #0 + + + 1 + ARCR_SEC_ERR_EN is locked, so it can't be updated + #1 + + + + + + + MAPSR + MMDC Core Power Saving Control and Status Register + 0x404 + 32 + read-write + 0x1007 + 0xFFFFFFFF + + + PSD + no description available + 0 + 1 + read-write + + + 0 + power saving enabled + #0 + + + 1 + power saving disabled (default) + #1 + + + + + RESERVED + no description available + 1 + 3 + read-only + + + PSS + no description available + 4 + 1 + read-only + + + 0 + not in power saving + #0 + + + 1 + power saving + #1 + + + + + RIS + no description available + 5 + 1 + read-only + + + 0 + idle + #0 + + + 1 + not idle + #1 + + + + + WIS + no description available + 6 + 1 + read-only + + + 0 + idle + #0 + + + 1 + not idle + #1 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + PST + no description available + 8 + 8 + read-write + + + 00000000 + Reserved - this value is forbidden. + #00000000 + + + 00000001 + timer is configured to 64 clock cycles. + #00000001 + + + 00000010 + timer is configured to 128 clock cycles. + #00000010 + + + 00010000 + (Default)- 1024 clock cycles. + #00010000 + + + 11111111 + timer clock is configured to 16320 clock cycles. + #11111111 + + + + + RESERVED + no description available + 16 + 4 + read-only + + + LPMD + no description available + 20 + 1 + read-write + + + 0 + no lpmd request + #0 + + + 1 + lpmd request + #1 + + + + + DVFS + no description available + 21 + 1 + read-write + + + 0 + no dvfs request + #0 + + + 1 + dvfs request + #1 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + LPACK + no description available + 24 + 1 + read-only + + + DVACK + no description available + 25 + 1 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + MAEXIDR0 + MMDC Core Exclusive ID Monitor Register0 + 0x408 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EXC_ID_MONITOR0 + no description available + 0 + 16 + read-write + + + EXC_ID_MONITOR1 + no description available + 16 + 16 + read-write + + + + + MAEXIDR1 + MMDC Core Exclusive ID Monitor Register1 + 0x40C + 32 + read-write + 0x600040 + 0xFFFFFFFF + + + EXC_ID_MONITOR2 + no description available + 0 + 16 + read-write + + + EXC_ID_MONITOR3 + no description available + 16 + 16 + read-write + + + + + MADPCR0 + MMDC Core Debug and Profiling Control Register 0 + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_EN + no description available + 0 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + DBG_RST + no description available + 1 + 1 + read-write + + + 0 + no reset + #0 + + + 1 + reset + #1 + + + + + PRF_FRZ + no description available + 2 + 1 + read-write + + + 0 + profiling counters are not frozen + #0 + + + 1 + profiling counters are frozen + #1 + + + + + CYC_OVF + no description available + 3 + 1 + read-write + + + 0 + no overflow + #0 + + + 1 + overflow + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SBS_EN + no description available + 8 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + SBS + no description available + 9 + 1 + read-write + + + 1 + Lanuch AXI pending access toward the DDR + #1 + + + 0 + No access will be launced toward the DDR + #0 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + MADPCR1 + MMDC Core Debug and Profiling Control Register 1 + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRF_AXI_ID + no description available + 0 + 16 + read-write + + + PRF_AXI_ID_MASK + no description available + 16 + 16 + read-write + + + 1 + AXI ID specific bit is chosen for profiling + #1 + + + 0 + AXI ID specific bit is ignored (don't care) + #0 + + + + + + + MADPSR0 + MMDC Core Debug and Profiling Status Register 0 + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + CYC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR1 + MMDC Core Debug and Profiling Status Register 1 + 0x41C + 32 + read-only + 0 + 0xFFFFFFFF + + + BUSY_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR2 + MMDC Core Debug and Profiling Status Register 2 + 0x420 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_ACC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR3 + MMDC Core Debug and Profiling Status Register 3 + 0x424 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_ACC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR4 + MMDC Core Debug and Profiling Status Register 4 + 0x428 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_BYTES_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR5 + MMDC Core Debug and Profiling Status Register 5 + 0x42C + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_BYTES_COUNT + no description available + 0 + 32 + read-only + + + + + MASBS0 + MMDC Core Step By Step Address Register + 0x430 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_ADDR + no description available + 0 + 32 + read-only + + + + + MASBS1 + MMDC Core Step By Step Address Attributes Register + 0x434 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_VLD + no description available + 0 + 1 + read-only + + + 0 + not valid + #0 + + + 1 + valid + #1 + + + + + SBS_TYPE + no description available + 1 + 1 + read-only + + + 0 + write + #0 + + + 1 + read + #1 + + + + + SBS_LOCK + no description available + 2 + 2 + read-only + + + SBS_PROT + no description available + 4 + 3 + read-only + + + SBS_SIZE + no description available + 7 + 3 + read-only + + + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 32 bits + #010 + + + 011 + 64 bits + #011 + + + 100 + 128bits + #100 + + + + + SBS_BURST + no description available + 10 + 2 + read-only + + + 00 + FIXED + #00 + + + 01 + INCR burst + #01 + + + 10 + WRAP burst + #10 + + + 11 + reserved + #11 + + + + + SBS_BUFF + no description available + 12 + 1 + read-only + + + SBS_LEN + no description available + 13 + 3 + read-only + + + 000 + burst of length 1 + #000 + + + 001 + burst of length 2 + #001 + + + 111 + burst of length 8 + #111 + + + + + SBS_AXI_ID + no description available + 16 + 16 + read-only + + + + + MAGENP + MMDC Core General Purpose Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP31_GP0 + no description available + 0 + 32 + read-write + + + + + MPZQHWCTRL + MMDC PHY ZQ HW control register + 0x800 + 32 + read-write + 0xA1380000 + 0xFFFFFFFF + + + ZQ_MODE + no description available + 0 + 2 + read-write + + + 0 + No ZQ calibration is issued. (Default) + #0 + + + 1 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh. + #1 + + + 10 + ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh + #10 + + + 11 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh + #11 + + + + + ZQ_HW_PER + no description available + 2 + 4 + read-write + + + 0000 + ZQ calibration is performed every 1 ms. + #0000 + + + 0001 + ZQ calibration is performed every 2 ms. + #0001 + + + 0010 + ZQ calibration is performed every 4 ms. + #0010 + + + 1010 + ZQ calibration is performed every 1 ms. + #1010 + + + 1110 + ZQ calibration is performed every 16 ms. + #1110 + + + 1111 + ZQ calibration is performed every 32 ms. + #1111 + + + + + ZQ_HW_PU_RES + no description available + 6 + 5 + read-only + + + 00000 + Min. resistance. + #00000 + + + 11111 + Max. resistance. + #11111 + + + + + ZQ_HW_PD_RES + no description available + 11 + 5 + read-only + + + 00000 + Max. resistance. + #00000 + + + 11111 + Min. resistance. + #11111 + + + + + ZQ_HW_FOR + no description available + 16 + 1 + read-write + + + TZQ_INIT + no description available + 17 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles + #010 + + + 011 + 256 cycles + #011 + + + 100 + 512 cycles - Default (JEDEC value for DDR3) + #100 + + + 101 + 1024 cycles + #101 + + + + + TZQ_OPER + no description available + 20 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles + #010 + + + 011 + 256 cycles - Default (JEDEC value for DDR3) + #011 + + + 100 + 512 cycles + #100 + + + 101 + 1024 cycles + #101 + + + + + TZQ_CS + no description available + 23 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles (Default) + #010 + + + 011 + 256 cycles + #011 + + + 100 + 512 cycles + #100 + + + 101 + 1024 cycles + #101 + + + + + RESERVED + no description available + 26 + 1 + read-only + + + ZQ_EARLY_COMPARATOR_EN_TIMER + no description available + 27 + 5 + read-write + + + 0 + - 0x6 Reserved + #0 + + + 111 + 8 cycles + #111 + + + 10100 + 21 cycles (Default) + #10100 + + + 11110 + 31 cycles + #11110 + + + 11111 + 32 cycles + #11111 + + + + + + + MPZQSWCTRL + MMDC PHY ZQ SW control register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZQ_SW_FOR + no description available + 0 + 1 + read-write + + + ZQ_SW_RES + no description available + 1 + 1 + read-only + + + 0 + Current ZQ calibration voltage is less than VDD/2. + #0 + + + 1 + Current ZQ calibration voltage is more than VDD/2 + #1 + + + + + ZQ_SW_PU_VAL + no description available + 2 + 5 + read-write + + + 00000 + Min. resistance. + #00000 + + + 11111 + Max. resistance. + #11111 + + + + + ZQ_SW_PD_VAL + no description available + 7 + 5 + read-write + + + 00000 + Max. resistance. + #00000 + + + 11111 + Min. resistance. + #11111 + + + + + ZQ_SW_PD + no description available + 12 + 1 + read-write + + + 0 + PU resistor calibration + #0 + + + 1 + PD resistor calibration + #1 + + + + + USE_ZQ_SW_VAL + no description available + 13 + 1 + read-write + + + 0 + Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls. + #0 + + + 1 + Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls. + #1 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + ZQ_CMP_OUT_SMP + no description available + 16 + 2 + read-write + + + 00 + 7 cycles + #00 + + + 01 + 15 cycles + #01 + + + 10 + 23 cycles + #10 + + + 11 + 31 cycles + #11 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + MPWLGCR + MMDC PHY Write Leveling Configuration and Error Status Register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WL_EN + no description available + 0 + 1 + read-write + + + SW_WL_EN + no description available + 1 + 1 + read-write + + + SW_WL_CNT_EN + no description available + 2 + 1 + read-write + + + 0 + MMDC doesn't count 25+15 cycles before issuing write-leveling DQS. + #0 + + + 1 + MMDC counts 25+15 cycles before issuing write-leveling DQS. + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + WL_SW_RES0 + no description available + 4 + 1 + read-only + + + 0 + DQS0 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS0 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES1 + no description available + 5 + 1 + read-only + + + 0 + DQS1 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS1 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES2 + no description available + 6 + 1 + read-only + + + 0 + DQS2 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS2 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES3 + no description available + 7 + 1 + read-only + + + 0 + DQS3 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS3 sampled high CK during SW write-leveling. + #1 + + + + + WL_HW_ERR0 + no description available + 8 + 1 + read-only + + + 0 + No error was found on byte0 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte0 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR1 + no description available + 9 + 1 + read-only + + + 0 + No error was found on byte1 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte1 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR2 + no description available + 10 + 1 + read-only + + + 0 + No error was found on byte2 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte2 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR3 + no description available + 11 + 1 + read-only + + + 0 + No error was found on byte3 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte3 during write-leveling HW calibration. + #1 + + + + + RESERVED + no description available + 12 + 20 + read-only + + + + + MPWLDECTRL0 + MMDC PHY Write Leveling Delay Control Register 0 + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_HC_DEL0 + no description available + 8 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL0 + no description available + 9 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + WL_DL_ABS_OFFSET1 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_HC_DEL1 + no description available + 24 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL1 + no description available + 25 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPWLDECTRL1 + MMDC PHY Write Leveling Delay Control Register 1 + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET2 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_HC_DEL2 + no description available + 8 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL2 + no description available + 9 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + WL_DL_ABS_OFFSET3 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_HC_DEL3 + no description available + 24 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL3 + no description available + 25 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPWLDLST + MMDC PHY Write Leveling delay-line Status Register + 0x814 + 32 + read-only + 0 + 0xFFFFFFFF + + + WL_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + WL_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPODTCTRL + MMDC PHY ODT control register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + ODT_WR_PAS_EN + no description available + 0 + 1 + read-write + + + 0 + Inactive CS ODT pin is disabled during write accesses to other CS. + #0 + + + 1 + Inactive CS ODT pin is enabled during write accesses to other CS. + #1 + + + + + ODT_WR_ACT_EN + no description available + 1 + 1 + read-write + + + 0 + Active CS ODT pin is disabled during write access. + #0 + + + 1 + Active CS ODT pin is enabled during write access. + #1 + + + + + ODT_RD_PAS_EN + no description available + 2 + 1 + read-write + + + 0 + Inactive CS ODT pin is disabled during read accesses to other CS. + #0 + + + 1 + Inactive CS ODT pin is enabled during read accesses to other CS. + #1 + + + + + ODT_RD_ACT_EN + no description available + 3 + 1 + read-write + + + 0 + Active CS ODT pin is disabled during read access. + #0 + + + 1 + Active CS ODT pin is enabled during read access. + #1 + + + + + ODT0_INT_RES + no description available + 4 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + ODT1_INT_RES + no description available + 8 + 3 + read-write + + + 0000 + Rtt_Nom Disabled. + #0000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + ODT2_INT_RES + no description available + 12 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + ODT3_INT_RES + no description available + 16 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + MPRDDQBY0DL + MMDC PHY Read DQ Byte0 Delay Register + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq0_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq0 delay + #000 + + + 001 + Add dq0 delay of 1 delay unit + #001 + + + 010 + Add dq0 delay of 2 delay units. + #010 + + + 011 + Add dq0 delay of 3 delay units. + #011 + + + 100 + Add dq0 delay of 4 delay units. + #100 + + + 101 + Add dq0 delay of 5 delay units. + #101 + + + 110 + Add dq0 delay of 6 delay units. + #110 + + + 111 + Add dq0 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq1_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq1 delay + #000 + + + 001 + Add dq1 delay of 1 delay unit + #001 + + + 010 + Add dq1 delay of 2 delay units. + #010 + + + 011 + Add dq1 delay of 3 delay units. + #011 + + + 100 + Add dq1 delay of 4 delay units. + #100 + + + 101 + Add dq1 delay of 5 delay units. + #101 + + + 110 + Add dq1 delay of 6 delay units. + #110 + + + 111 + Add dq1 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq2_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq2 delay + #000 + + + 001 + Add dq2 delay of 1 delay unit + #001 + + + 010 + Add dq2 delay of 2 delay units. + #010 + + + 011 + Add dq2 delay of 3 delay units. + #011 + + + 100 + Add dq2 delay of 4 delay units. + #100 + + + 101 + Add dq2 delay of 5 delay units. + #101 + + + 110 + Add dq2 delay of 6 delay units. + #110 + + + 111 + Add dq2 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq3_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq3 delay + #000 + + + 001 + Add dq3 delay of 1 delay unit + #001 + + + 010 + Add dq3 delay of 2 delay units. + #010 + + + 011 + Add dq3 delay of 3 delay units. + #011 + + + 100 + Add dq3 delay of 4 delay units. + #100 + + + 101 + Add dq3 delay of 5 delay units. + #101 + + + 110 + Add dq3 delay of 6 delay units. + #110 + + + 111 + Add dq3 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq4_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq4 delay + #000 + + + 001 + Add dq4 delay of 1 delay unit + #001 + + + 010 + Add dq4 delay of 2 delay units. + #010 + + + 011 + Add dq4 delay of 3 delay units. + #011 + + + 100 + Add dq4 delay of 4 delay units. + #100 + + + 101 + Add dq4 delay of 5 delay units. + #101 + + + 110 + Add dq4 delay of 6 delay units. + #110 + + + 111 + Add dq4 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq5_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq5 delay + #000 + + + 001 + Add dq5 delay of 1 delay unit + #001 + + + 010 + Add dq5 delay of 2 delay units. + #010 + + + 011 + Add dq5 delay of 3 delay units. + #011 + + + 100 + Add dq5 delay of 4 delay units. + #100 + + + 101 + Add dq5 delay of 5 delay units. + #101 + + + 110 + Add dq5 delay of 6 delay units. + #110 + + + 111 + Add dq5 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq6_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq6 delay + #000 + + + 001 + Add dq6 delay of 1 delay unit + #001 + + + 010 + Add dq6 delay of 2 delay units. + #010 + + + 011 + Add dq6 delay of 3 delay units. + #011 + + + 100 + Add dq6 delay of 4 delay units. + #100 + + + 101 + Add dq6 delay of 5 delay units. + #101 + + + 110 + Add dq6 delay of 6 delay units. + #110 + + + 111 + Add dq6 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq7_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq7 delay + #000 + + + 001 + Add dq7 delay of 1 delay unit + #001 + + + 010 + Add dq7 delay of 2 delay units. + #010 + + + 011 + Add dq7 delay of 3 delay units. + #011 + + + 100 + Add dq7 delay of 4 delay units. + #100 + + + 101 + Add dq7 delay of 5 delay units. + #101 + + + 110 + Add dq7 delay of 6 delay units. + #110 + + + 111 + Add dq7 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY1DL + MMDC PHY Read DQ Byte1 Delay Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq8_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq8 delay + #000 + + + 001 + Add dq8 delay of 1 delay unit + #001 + + + 010 + Add dq8 delay of 2 delay units. + #010 + + + 011 + Add dq8 delay of 3 delay units. + #011 + + + 100 + Add dq8 delay of 4 delay units. + #100 + + + 101 + Add dq8 delay of 5 delay units. + #101 + + + 110 + Add dq8 delay of 6 delay units. + #110 + + + 111 + Add dq8 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq9_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq9 delay + #000 + + + 001 + Add dq9 delay of 1 delay unit + #001 + + + 010 + Add dq9 delay of 2 delay units. + #010 + + + 011 + Add dq9 delay of 3 delay units. + #011 + + + 100 + Add dq9 delay of 4 delay units. + #100 + + + 101 + Add dq9 delay of 5 delay units. + #101 + + + 110 + Add dq9 delay of 6 delay units. + #110 + + + 111 + Add dq9 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq10_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq10 delay + #000 + + + 001 + Add dq10 delay of 1 delay unit + #001 + + + 010 + Add dq10 delay of 2 delay units. + #010 + + + 011 + Add dq10 delay of 3 delay units. + #011 + + + 100 + Add dq10 delay of 4 delay units. + #100 + + + 101 + Add dq10 delay of 5 delay unit + #101 + + + 110 + Add dq10 delay of 6 delay units. + #110 + + + 111 + Add dq10 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq11_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq11 delay + #000 + + + 001 + Add dq11 delay of 1 delay unit + #001 + + + 010 + Add dq11 delay of 2 delay units. + #010 + + + 011 + Add dq11 delay of 3 delay units. + #011 + + + 100 + Add dq11 delay of 4 delay units. + #100 + + + 101 + Add dq11 delay of 5 delay units. + #101 + + + 110 + Add dq11 delay of 6 delay units. + #110 + + + 111 + Add dq11 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq12_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq12 delay + #000 + + + 001 + Add dq12 delay of 1 delay unit + #001 + + + 010 + Add dq12 delay of 2 delay units. + #010 + + + 011 + Add dq12 delay of 3 delay units. + #011 + + + 100 + Add dq12 delay of 4 delay units. + #100 + + + 101 + Add dq12 delay of 5 delay units. + #101 + + + 110 + Add dq12 delay of 6 delay units. + #110 + + + 111 + Add dq12 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq13_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq13 delay + #000 + + + 001 + Add dq13 delay of 1 delay unit + #001 + + + 010 + Add dq13 delay of 2 delay units. + #010 + + + 011 + Add dq13 delay of 3 delay units. + #011 + + + 100 + Add dq13 delay of 4 delay units. + #100 + + + 101 + Add dq13 delay of 5 delay units. + #101 + + + 110 + Add dq13 delay of 6 delay units. + #110 + + + 111 + Add dq13 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq14_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq14 delay + #000 + + + 001 + Add dq14 delay of 1 delay unit + #001 + + + 010 + Add dq14 delay of 2 delay units. + #010 + + + 011 + Add dq14 delay of 3 delay units. + #011 + + + 100 + Add dq14 delay of 4 delay units. + #100 + + + 101 + Add dq14 delay of 5 delay units. + #101 + + + 110 + Add dq14 delay of 6 delay units. + #110 + + + 111 + Add dq14 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq15_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq15 delay + #000 + + + 001 + Add dq15 delay of 1 delay unit + #001 + + + 010 + Add dq15 delay of 2 delay units. + #010 + + + 011 + Add dq15 delay of 3 delay units. + #011 + + + 100 + Add dq15 delay of 4 delay units. + #100 + + + 101 + Add dq15 delay of 5 delay units. + #101 + + + 110 + Add dq15 delay of 6 delay units. + #110 + + + 111 + Add dq15 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY2DL + MMDC PHY Read DQ Byte2 Delay Register + 0x824 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq16_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq16 delay + #000 + + + 001 + Add dq16 delay of 1 delay unit + #001 + + + 010 + Add dq16 delay of 2 delay units. + #010 + + + 011 + Add dq16 delay of 3 delay units. + #011 + + + 100 + Add dq16 delay of 4 delay units. + #100 + + + 101 + Add dq16 delay of 5 delay units. + #101 + + + 110 + Add dq16 delay of 6 delay units. + #110 + + + 111 + Add dq16 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq17_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq17 delay + #000 + + + 001 + Add dq17 delay of 1 delay unit + #001 + + + 010 + Add dq17 delay of 2 delay units. + #010 + + + 011 + Add dq17 delay of 3 delay units. + #011 + + + 100 + Add dq17 delay of 4 delay units. + #100 + + + 101 + Add dq17 delay of 5 delay units. + #101 + + + 110 + Add dq17 delay of 6 delay units. + #110 + + + 111 + Add dq17 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq18_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq18 delay + #000 + + + 001 + Add dq18 delay of 1 delay unit + #001 + + + 010 + Add dq18 delay of 2 delay units. + #010 + + + 011 + Add dq18 delay of 3 delay units. + #011 + + + 100 + Add dq18 delay of 4 delay units. + #100 + + + 101 + Add dq18 delay of 5 delay units. + #101 + + + 110 + Add dq18 delay of 6 delay units. + #110 + + + 111 + Add dq18 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq19_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq19 delay + #000 + + + 001 + Add dq19 delay of 1 delay unit + #001 + + + 010 + Add dq19 delay of 2 delay units. + #010 + + + 011 + Add dq19 delay of 3 delay units. + #011 + + + 100 + Add dq19 delay of 4 delay units. + #100 + + + 101 + Add dq19 delay of 5 delay units. + #101 + + + 110 + Add dq19 delay of 6 delay units. + #110 + + + 111 + Add dq19 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq20_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq20 delay + #000 + + + 001 + Add dq20 delay of 1 delay unit + #001 + + + 010 + Add dq20 delay of 2 delay units. + #010 + + + 011 + Add dq20 delay of 3 delay units. + #011 + + + 100 + Add dq20 delay of 4 delay units. + #100 + + + 101 + Add dq20 delay of 5 delay units. + #101 + + + 110 + Add dq20 delay of 6 delay units. + #110 + + + 111 + Add dq20 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq21_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq21 delay + #000 + + + 001 + Add dq21 delay of 1 delay unit + #001 + + + 010 + Add dq21 delay of 2 delay units. + #010 + + + 011 + Add dq21 delay of 3 delay units. + #011 + + + 100 + Add dq21 delay of 4 delay units. + #100 + + + 101 + Add dq21 delay of 5 delay units. + #101 + + + 110 + Add dq21 delay of 6 delay units. + #110 + + + 111 + Add dq21 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq22_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq22 delay + #000 + + + 001 + Add dq22 delay of 1 delay unit + #001 + + + 010 + Add dq22 delay of 2 delay units. + #010 + + + 011 + Add dq22 delay of 3 delay units. + #011 + + + 100 + Add dq22 delay of 4 delay units. + #100 + + + 101 + Add dq22 delay of 5 delay units. + #101 + + + 110 + Add dq22 delay of 6 delay units. + #110 + + + 111 + Add dq22 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq23_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq23 delay + #000 + + + 001 + Add dq23 delay of 1 delay unit + #001 + + + 010 + Add dq23 delay of 2 delay units. + #010 + + + 011 + Add dq23 delay of 3 delay units. + #011 + + + 100 + Add dq23 delay of 4 delay units. + #100 + + + 101 + Add dq23 delay of 5 delay units. + #101 + + + 110 + Add dq23 delay of 6 delay units. + #110 + + + 111 + Add dq23 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY3DL + MMDC PHY Read DQ Byte3 Delay Register + 0x828 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq24_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq24 delay + #000 + + + 001 + Add dq24 delay of 1 delay unit + #001 + + + 010 + Add dq24 delay of 2 delay units. + #010 + + + 011 + Add dq24 delay of 3 delay units. + #011 + + + 100 + Add dq24 delay of 4 delay units. + #100 + + + 101 + Add dq24 delay of 5 delay units. + #101 + + + 110 + Add dq24 delay of 6 delay units. + #110 + + + 111 + Add dq24 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq25_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq25 delay + #000 + + + 001 + Add dq25 delay of 1 delay unit + #001 + + + 010 + Add dq25 delay of 2 delay units. + #010 + + + 011 + Add dq25 delay of 3 delay units. + #011 + + + 100 + Add dq25 delay of 4 delay units. + #100 + + + 101 + Add dq25 delay of 5 delay units. + #101 + + + 110 + Add dq25 delay of 6 delay units. + #110 + + + 111 + Add dq25 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq26_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq26 delay + #000 + + + 001 + Add dq26 delay of 1 delay unit + #001 + + + 010 + Add dq26 delay of 2 delay units. + #010 + + + 011 + Add dq26 delay of 3 delay units. + #011 + + + 100 + Add dq26 delay of 4 delay units. + #100 + + + 101 + Add dq26 delay of 5 delay units. + #101 + + + 110 + Add dq26 delay of 6 delay units. + #110 + + + 111 + Add dq26 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq27_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq27 delay + #000 + + + 001 + Add dq27 delay of 1 delay unit + #001 + + + 010 + Add dq27 delay of 2 delay units. + #010 + + + 011 + Add dq27 delay of 3 delay units. + #011 + + + 100 + Add dq27 delay of 4 delay units. + #100 + + + 101 + Add dq27 delay of 5 delay units. + #101 + + + 110 + Add dq27 delay of 6 delay units. + #110 + + + 111 + Add dq27 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq28_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq28 delay + #000 + + + 001 + Add dq28 delay of 1 delay unit + #001 + + + 010 + Add dq28 delay of 2 delay units. + #010 + + + 011 + Add dq28 delay of 3 delay units. + #011 + + + 100 + Add dq28 delay of 4 delay units. + #100 + + + 101 + Add dq28 delay of 5 delay units. + #101 + + + 110 + Add dq28 delay of 6 delay units. + #110 + + + 111 + Add dq28 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq29_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq29 delay + #000 + + + 001 + Add dq29 delay of 1 delay unit + #001 + + + 010 + Add dq29 delay of 2 delay units. + #010 + + + 011 + Add dq29 delay of 3 delay units. + #011 + + + 100 + Add dq29 delay of 4 delay units. + #100 + + + 101 + Add dq29 delay of 5 delay units. + #101 + + + 110 + Add dq29 delay of 6 delay units. + #110 + + + 111 + Add dq29 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq30_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq30 delay + #000 + + + 001 + Add dq30 delay of 1 delay unit + #001 + + + 010 + Add dq30 delay of 2 delay units. + #010 + + + 011 + Add dq30 delay of 3 delay units. + #011 + + + 100 + Add dq30 delay of 4 delay units. + #100 + + + 101 + Add dq30 delay of 5 delay units. + #101 + + + 110 + Add dq30 delay of 6 delay units. + #110 + + + 111 + Add dq30 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq31_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq31 delay + #000 + + + 001 + Add dq31 delay of 1 delay unit + #001 + + + 010 + Add dq31 delay of 2 delay units. + #010 + + + 011 + Add dq31 delay of 3 delay units. + #011 + + + 100 + Add dq31 delay of 4 delay units. + #100 + + + 101 + Add dq31 delay of 5 delay units. + #101 + + + 110 + Add dq31 delay of 6 delay units. + #110 + + + 111 + Add dq31 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDQBY0DL + MMDC PHY Write DQ Byte0 Delay Register + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq0_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq0 delay + #00 + + + 01 + Add dq0 delay of 1 delay unit. + #01 + + + 10 + Add dq0 delay of 2 delay units. + #10 + + + 11 + Add dq0 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq1_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq1 delay + #00 + + + 01 + Add dq1 delay of 1 delay unit. + #01 + + + 10 + Add dq1 delay of 2 delay units. + #10 + + + 11 + Add dq1 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq2_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq2 delay + #00 + + + 01 + Add dq2 delay of 1 delay unit. + #01 + + + 10 + Add dq2 delay of 2 delay units. + #10 + + + 11 + Add dq2 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq3_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq3 delay + #00 + + + 01 + Add dq3 delay of 1 delay unit. + #01 + + + 10 + Add dq3 delay of 2 delay units. + #10 + + + 11 + Add dq3 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq4_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq4 delay + #00 + + + 01 + Add dq4 delay of 1 delay unit.. + #01 + + + 10 + Add dq4 delay of 2 delay units. + #10 + + + 11 + Add dq4 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq5_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq5 delay + #00 + + + 01 + Add dq5 delay of 1 delay unit. + #01 + + + 10 + Add dq5 delay of 2 delay units. + #10 + + + 11 + Add dq5 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq6_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq6 delay + #00 + + + 01 + Add dq6 delay of 1 delay unit. + #01 + + + 10 + Add dq6 delay of 2 delay units. + #10 + + + 11 + Add dq6 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq7_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq7 delay + #00 + + + 01 + Add dq7 delay of 1 delay unit. + #01 + + + 10 + Add dq7 delay of 2 delay units. + #10 + + + 11 + Add dq7 delay of 3 delay units. + #11 + + + + + wr_dm0_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm0 delay + #00 + + + 01 + Add dm0 delay of 1 delay unit. + #01 + + + 10 + Add dm0 delay of 2 delay units. + #10 + + + 11 + Add dm0 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY1DL + MMDC PHY Write DQ Byte1 Delay Register + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq8_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq8 delay + #00 + + + 01 + Add dq8 delay of 1 delay unit. + #01 + + + 10 + Add dq8 delay of 2 delay units. + #10 + + + 11 + Add dq8 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq9_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq9 delay + #00 + + + 01 + Add dq9 delay of 1 delay unit. + #01 + + + 10 + Add dq9 delay of 2 delay units. + #10 + + + 11 + Add dq9 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq10_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq10 delay + #00 + + + 01 + Add dq10 delay of 1 delay unit. + #01 + + + 10 + Add dq10 delay of 2 delay units. + #10 + + + 11 + Add dq10 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq11_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq11 delay + #00 + + + 01 + Add dq11 delay of 1 delay unit. + #01 + + + 10 + Add dq11 delay of 2 delay units. + #10 + + + 11 + Add dq11 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq12_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq12 delay + #00 + + + 01 + Add dq12 delay of 1 delay unit. + #01 + + + 10 + Add dq12 delay of 2 delay units. + #10 + + + 11 + Add dq12 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq13_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq13 delay + #00 + + + 01 + Add dq13 delay of 1 delay unit. + #01 + + + 10 + Add dq13 delay of 2 delay units. + #10 + + + 11 + Add dq13 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq14_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq14 delay + #00 + + + 01 + Add dq14 delay of 1 delay unit. + #01 + + + 10 + Add dq14 delay of 2 delay units. + #10 + + + 11 + Add dq14 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq15_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq15 delay + #00 + + + 01 + Add dq15 delay of 1 delay unit. + #01 + + + 10 + Add dq15 delay of 2 delay units. + #10 + + + 11 + Add dq15 delay of 3 delay units. + #11 + + + + + wr_dm1_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm1 delay + #00 + + + 01 + Add dm1 delay of 1 delay unit. + #01 + + + 10 + Add dm1 delay of 2 delay units. + #10 + + + 11 + Add dm1 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY2DL + MMDC PHY Write DQ Byte2 Delay Register + 0x834 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq16_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq16 delay + #00 + + + 01 + Add dq16 delay of 1 delay unit. + #01 + + + 10 + Add dq16 delay of 2 delay units. + #10 + + + 11 + Add dq16 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq17_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq17 delay + #00 + + + 01 + Add dq17 delay of 1 delay unit. + #01 + + + 10 + Add dq17 delay of 2 delay units. + #10 + + + 11 + Add dq17 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq18_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq18 delay + #00 + + + 01 + Add dq18 delay of 1 delay unit. + #01 + + + 10 + Add dq18 delay of 2 delay units. + #10 + + + 11 + Add dq18 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq19_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq19 delay + #00 + + + 01 + Add dq19 delay of 1 delay unit. + #01 + + + 10 + Add dq19 delay of 2 delay units. + #10 + + + 11 + Add dq19 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq20_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq20 delay + #00 + + + 01 + Add dq20 delay of 1 delay unit. + #01 + + + 10 + Add dq20 delay of 2 delay units. + #10 + + + 11 + Add dq20 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq21_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq21 delay + #00 + + + 01 + Add dq21 delay of 1 delay unit. + #01 + + + 10 + Add dq21 delay of 2 delay units. + #10 + + + 11 + Add dq21 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq22_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq22 delay + #00 + + + 01 + Add dq22 delay of 1 delay unit. + #01 + + + 10 + Add dq22 delay of 2 delay units. + #10 + + + 11 + Add dq22 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq23_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq23 delay + #00 + + + 01 + Add dq23 delay of 1 delay unit. + #01 + + + 10 + Add dq23 delay of 2 delay units. + #10 + + + 11 + Add dq23 delay of 3 delay units. + #11 + + + + + wr_dm2_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm2 delay + #00 + + + 01 + Add dm2 delay of 1 delay unit. + #01 + + + 10 + Add dm2 delay of 2 delay units. + #10 + + + 11 + Add dm2 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY3DL + MMDC PHY Write DQ Byte3 Delay Register + 0x838 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq24_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq24 delay + #00 + + + 01 + Add dq24 delay of 1 delay unit. + #01 + + + 10 + Add dq24 delay of 2 delay units. + #10 + + + 11 + Add dq24 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq25_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq25 delay + #00 + + + 01 + Add dq25 delay of 1 delay unit. + #01 + + + 10 + Add dq25 delay of 2 delay units. + #10 + + + 11 + Add dq25 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq26_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq26 delay + #00 + + + 01 + Add dq26 delay of 1 delay unit. + #01 + + + 10 + Add dq26 delay of 2 delay units. + #10 + + + 11 + Add dq26 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq27_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq27 delay + #00 + + + 01 + Add dq27 delay of 1 delay unit. + #01 + + + 10 + Add dq27 delay of 2 delay units. + #10 + + + 11 + Add dq27 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq28_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq28 delay + #00 + + + 01 + Add dq28 delay of 1 delay unit. + #01 + + + 10 + Add dq28 delay of 2 delay units. + #10 + + + 11 + Add dq28 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq29_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq29 delay + #00 + + + 01 + Add dq29 delay of 1 delay unit. + #01 + + + 10 + Add dq29 delay of 2 delay units. + #10 + + + 11 + Add dq29 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq30_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq30 delay + #00 + + + 01 + Add dq30 delay of 1 delay unit. + #01 + + + 10 + Add dq30 delay of 2 delay units. + #10 + + + 11 + Add dq30 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq31_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq31 delay + #00 + + + 01 + Add dq31 delay of 1 delay unit. + #01 + + + 10 + Add dq31 delay of 2 delay units. + #10 + + + 11 + Add dq31 delay of 3 delay units. + #11 + + + + + wr_dm3_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm3 delay + #00 + + + 01 + Add dm3 delay of 1 delay unit. + #01 + + + 10 + Add dm3 delay of 2 delay units. + #10 + + + 11 + Add dm3 delay of 3 delay units. + #11 + + + + + + + MPDGCTRL0 + MMDC PHY Read DQS Gating Control Register 0 + 0x83C + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_HC_DEL0 + no description available + 8 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + HW_DG_ERR + no description available + 12 + 1 + read-only + + + 0 + No error was found during the DQS gating HW calibration process. + #0 + + + 1 + An error was found during the DQS gating HW calibration process. + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + DG_DL_ABS_OFFSET1 + no description available + 16 + 7 + read-write + + + DG_EXT_UP + no description available + 23 + 1 + read-write + + + DG_HC_DEL1 + no description available + 24 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + HW_DG_EN + no description available + 28 + 1 + read-write + + + 0 + Disable automatic read DQS gating calibration + #0 + + + 1 + Start automatic read DQS gating calibration + #1 + + + + + DG_DIS + no description available + 29 + 1 + read-write + + + 0 + Read DQS gating mechanism is enbled + #0 + + + 1 + Read DQS gating mechanism is disabled + #1 + + + + + DG_CMP_CYC + no description available + 30 + 1 + read-write + + + 0 + MMDC waits 16 DDR cycles + #0 + + + 1 + MMDC waits 32 DDR cycles + #1 + + + + + RST_RD_FIFO + no description available + 31 + 1 + read-write + + + + + MPDGCTRL1 + MMDC PHY Read DQS Gating Control Register 1 + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET2 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_HC_DEL2 + no description available + 8 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + DG_DL_ABS_OFFSET3 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + DG_HC_DEL3 + no description available + 24 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + MPDGDLST0 + MMDC PHY Read DQS Gating delay-line Status Register + 0x844 + 32 + read-only + 0 + 0xFFFFFFFF + + + DG_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + DG_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + DG_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLCTL + MMDC PHY Read delay-lines Configuration Register + 0x848 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + RD_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RD_DL_ABS_OFFSET1 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + RD_DL_ABS_OFFSET2 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + RD_DL_ABS_OFFSET3 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLST + MMDC PHY Read delay-lines Status Register + 0x84C + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + RD_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + RD_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RD_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLCTL + MMDC PHY Write delay-lines Configuration Register + 0x850 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + WR_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WR_DL_ABS_OFFSET1 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + WR_DL_ABS_OFFSET2 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WR_DL_ABS_OFFSET3 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLST + MMDC PHY Write delay-lines Status Register + 0x854 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + WR_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + WR_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + WR_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPSDCTRL + MMDC PHY CK Control Register + 0x858 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + SDclk0_del + no description available + 8 + 2 + read-write + + + 00 + No change in DDR clock0 delay + #00 + + + 01 + Add DDR clock0 delay of 1 delay unit. + #01 + + + 10 + Add DDR clock0 delay of 2 delay units. + #10 + + + 11 + Add DDR clock0 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + MPZQLP2CTL + MMDC ZQ LPDDR2 HW Control Register + 0x85C + 32 + read-write + 0x1B5F0109 + 0xFFFFFFFF + + + ZQ_LP2_HW_ZQINIT + no description available + 0 + 9 + read-write + + + 110111 + 112 cycles + #110111 + + + 111000 + 114 cycles + #111000 + + + 100001001 + 532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz) + #100001001 + + + 111111110 + 1022 cycles + #111111110 + + + 111111111 + 1024 cycles + #111111111 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + ZQ_LP2_HW_ZQCL + no description available + 16 + 8 + read-write + + + 110111 + 112 cycles + #110111 + + + 111000 + 114 cycles + #111000 + + + 1011111 + 192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz) + #1011111 + + + 11111110 + 510 cycles + #11111110 + + + 11111111 + 512 cycles + #11111111 + + + + + ZQ_LP2_HW_ZQCS + no description available + 24 + 7 + read-write + + + 11011 + 112 cycles (default) + #11011 + + + 11100 + 116 cycles + #11100 + + + 1111110 + 508 cycles + #1111110 + + + 1111111 + 512 cycles + #1111111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLHWCTL + MMDC PHY Read Delay HW Calibration Control Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_RD_DL_ERR0 + no description available + 0 + 1 + read-only + + + 0 + No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + #0 + + + 1 + An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + #1 + + + + + HW_RD_DL_ERR1 + no description available + 1 + 1 + read-only + + + 0 + No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + #0 + + + 1 + An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + #1 + + + + + HW_RD_DL_ERR2 + no description available + 2 + 1 + read-only + + + 0 + No error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. + #0 + + + 1 + An error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. + #1 + + + + + HW_RD_DL_ERR3 + no description available + 3 + 1 + read-only + + + 0 + No error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. + #0 + + + 1 + An error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. + #1 + + + + + HW_RD_DL_EN + no description available + 4 + 1 + read-write + + + HW_RD_DL_CMP_CYC + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPWRDLHWCTL + MMDC PHY Write Delay HW Calibration Control Register + 0x864 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WR_DL_ERR0 + no description available + 0 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 0. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 0. + #1 + + + + + HW_WR_DL_ERR1 + no description available + 1 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 1. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 1. + #1 + + + + + HW_WR_DL_ERR2 + no description available + 2 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 2. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 2. + #1 + + + + + HW_WR_DL_ERR3 + no description available + 3 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 3. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 3. + #1 + + + + + HW_WR_DL_EN + no description available + 4 + 1 + read-write + + + HW_WR_DL_CMP_CYC + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPRDDLHWST0 + MMDC PHY Read Delay HW Calibration Status Register 0 + 0x868 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_RD_DL_UP0 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_RD_DL_LOW1 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_RD_DL_UP1 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLHWST1 + MMDC PHY Read Delay HW Calibration Status Register 1 + 0x86C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW2 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_RD_DL_UP2 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_RD_DL_LOW3 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_RD_DL_UP3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLHWST0 + MMDC PHY Write Delay HW Calibration Status Register 0 + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_WR_DL_UP0 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_WR_DL_LOW1 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_WR_DL_UP1 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLHWST1 + MMDC PHY Write Delay HW Calibration Status Register 1 + 0x874 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW2 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_WR_DL_UP2 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_WR_DL_LOW3 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_WR_DL_UP3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWLHWERR + MMDC PHY Write Leveling HW Error Register + 0x878 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WL0_DQ + no description available + 0 + 8 + read-only + + + HW_WL1_DQ + no description available + 8 + 8 + read-only + + + HW_WL2_DQ + no description available + 16 + 8 + read-only + + + HW_WL3_DQ + no description available + 24 + 8 + read-only + + + + + MPDGHWST0 + MMDC PHY Read DQS Gating HW Status Register 0 + 0x87C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW0 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP0 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST1 + MMDC PHY Read DQS Gating HW Status Register 1 + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW1 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP1 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST2 + MMDC PHY Read DQS Gating HW Status Register 2 + 0x884 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW2 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP2 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST3 + MMDC PHY Read DQS Gating HW Status Register 3 + 0x888 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW3 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP3 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPPDCMPR1 + MMDC PHY Pre-defined Compare Register 1 + 0x88C + 32 + read-write + 0 + 0xFFFFFFFF + + + PDV1 + no description available + 0 + 16 + read-write + + + PDV2 + no description available + 16 + 16 + read-write + + + + + MPPDCMPR2 + MMDC PHY Pre-defined Compare and CA delay-line Configuration Register + 0x890 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + MPR_CMP + no description available + 0 + 1 + read-write + + + MPR_FULL_CMP + no description available + 1 + 1 + read-write + + + READ_LEVEL_PATTERN + no description available + 2 + 1 + read-write + + + 0 + Compare with read pattern 1010 + #0 + + + 1 + Compare with read pattern 0011 (Used only in LPDDR2 mode) + #1 + + + + + RESERVED + no description available + 3 + 13 + read-only + + + CA_DL_ABS_OFFSET + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + PHY_CA_DL_UNIT + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPSWDAR0 + MMDC PHY SW Dummy Access Register + 0x894 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_DUMMY_WR + no description available + 0 + 1 + read-write + + + SW_DUMMY_RD + no description available + 1 + 1 + read-write + + + SW_DUM_CMP0 + no description available + 2 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP1 + no description available + 3 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP2 + no description available + 4 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP3 + no description available + 5 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPSWDRDR0 + MMDC PHY SW Dummy Read Data Register 0 + 0x898 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD0 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR1 + MMDC PHY SW Dummy Read Data Register 1 + 0x89C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD1 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR2 + MMDC PHY SW Dummy Read Data Register 2 + 0x8A0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD2 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR3 + MMDC PHY SW Dummy Read Data Register 3 + 0x8A4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD3 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR4 + MMDC PHY SW Dummy Read Data Register 4 + 0x8A8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD4 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR5 + MMDC PHY SW Dummy Read Data Register 5 + 0x8AC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD5 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR6 + MMDC PHY SW Dummy Read Data Register 6 + 0x8B0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD6 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR7 + MMDC PHY SW Dummy Read Data Register 7 + 0x8B4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD7 + no description available + 0 + 32 + read-only + + + + + MPMUR0 + MMDC PHY Measure Unit Register + 0x8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MU_BYP_VAL + no description available + 0 + 10 + read-write + + + MU_BYP_EN + no description available + 10 + 1 + read-write + + + 0 + The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM. + #0 + + + 1 + The delay-lines use delay units as indicated at MU_BYPASS_VAL. + #1 + + + + + FRC_MSR + no description available + 11 + 1 + read-write + + + 0 + No measurement is performed + #0 + + + 1 + Perform measurement process + #1 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + MU_UNIT_DEL_NUM + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + MPWRCADL + MMDC Write CA delay-line controller + 0x8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + WR_CA0_DEL + no description available + 0 + 2 + read-write + + + 00 + No change in CA0 delay + #00 + + + 01 + Add CA0 delay of 1 delay unit + #01 + + + 10 + Add CA0 delay of 2 delay units. + #10 + + + 11 + Add CA0 delay of 3 delay units. + #11 + + + + + WR_CA1_DEL + no description available + 2 + 2 + read-write + + + 00 + No change in CA1 delay + #00 + + + 01 + Add CA1 delay of 1 delay unit + #01 + + + 10 + Add CA1 delay of 2 delay units. + #10 + + + 11 + Add CA1 delay of 3 delay units. + #11 + + + + + WR_CA2_DEL + no description available + 4 + 2 + read-write + + + 00 + No change in CA2 delay + #00 + + + 01 + Add CA2 delay of 1 delay unit + #01 + + + 10 + Add CA2 delay of 2 delay units. + #10 + + + 11 + Add CA2 delay of 3 delay units. + #11 + + + + + WR_CA3_DEL + no description available + 6 + 2 + read-write + + + 00 + No change in CA3 delay + #00 + + + 01 + Add CA3 delay of 1 delay unit + #01 + + + 10 + Add CA3 delay of 2 delay units. + #10 + + + 11 + Add CA3 delay of 3 delay units. + #11 + + + + + WR_CA4_DEL + no description available + 8 + 2 + read-write + + + 00 + No change in CA4 delay + #00 + + + 01 + Add CA4 delay of 1 delay unit + #01 + + + 10 + Add CA4 delay of 2 delay units. + #10 + + + 11 + Add CA4 delay of 3 delay units. + #11 + + + + + WR_CA5_DEL + no description available + 10 + 2 + read-write + + + 00 + No change in CA5 delay + #00 + + + 01 + Add CA5 delay of 1 delay unit + #01 + + + 10 + Add CA5 delay of 2 delay units. + #10 + + + 11 + Add CA5 delay of 3 delay units. + #11 + + + + + WR_CA6_DEL + no description available + 12 + 2 + read-write + + + 00 + No change in CA6 delay + #00 + + + 01 + Add CA6 delay of 1 delay unit + #01 + + + 10 + Add CA6 delay of 2 delay units. + #10 + + + 11 + Add CA6 delay of 3 delay units. + #11 + + + + + WR_CA7_DEL + no description available + 14 + 2 + read-write + + + 00 + No change in CA7 delay + #00 + + + 01 + Add CA7 delay of 1 delay unit + #01 + + + 10 + Add CA7 delay of 2 delay units. + #10 + + + 11 + Add CA7 delay of 3 delay units. + #11 + + + + + WR_CA8_DEL + no description available + 16 + 2 + read-write + + + 00 + No change in CA8 delay + #00 + + + 01 + Add CA8 delay of 1 delay unit + #01 + + + 10 + Add CA8 delay of 2 delay units. + #10 + + + 11 + Add CA8 delay of 3 delay units. + #11 + + + + + WR_CA9_DEL + no description available + 18 + 2 + read-write + + + 00 + No change in CA9 delay + #00 + + + 01 + Add CA9 delay of 1 delay unit + #01 + + + 10 + Add CA9 delay of 2 delay units. + #10 + + + 11 + Add CA9 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + MPDCCR + MMDC Duty Cycle Control Register + 0x8C0 + 32 + read-only + 0x24922492 + 0xFFFFFFFF + + + WR_DQS0_FT_DCC + no description available + 0 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS1_FT_DCC + no description available + 3 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS2_FT_DCC + no description available + 6 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS3_FT_DCC + no description available + 9 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + CK_FT0_DCC + no description available + 12 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CK_FT1_DCC + no description available + 16 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS0_FT_DCC + no description available + 19 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS1_FT_DCC + no description available + 22 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS2_FT_DCC + no description available + 25 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS3_FT_DCC + no description available + 28 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + + + MMDC2 + MMDC + MMDC + MMDC2_ + 0x21B4000 + + 0 + 0x8C4 + registers + + + + MDCTL + MMDC Core Control Register + 0 + 32 + read-write + 0x3110000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + DSIZ + no description available + 16 + 2 + read-write + + + 0 + 16-bit data bus + #0 + + + 1 + 32-bit data bus + #1 + + + + + RESERVED + no description available + 18 + 1 + read-only + + + BL + no description available + 19 + 1 + read-write + + + 0 + Burst Length 4 is used + #0 + + + 1 + Burst Length 8 is used + #1 + + + + + COL + no description available + 20 + 3 + read-write + + + 0 + 9 bits column + #0 + + + 1 + 10 bits column + #1 + + + 10 + 11 bits column + #10 + + + 11 + 8 bits column + #11 + + + 100 + 12 bits column + #100 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + ROW + no description available + 24 + 3 + read-write + + + 000 + 11 bits Row + #000 + + + 001 + 12 bits Row + #001 + + + 010 + 13 bits Row + #010 + + + 011 + 14 bits Row + #011 + + + 100 + 15 bits Row + #100 + + + 101 + 16 bits Row + #101 + + + + + RESERVED + no description available + 27 + 3 + read-only + + + SDE_1 + no description available + 30 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + SDE_0 + no description available + 31 + 1 + read-write + + + 0 + Disabled + #0 + + + 1 + Enabled + #1 + + + + + + + MDPDC + MMDC Core Power Down Control Register + 0x4 + 32 + read-write + 0x30012 + 0xFFFFFFFF + + + tCKSRE + no description available + 0 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycles + #1 + + + 110 + 6cycles + #110 + + + 111 + 7cycles + #111 + + + + + tCKSRX + no description available + 3 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycles + #1 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + BOTH_CS_PD + no description available + 6 + 1 + read-write + + + 0 + Each chip select can enter power down independently according to its configuration. + #0 + + + 1 + Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained. + #1 + + + + + SLOW_PD + no description available + 7 + 1 + read-write + + + 0 + Fast mode. + #0 + + + 1 + Slow mode. + #1 + + + + + PWDT_0 + no description available + 8 + 4 + read-write + + + PWDT_1 + no description available + 12 + 4 + read-write + + + tCKE + no description available + 16 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 19 + 5 + read-only + + + PRCT_0 + no description available + 24 + 3 + read-write + + + RESERVED + no description available + 27 + 1 + read-only + + + PRCT_1 + no description available + 28 + 3 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MDOTC + MMDC Core ODT Timing Control Register + 0x8 + 32 + read-write + 0x12272000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + tODT_idle_off + no description available + 4 + 5 + read-write + + + 0 + 0 cycle (turned off at the earliest possible time) + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11110 + 30 cycles + #11110 + + + 11111 + 31 cycles + #11111 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + tODTLon + no description available + 12 + 3 + read-write + + + 0 + - 0x1 Reserved + #0 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + tAXPD + no description available + 16 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tANPD + no description available + 20 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tAONPD + no description available + 24 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tAOFPD + no description available + 27 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + MDCFG0 + MMDC Core Timing Configuration Register 0 + 0xC + 32 + read-write + 0x323622D3 + 0xFFFFFFFF + + + tCL + no description available + 0 + 4 + read-write + + + 0 + 3 cycles + #0 + + + 1 + 4 cycles + #1 + + + 10 + 5 cycles + #10 + + + 11 + 6 cycles + #11 + + + 100 + 7 cycles + #100 + + + 101 + 8 cycles + #101 + + + 110 + 9 cycles + #110 + + + 111 + 10 cycles + #111 + + + 1000 + 11 cycles + #1000 + + + 1001 + - 0xF Reserved + #1001 + + + + + tFAW + no description available + 4 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + 32 clocks + #11111 + + + + + tXPDLL + no description available + 9 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tXP + no description available + 13 + 3 + read-write + + + 0 + 1 cycle + #0 + + + 1 + 2 cycles + #1 + + + 110 + 7 cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tXS + no description available + 16 + 8 + read-write + + + 0 + - 0x15 reserved + #0 + + + 10110 + 23 clocks + #10110 + + + 10111 + 24 clocks + #10111 + + + 11111110 + 255 clocks + #11111110 + + + 11111111 + 256 clocks + #11111111 + + + + + tRFC + no description available + 24 + 8 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11111110 + 255 clocks + #11111110 + + + 11111111 + 256 clocks + #11111111 + + + + + + + MDCFG1 + MMDC Core Timing Configuration Register 1 + 0x10 + 32 + read-write + 0xB6B18A23 + 0xFFFFFFFF + + + tCWL + no description available + 0 + 3 + read-write + + + 0 + 2cycles ( DDR2/ DDR3) , 1 cycle (LPDDR2) + #0 + + + 1 + 3cycles ( DDR2/ DDR3) , 2 cycles (LPDDR2) + #1 + + + 10 + 4cycles ( DDR2/ DDR3) , 3 cycles (LPDDR2) + #10 + + + 11 + 5cycles ( DDR2/ DDR3) , 4 cycles (LPDDR2) + #11 + + + 100 + 6cycles ( DDR2/ DDR3) , 5 cycles (LPDDR2) + #100 + + + 101 + 7cycles ( DDR2/ DDR3) , 6 cycles (LPDDR2) + #101 + + + 110 + 8cycles ( DDR2/ DDR3) , 7 cycles (LPDDR2) + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 3 + 2 + read-only + + + tMRD + no description available + 5 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + 16 clocks + #1111 + + + + + tWR + no description available + 9 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 12 + 3 + read-only + + + tRPA + no description available + 15 + 1 + read-write + + + 0 + Will be equal to: tRP. + #0 + + + 1 + Will be equal to: tRP+1. + #1 + + + + + tRAS + no description available + 16 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + Reserved + #11111 + + + + + tRC + no description available + 21 + 5 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11110 + 31 clocks + #11110 + + + 11111 + 32 clocks + #11111 + + + + + tRP + no description available + 26 + 3 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11 + 4 clocks + #11 + + + 100 + 5 clocks + #100 + + + 101 + 6 clocks + #101 + + + 110 + 7 clocks + #110 + + + 111 + 8 clocks + #111 + + + + + tRCD + no description available + 29 + 3 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 11 + 4 clocks + #11 + + + 100 + 5 clocks + #100 + + + 101 + 6 clocks + #101 + + + 110 + 7 clocks + #110 + + + 111 + 8 clocks + #111 + + + + + + + MDCFG2 + MMDC Core Timing Configuration Register 2 + 0x14 + 32 + read-write + 0xC70092 + 0xFFFFFFFF + + + tRRD + no description available + 0 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + Reserved + #111 + + + + + tWTR + no description available + 3 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + tRTP + no description available + 6 + 3 + read-write + + + 0 + 1cycle + #0 + + + 1 + 2cycles + #1 + + + 10 + 3cycles + #10 + + + 11 + 4cycles + #11 + + + 100 + 5cycles + #100 + + + 101 + 6cycles + #101 + + + 110 + 7cycles + #110 + + + 111 + 8 cycles + #111 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + tDLLK + no description available + 16 + 9 + read-write + + + 0 + 1 cycle. + #0 + + + 1 + 2 cycles. + #1 + + + 10 + 3 cycles. + #10 + + + 11000111 + 200 cycles (JEDEC value for DDR2). + #11000111 + + + 111111110 + 511 cycles. + #111111110 + + + 111111111 + 512 cycles (JEDEC value for DDR3). + #111111111 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + MDMISC + MMDC Core Miscellaneous Register + 0x18 + 32 + read-write + 0x1600 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + RST + no description available + 1 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Assert reset to the MMDC. + #1 + + + + + LPDDR2_2CH + no description available + 2 + 1 + read-write + + + 0 + 1-channel mode (DDR3) + #0 + + + 1 + 2-channels mode (LPDDR2) + #1 + + + + + DDR_TYPE + no description available + 3 + 2 + read-write + + + 0 + DDR3 device is used. (Default) + #0 + + + 1 + LPDDR2 device is used. + #1 + + + 10 + DDR2 device is used. + #10 + + + 11 + Reserved. + #11 + + + 10 + Reserved. + #10 + + + 11 + Reserved. + #11 + + + + + DDR_4_BANK + no description available + 5 + 1 + read-write + + + 0 + 8 banks device is being used. (Default) + #0 + + + 1 + 4 banks device is being used + #1 + + + + + RALAT + no description available + 6 + 3 + read-write + + + 0 + no additional latency. + #0 + + + 1 + 1 cycle additional latency. + #1 + + + 10 + 2 cycles additional latency. + #10 + + + 11 + 3 cycles additional latency. + #11 + + + 100 + 4 cycles additional latency. + #100 + + + 101 + 5 cycles additional latency. + #101 + + + 110 + 6 cycles additional latency. + #110 + + + 111 + 7 cycles additional latency. + #111 + + + + + MIF3_MODE + no description available + 9 + 2 + read-write + + + 00 + Disable prediction. + #00 + + + 01 + Enable prediction based on : Valid access on first pipe line stage. + #01 + + + 10 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus. + #10 + + + 11 + Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue. + #11 + + + + + LPDDR2_S2 + no description available + 11 + 1 + read-write + + + 0 + LPDDR2-S4 device is used. + #0 + + + 1 + LPDDR2-S2 device is used. + #1 + + + + + BI_ON + no description available + 12 + 1 + read-write + + + 0 + Banks are not interleaved, and address will be decoded as bank-row-column + #0 + + + 1 + Banks are interleaved, and address will be decoded as row-bank-column + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + WALAT + no description available + 16 + 2 + read-write + + + 0 + No additional latency required. + #0 + + + 1 + 1 cycle additional delay + #1 + + + 10 + 2 cycles additional delay + #10 + + + 11 + 3 cycles additional delay + #11 + + + + + LHD + no description available + 18 + 1 + read-write + + + 0 + Latency hiding on. + #0 + + + 1 + Latency hiding disable. + #1 + + + + + ADDR_MIRROR + no description available + 19 + 1 + read-write + + + 0 + Address mirroring disabled. + #0 + + + 1 + Address mirroring enabled. + #1 + + + + + CALIB_PER_CS + no description available + 20 + 1 + read-write + + + 0 + Calibration is targetted to CS0 + #0 + + + 1 + Calibration is targetted to CS1 + #1 + + + + + RESERVED + no description available + 21 + 9 + read-only + + + CS1_RDY + no description available + 30 + 1 + read-only + + + 0 + Device in wake-up period. + #0 + + + 1 + Device is ready for initialization. + #1 + + + + + CS0_RDY + no description available + 31 + 1 + read-only + + + 0 + Device in wake-up period. + #0 + + + 1 + Device is ready for initialization. + #1 + + + + + + + MDSCR + MMDC Core Special Command Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD_BA + no description available + 0 + 3 + read-write + + + 0 + bank address 0 + #0 + + + 1 + bank address 1 + #1 + + + 10 + bank address 2 + #10 + + + 111 + bank address 7 + #111 + + + + + CMD_CS + no description available + 3 + 1 + read-write + + + 0 + to Chip-select 0 + #0 + + + 1 + to Chip-select 1 + #1 + + + + + CMD + no description available + 4 + 3 + read-write + + + 0 + Normal operation + #0 + + + 1 + Precharge all, command is sent independently of bank status (set correct CMD_CS). Will be issued even if banks are closed. Mainly used for init sequence purpose. + #1 + + + 10 + Auto-Refresh Command (set correct CMD_CS). + #10 + + + 11 + Load Mode Register Command ( DDR2/ DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2, set correct CMD_CS, MR_OP, MR_ADDR) + #11 + + + 100 + ZQ calibration ( DDR2/ DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 ) + #100 + + + 101 + Precharge all, only if banks open (set correct CMD_CS). + #101 + + + 110 + MRR command (LPDDR2, set correct CMD_CS, MR_ADDR) + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 7 + 2 + read-only + + + WL_EN + no description available + 9 + 1 + read-write + + + 0 + Exit write leveling mode or stay in normal mode. + #0 + + + 1 + Write leveling entry command was sent. + #1 + + + + + MRR_READ_DATA_VALID + no description available + 10 + 1 + read-only + + + 0 + Cleared upon the assertion of MRR command + #0 + + + 1 + Set after MRR data is valid and stored at MDMRR register. + #1 + + + + + RESERVED + no description available + 11 + 3 + read-only + + + CON_ACK + no description available + 14 + 1 + read-only + + + 0 + Configuration of MMDC registers is forbidden. + #0 + + + 1 + Configuration of MMDC registers is permitted. + #1 + + + + + CON_REQ + no description available + 15 + 1 + read-write + + + 0 + No request to configure MMDC. + #0 + + + 1 + A request to configure MMDC is valid + #1 + + + + + CMD_ADDR_LSB_MR_ADDR + no description available + 16 + 8 + read-write + + + CMD_ADDR_MSB_MR_OP + no description available + 24 + 8 + read-write + + + + + MDREF + MMDC Core Refresh Control Register + 0x20 + 32 + read-write + 0xC000 + 0xFFFFFFFF + + + START_REF + no description available + 0 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Start a refresh cycle. + #1 + + + + + RESERVED + no description available + 1 + 10 + read-only + + + REFR + no description available + 11 + 3 + read-write + + + 0 + 1 refresh + #0 + + + 1 + 2 refreshes + #1 + + + 10 + 3 refreshes + #10 + + + 11 + 4 refreshes + #11 + + + 100 + 5 refreshes + #100 + + + 101 + 6 refreshes + #101 + + + 110 + 7 refreshes + #110 + + + 111 + 8 refreshes + #111 + + + + + REF_SEL + no description available + 14 + 2 + read-write + + + 0 + Periodic refresh cycles will be triggered in frequency of 64KHz. + #0 + + + 1 + Periodic refresh cycles will be triggered in frequency of 32KHz. + #1 + + + + + REF_CNT + no description available + 16 + 16 + read-write + + + 0 + Reserved. + #0 + + + 1 + 1 cycle. + #1 + + + 1111111111111110 + 65534 cycles. + #1111111111111110 + + + 1111111111111111 + 65535 cycles. + #1111111111111111 + + + + + + + MDRWD + MMDC Core Read/Write Command Delay Register + 0x2C + 32 + read-write + 0xF9F26D2 + 0xFFFFFFFF + + + RTR_DIFF + no description available + 0 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RTW_DIFF + no description available + 3 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + WTW_DIFF + no description available + 6 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles (Default) + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + WTR_DIFF + no description available + 9 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles + #10 + + + 11 + 3 cycles (Default) + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RTW_SAME + no description available + 12 + 3 + read-write + + + 0 + 0 cycle + #0 + + + 1 + 1 cycle + #1 + + + 10 + 2 cycles (Default) + #10 + + + 11 + 3 cycles + #11 + + + 100 + 4 cycles + #100 + + + 101 + 5 cycles + #101 + + + 110 + 6 cycles + #110 + + + 111 + 7 cycles + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + tDAI + no description available + 16 + 13 + read-write + + + 0 + 1 cycle + #0 + + + 111110011111 + 4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock). + #111110011111 + + + 1111111111111 + 8192 cycles + #1111111111111 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + MDOR + MMDC Core Out of Reset Delays Register + 0x30 + 32 + read-write + 0x9F0E0E + 0xFFFFFFFF + + + RST_to_CKE + no description available + 0 + 6 + read-write + + + 0 + Reserved + #0 + + + 1 + Reserved + #1 + + + 10 + Reserved + #10 + + + 11 + 1 cycles + #11 + + + 10000 + 14 cycles (JEDEC value for DDR2/LPDDR2) - total of 200 us + #10000 + + + 100011 + 33 cycles (JEDEC value for DDR3) - total of 500 us + #100011 + + + 111110 + 60 cycles + #111110 + + + 111111 + 61 cycles + #111111 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + SDE_to_RST + no description available + 8 + 6 + read-write + + + 0 + Reserved + #0 + + + 1 + Reserved + #1 + + + 10 + Reserved + #10 + + + 11 + 1 cycles + #11 + + + 100 + 2 cycles + #100 + + + 10000 + 14 cycles (Jedec value for DDR3) - total of 200 us + #10000 + + + 111110 + 60 cycles + #111110 + + + 111111 + 61 cycles + #111111 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + tXPR + no description available + 16 + 8 + read-write + + + 0 + Reserved + #0 + + + 1 + 2 cycles + #1 + + + 10 + 3 cycles + #10 + + + 11111110 + 255 cycles + #11111110 + + + 11111111 + 256 cycles + #11111111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + MDMRR + MMDC Core MRR Data Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + MRR_READ_DATA0 + no description available + 0 + 8 + read-only + + + MRR_READ_DATA1 + no description available + 8 + 8 + read-only + + + MRR_READ_DATA2 + no description available + 16 + 8 + read-only + + + MRR_READ_DATA3 + no description available + 24 + 8 + read-only + + + + + MDCFG3LP + MMDC Core Timing Configuration Register 3 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + tRPab_LP + no description available + 0 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + tRPpb_LP + no description available + 4 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + tRCD_LP + no description available + 8 + 4 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 1110 + 15 clocks + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + RC_LP + no description available + 16 + 6 + read-write + + + 0 + 1 clock + #0 + + + 1 + 2 clocks + #1 + + + 10 + 3 clocks + #10 + + + 111110 + 63 clocks + #111110 + + + 111111 + Reserved + #111111 + + + + + RESERVED + no description available + 22 + 10 + read-only + + + + + MDMR4 + MMDC Core MR4 Derating Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + UPDATE_DE_REQ + no description available + 0 + 1 + read-write + + + 0 + Do nothing. + #0 + + + 1 + Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR + #1 + + + + + UPDATE_DE_ACK + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + tRCD_DE + no description available + 4 + 1 + read-write + + + 0 + Original tRCD is used. + #0 + + + 1 + tRCD is derated in 1 cycle. + #1 + + + + + tRC_DE + no description available + 5 + 1 + read-write + + + 0 + Original tRC is used. + #0 + + + 1 + tRC is derated in 1 cycle. + #1 + + + + + tRAS_DE + no description available + 6 + 1 + read-write + + + 0 + Original tRAS is used. + #0 + + + 1 + tRAS is derated in 1 cycle. + #1 + + + + + tRP_DE + no description available + 7 + 1 + read-write + + + 0 + Original tRP is used. + #0 + + + 1 + tRP is derated in 1 cycle. + #1 + + + + + tRRD_DE + no description available + 8 + 1 + read-write + + + 0 + Original tRRD is used. + #0 + + + 1 + tRRD is derated in 1 cycle. + #1 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + MDASP + MMDC Core Address Space Partition Register + 0x40 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + CS0_END + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 25 + read-only + + + + + MAARCR + MMDC Core AXI Reordering Control Regsiter + 0x400 + 32 + read-write + 0x514201F0 + 0xFFFFFFFF + + + ARCR_GUARD + no description available + 0 + 4 + read-write + + + 0000 + 15 (default) + #0000 + + + 0001 + 16 + #0001 + + + 1111 + 30 + #1111 + + + + + ARCR_DYN_MAX + no description available + 4 + 4 + read-write + + + 0000 + 0 + #0000 + + + 0001 + 1 + #0001 + + + 1111 + 15 (default) + #1111 + + + + + ARCR_DYN_JMP + no description available + 8 + 4 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + ARCR_ACC_HIT + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 1 + read-only + + + ARCR_PAG_HIT + no description available + 20 + 3 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + ARCR_RCH_EN + no description available + 24 + 1 + read-write + + + 0 + normal prioritization, no bypassing + #0 + + + 1 + accesses with QoS=='F' bypass the arbitration + #1 + + + + + RESERVED + no description available + 25 + 3 + read-only + + + ARCR_EXC_ERR_EN + no description available + 28 + 1 + read-write + + + 0 + violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00) + #0 + + + 1 + violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10) + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + ARCR_SEC_ERR_EN + no description available + 30 + 1 + read-write + + + 0 + security violation results in OKAY response (rresp/bresp=2'b00) + #0 + + + 1 + security violation results in SLAVE Error response (rresp/bresp=2'b10) + #1 + + + + + ARCR_SEC_ERR_LOCK + no description available + 31 + 1 + read-write + + + 0 + ARCR_SEC_ERR_EN is unlocked, so can be updated any moment + #0 + + + 1 + ARCR_SEC_ERR_EN is locked, so it can't be updated + #1 + + + + + + + MAPSR + MMDC Core Power Saving Control and Status Register + 0x404 + 32 + read-write + 0x1007 + 0xFFFFFFFF + + + PSD + no description available + 0 + 1 + read-write + + + 0 + power saving enabled + #0 + + + 1 + power saving disabled (default) + #1 + + + + + RESERVED + no description available + 1 + 3 + read-only + + + PSS + no description available + 4 + 1 + read-only + + + 0 + not in power saving + #0 + + + 1 + power saving + #1 + + + + + RIS + no description available + 5 + 1 + read-only + + + 0 + idle + #0 + + + 1 + not idle + #1 + + + + + WIS + no description available + 6 + 1 + read-only + + + 0 + idle + #0 + + + 1 + not idle + #1 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + PST + no description available + 8 + 8 + read-write + + + 00000000 + Reserved - this value is forbidden. + #00000000 + + + 00000001 + timer is configured to 64 clock cycles. + #00000001 + + + 00000010 + timer is configured to 128 clock cycles. + #00000010 + + + 00010000 + (Default)- 1024 clock cycles. + #00010000 + + + 11111111 + timer clock is configured to 16320 clock cycles. + #11111111 + + + + + RESERVED + no description available + 16 + 4 + read-only + + + LPMD + no description available + 20 + 1 + read-write + + + 0 + no lpmd request + #0 + + + 1 + lpmd request + #1 + + + + + DVFS + no description available + 21 + 1 + read-write + + + 0 + no dvfs request + #0 + + + 1 + dvfs request + #1 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + LPACK + no description available + 24 + 1 + read-only + + + DVACK + no description available + 25 + 1 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + MAEXIDR0 + MMDC Core Exclusive ID Monitor Register0 + 0x408 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + EXC_ID_MONITOR0 + no description available + 0 + 16 + read-write + + + EXC_ID_MONITOR1 + no description available + 16 + 16 + read-write + + + + + MAEXIDR1 + MMDC Core Exclusive ID Monitor Register1 + 0x40C + 32 + read-write + 0x600040 + 0xFFFFFFFF + + + EXC_ID_MONITOR2 + no description available + 0 + 16 + read-write + + + EXC_ID_MONITOR3 + no description available + 16 + 16 + read-write + + + + + MADPCR0 + MMDC Core Debug and Profiling Control Register 0 + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DBG_EN + no description available + 0 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + DBG_RST + no description available + 1 + 1 + read-write + + + 0 + no reset + #0 + + + 1 + reset + #1 + + + + + PRF_FRZ + no description available + 2 + 1 + read-write + + + 0 + profiling counters are not frozen + #0 + + + 1 + profiling counters are frozen + #1 + + + + + CYC_OVF + no description available + 3 + 1 + read-write + + + 0 + no overflow + #0 + + + 1 + overflow + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + SBS_EN + no description available + 8 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + SBS + no description available + 9 + 1 + read-write + + + 1 + Lanuch AXI pending access toward the DDR + #1 + + + 0 + No access will be launced toward the DDR + #0 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + MADPCR1 + MMDC Core Debug and Profiling Control Register 1 + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRF_AXI_ID + no description available + 0 + 16 + read-write + + + PRF_AXI_ID_MASK + no description available + 16 + 16 + read-write + + + 1 + AXI ID specific bit is chosen for profiling + #1 + + + 0 + AXI ID specific bit is ignored (don't care) + #0 + + + + + + + MADPSR0 + MMDC Core Debug and Profiling Status Register 0 + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + CYC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR1 + MMDC Core Debug and Profiling Status Register 1 + 0x41C + 32 + read-only + 0 + 0xFFFFFFFF + + + BUSY_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR2 + MMDC Core Debug and Profiling Status Register 2 + 0x420 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_ACC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR3 + MMDC Core Debug and Profiling Status Register 3 + 0x424 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_ACC_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR4 + MMDC Core Debug and Profiling Status Register 4 + 0x428 + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_BYTES_COUNT + no description available + 0 + 32 + read-only + + + + + MADPSR5 + MMDC Core Debug and Profiling Status Register 5 + 0x42C + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_BYTES_COUNT + no description available + 0 + 32 + read-only + + + + + MASBS0 + MMDC Core Step By Step Address Register + 0x430 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_ADDR + no description available + 0 + 32 + read-only + + + + + MASBS1 + MMDC Core Step By Step Address Attributes Register + 0x434 + 32 + read-only + 0 + 0xFFFFFFFF + + + SBS_VLD + no description available + 0 + 1 + read-only + + + 0 + not valid + #0 + + + 1 + valid + #1 + + + + + SBS_TYPE + no description available + 1 + 1 + read-only + + + 0 + write + #0 + + + 1 + read + #1 + + + + + SBS_LOCK + no description available + 2 + 2 + read-only + + + SBS_PROT + no description available + 4 + 3 + read-only + + + SBS_SIZE + no description available + 7 + 3 + read-only + + + 000 + 8 bits + #000 + + + 001 + 16 bits + #001 + + + 010 + 32 bits + #010 + + + 011 + 64 bits + #011 + + + 100 + 128bits + #100 + + + + + SBS_BURST + no description available + 10 + 2 + read-only + + + 00 + FIXED + #00 + + + 01 + INCR burst + #01 + + + 10 + WRAP burst + #10 + + + 11 + reserved + #11 + + + + + SBS_BUFF + no description available + 12 + 1 + read-only + + + SBS_LEN + no description available + 13 + 3 + read-only + + + 000 + burst of length 1 + #000 + + + 001 + burst of length 2 + #001 + + + 111 + burst of length 8 + #111 + + + + + SBS_AXI_ID + no description available + 16 + 16 + read-only + + + + + MAGENP + MMDC Core General Purpose Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + GP31_GP0 + no description available + 0 + 32 + read-write + + + + + MPZQHWCTRL + MMDC PHY ZQ HW control register + 0x800 + 32 + read-write + 0xA1380000 + 0xFFFFFFFF + + + ZQ_MODE + no description available + 0 + 2 + read-write + + + 0 + No ZQ calibration is issued. (Default) + #0 + + + 1 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh. + #1 + + + 10 + ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh + #10 + + + 11 + ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh + #11 + + + + + ZQ_HW_PER + no description available + 2 + 4 + read-write + + + 0000 + ZQ calibration is performed every 1 ms. + #0000 + + + 0001 + ZQ calibration is performed every 2 ms. + #0001 + + + 0010 + ZQ calibration is performed every 4 ms. + #0010 + + + 1010 + ZQ calibration is performed every 1 ms. + #1010 + + + 1110 + ZQ calibration is performed every 16 ms. + #1110 + + + 1111 + ZQ calibration is performed every 32 ms. + #1111 + + + + + ZQ_HW_PU_RES + no description available + 6 + 5 + read-only + + + 00000 + Min. resistance. + #00000 + + + 11111 + Max. resistance. + #11111 + + + + + ZQ_HW_PD_RES + no description available + 11 + 5 + read-only + + + 00000 + Max. resistance. + #00000 + + + 11111 + Min. resistance. + #11111 + + + + + ZQ_HW_FOR + no description available + 16 + 1 + read-write + + + TZQ_INIT + no description available + 17 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles + #010 + + + 011 + 256 cycles + #011 + + + 100 + 512 cycles - Default (JEDEC value for DDR3) + #100 + + + 101 + 1024 cycles + #101 + + + + + TZQ_OPER + no description available + 20 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles + #010 + + + 011 + 256 cycles - Default (JEDEC value for DDR3) + #011 + + + 100 + 512 cycles + #100 + + + 101 + 1024 cycles + #101 + + + + + TZQ_CS + no description available + 23 + 3 + read-write + + + 000 + Reserved + #000 + + + 001 + Reserved + #001 + + + 010 + 128 cycles (Default) + #010 + + + 011 + 256 cycles + #011 + + + 100 + 512 cycles + #100 + + + 101 + 1024 cycles + #101 + + + + + RESERVED + no description available + 26 + 1 + read-only + + + ZQ_EARLY_COMPARATOR_EN_TIMER + no description available + 27 + 5 + read-write + + + 0 + - 0x6 Reserved + #0 + + + 111 + 8 cycles + #111 + + + 10100 + 21 cycles (Default) + #10100 + + + 11110 + 31 cycles + #11110 + + + 11111 + 32 cycles + #11111 + + + + + + + MPZQSWCTRL + MMDC PHY ZQ SW control register + 0x804 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZQ_SW_FOR + no description available + 0 + 1 + read-write + + + ZQ_SW_RES + no description available + 1 + 1 + read-only + + + 0 + Current ZQ calibration voltage is less than VDD/2. + #0 + + + 1 + Current ZQ calibration voltage is more than VDD/2 + #1 + + + + + ZQ_SW_PU_VAL + no description available + 2 + 5 + read-write + + + 00000 + Min. resistance. + #00000 + + + 11111 + Max. resistance. + #11111 + + + + + ZQ_SW_PD_VAL + no description available + 7 + 5 + read-write + + + 00000 + Max. resistance. + #00000 + + + 11111 + Min. resistance. + #11111 + + + + + ZQ_SW_PD + no description available + 12 + 1 + read-write + + + 0 + PU resistor calibration + #0 + + + 1 + PD resistor calibration + #1 + + + + + USE_ZQ_SW_VAL + no description available + 13 + 1 + read-write + + + 0 + Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls. + #0 + + + 1 + Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls. + #1 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + ZQ_CMP_OUT_SMP + no description available + 16 + 2 + read-write + + + 00 + 7 cycles + #00 + + + 01 + 15 cycles + #01 + + + 10 + 23 cycles + #10 + + + 11 + 31 cycles + #11 + + + + + RESERVED + no description available + 18 + 14 + read-only + + + + + MPWLGCR + MMDC PHY Write Leveling Configuration and Error Status Register + 0x808 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WL_EN + no description available + 0 + 1 + read-write + + + SW_WL_EN + no description available + 1 + 1 + read-write + + + SW_WL_CNT_EN + no description available + 2 + 1 + read-write + + + 0 + MMDC doesn't count 25+15 cycles before issuing write-leveling DQS. + #0 + + + 1 + MMDC counts 25+15 cycles before issuing write-leveling DQS. + #1 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + WL_SW_RES0 + no description available + 4 + 1 + read-only + + + 0 + DQS0 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS0 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES1 + no description available + 5 + 1 + read-only + + + 0 + DQS1 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS1 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES2 + no description available + 6 + 1 + read-only + + + 0 + DQS2 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS2 sampled high CK during SW write-leveling. + #1 + + + + + WL_SW_RES3 + no description available + 7 + 1 + read-only + + + 0 + DQS3 sampled low CK during SW write-leveling. + #0 + + + 1 + DQS3 sampled high CK during SW write-leveling. + #1 + + + + + WL_HW_ERR0 + no description available + 8 + 1 + read-only + + + 0 + No error was found on byte0 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte0 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR1 + no description available + 9 + 1 + read-only + + + 0 + No error was found on byte1 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte1 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR2 + no description available + 10 + 1 + read-only + + + 0 + No error was found on byte2 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte2 during write-leveling HW calibration. + #1 + + + + + WL_HW_ERR3 + no description available + 11 + 1 + read-only + + + 0 + No error was found on byte3 during write-leveling HW calibration. + #0 + + + 1 + An error was found on byte3 during write-leveling HW calibration. + #1 + + + + + RESERVED + no description available + 12 + 20 + read-only + + + + + MPWLDECTRL0 + MMDC PHY Write Leveling Delay Control Register 0 + 0x80C + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_HC_DEL0 + no description available + 8 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL0 + no description available + 9 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + WL_DL_ABS_OFFSET1 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_HC_DEL1 + no description available + 24 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL1 + no description available + 25 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPWLDECTRL1 + MMDC PHY Write Leveling Delay Control Register 1 + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + WL_DL_ABS_OFFSET2 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_HC_DEL2 + no description available + 8 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL2 + no description available + 9 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 11 + 5 + read-only + + + WL_DL_ABS_OFFSET3 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_HC_DEL3 + no description available + 24 + 1 + read-write + + + 0 + No delay is added. + #0 + + + 1 + Half cycle delay is added. + #1 + + + + + WL_CYC_DEL3 + no description available + 25 + 2 + read-write + + + 0 + No delay is added. + #0 + + + 1 + 1 cycle delay is added. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPWLDLST + MMDC PHY Write Leveling delay-line Status Register + 0x814 + 32 + read-only + 0 + 0xFFFFFFFF + + + WL_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + WL_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + WL_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + WL_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPODTCTRL + MMDC PHY ODT control register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + ODT_WR_PAS_EN + no description available + 0 + 1 + read-write + + + 0 + Inactive CS ODT pin is disabled during write accesses to other CS. + #0 + + + 1 + Inactive CS ODT pin is enabled during write accesses to other CS. + #1 + + + + + ODT_WR_ACT_EN + no description available + 1 + 1 + read-write + + + 0 + Active CS ODT pin is disabled during write access. + #0 + + + 1 + Active CS ODT pin is enabled during write access. + #1 + + + + + ODT_RD_PAS_EN + no description available + 2 + 1 + read-write + + + 0 + Inactive CS ODT pin is disabled during read accesses to other CS. + #0 + + + 1 + Inactive CS ODT pin is enabled during read accesses to other CS. + #1 + + + + + ODT_RD_ACT_EN + no description available + 3 + 1 + read-write + + + 0 + Active CS ODT pin is disabled during read access. + #0 + + + 1 + Active CS ODT pin is enabled during read access. + #1 + + + + + ODT0_INT_RES + no description available + 4 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + ODT1_INT_RES + no description available + 8 + 3 + read-write + + + 0000 + Rtt_Nom Disabled. + #0000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + ODT2_INT_RES + no description available + 12 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + ODT3_INT_RES + no description available + 16 + 3 + read-write + + + 000 + Rtt_Nom Disabled. + #000 + + + 001 + Rtt_Nom 120 Ohm /75 Ohm(ddr2) + #001 + + + 010 + Rtt_Nom 60 Ohm /150 Ohm(ddr2) + #010 + + + 011 + Rtt_Nom 40 Ohm /50 Ohm(ddr2) + #011 + + + 100 + Rtt_Nom 30 Ohm /37.5 Ohm(ddr2) + #100 + + + 101 + Rtt_Nom 24 Ohm /30 Ohm(ddr2) + #101 + + + 110 + Rtt_Nom 20 Ohm /25 Ohm(ddr2) + #110 + + + 111 + Rtt_Nom 17 Ohm /21 Ohm(ddr2) + #111 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + MPRDDQBY0DL + MMDC PHY Read DQ Byte0 Delay Register + 0x81C + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq0_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq0 delay + #000 + + + 001 + Add dq0 delay of 1 delay unit + #001 + + + 010 + Add dq0 delay of 2 delay units. + #010 + + + 011 + Add dq0 delay of 3 delay units. + #011 + + + 100 + Add dq0 delay of 4 delay units. + #100 + + + 101 + Add dq0 delay of 5 delay units. + #101 + + + 110 + Add dq0 delay of 6 delay units. + #110 + + + 111 + Add dq0 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq1_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq1 delay + #000 + + + 001 + Add dq1 delay of 1 delay unit + #001 + + + 010 + Add dq1 delay of 2 delay units. + #010 + + + 011 + Add dq1 delay of 3 delay units. + #011 + + + 100 + Add dq1 delay of 4 delay units. + #100 + + + 101 + Add dq1 delay of 5 delay units. + #101 + + + 110 + Add dq1 delay of 6 delay units. + #110 + + + 111 + Add dq1 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq2_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq2 delay + #000 + + + 001 + Add dq2 delay of 1 delay unit + #001 + + + 010 + Add dq2 delay of 2 delay units. + #010 + + + 011 + Add dq2 delay of 3 delay units. + #011 + + + 100 + Add dq2 delay of 4 delay units. + #100 + + + 101 + Add dq2 delay of 5 delay units. + #101 + + + 110 + Add dq2 delay of 6 delay units. + #110 + + + 111 + Add dq2 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq3_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq3 delay + #000 + + + 001 + Add dq3 delay of 1 delay unit + #001 + + + 010 + Add dq3 delay of 2 delay units. + #010 + + + 011 + Add dq3 delay of 3 delay units. + #011 + + + 100 + Add dq3 delay of 4 delay units. + #100 + + + 101 + Add dq3 delay of 5 delay units. + #101 + + + 110 + Add dq3 delay of 6 delay units. + #110 + + + 111 + Add dq3 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq4_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq4 delay + #000 + + + 001 + Add dq4 delay of 1 delay unit + #001 + + + 010 + Add dq4 delay of 2 delay units. + #010 + + + 011 + Add dq4 delay of 3 delay units. + #011 + + + 100 + Add dq4 delay of 4 delay units. + #100 + + + 101 + Add dq4 delay of 5 delay units. + #101 + + + 110 + Add dq4 delay of 6 delay units. + #110 + + + 111 + Add dq4 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq5_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq5 delay + #000 + + + 001 + Add dq5 delay of 1 delay unit + #001 + + + 010 + Add dq5 delay of 2 delay units. + #010 + + + 011 + Add dq5 delay of 3 delay units. + #011 + + + 100 + Add dq5 delay of 4 delay units. + #100 + + + 101 + Add dq5 delay of 5 delay units. + #101 + + + 110 + Add dq5 delay of 6 delay units. + #110 + + + 111 + Add dq5 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq6_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq6 delay + #000 + + + 001 + Add dq6 delay of 1 delay unit + #001 + + + 010 + Add dq6 delay of 2 delay units. + #010 + + + 011 + Add dq6 delay of 3 delay units. + #011 + + + 100 + Add dq6 delay of 4 delay units. + #100 + + + 101 + Add dq6 delay of 5 delay units. + #101 + + + 110 + Add dq6 delay of 6 delay units. + #110 + + + 111 + Add dq6 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq7_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq7 delay + #000 + + + 001 + Add dq7 delay of 1 delay unit + #001 + + + 010 + Add dq7 delay of 2 delay units. + #010 + + + 011 + Add dq7 delay of 3 delay units. + #011 + + + 100 + Add dq7 delay of 4 delay units. + #100 + + + 101 + Add dq7 delay of 5 delay units. + #101 + + + 110 + Add dq7 delay of 6 delay units. + #110 + + + 111 + Add dq7 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY1DL + MMDC PHY Read DQ Byte1 Delay Register + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq8_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq8 delay + #000 + + + 001 + Add dq8 delay of 1 delay unit + #001 + + + 010 + Add dq8 delay of 2 delay units. + #010 + + + 011 + Add dq8 delay of 3 delay units. + #011 + + + 100 + Add dq8 delay of 4 delay units. + #100 + + + 101 + Add dq8 delay of 5 delay units. + #101 + + + 110 + Add dq8 delay of 6 delay units. + #110 + + + 111 + Add dq8 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq9_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq9 delay + #000 + + + 001 + Add dq9 delay of 1 delay unit + #001 + + + 010 + Add dq9 delay of 2 delay units. + #010 + + + 011 + Add dq9 delay of 3 delay units. + #011 + + + 100 + Add dq9 delay of 4 delay units. + #100 + + + 101 + Add dq9 delay of 5 delay units. + #101 + + + 110 + Add dq9 delay of 6 delay units. + #110 + + + 111 + Add dq9 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq10_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq10 delay + #000 + + + 001 + Add dq10 delay of 1 delay unit + #001 + + + 010 + Add dq10 delay of 2 delay units. + #010 + + + 011 + Add dq10 delay of 3 delay units. + #011 + + + 100 + Add dq10 delay of 4 delay units. + #100 + + + 101 + Add dq10 delay of 5 delay unit + #101 + + + 110 + Add dq10 delay of 6 delay units. + #110 + + + 111 + Add dq10 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq11_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq11 delay + #000 + + + 001 + Add dq11 delay of 1 delay unit + #001 + + + 010 + Add dq11 delay of 2 delay units. + #010 + + + 011 + Add dq11 delay of 3 delay units. + #011 + + + 100 + Add dq11 delay of 4 delay units. + #100 + + + 101 + Add dq11 delay of 5 delay units. + #101 + + + 110 + Add dq11 delay of 6 delay units. + #110 + + + 111 + Add dq11 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq12_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq12 delay + #000 + + + 001 + Add dq12 delay of 1 delay unit + #001 + + + 010 + Add dq12 delay of 2 delay units. + #010 + + + 011 + Add dq12 delay of 3 delay units. + #011 + + + 100 + Add dq12 delay of 4 delay units. + #100 + + + 101 + Add dq12 delay of 5 delay units. + #101 + + + 110 + Add dq12 delay of 6 delay units. + #110 + + + 111 + Add dq12 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq13_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq13 delay + #000 + + + 001 + Add dq13 delay of 1 delay unit + #001 + + + 010 + Add dq13 delay of 2 delay units. + #010 + + + 011 + Add dq13 delay of 3 delay units. + #011 + + + 100 + Add dq13 delay of 4 delay units. + #100 + + + 101 + Add dq13 delay of 5 delay units. + #101 + + + 110 + Add dq13 delay of 6 delay units. + #110 + + + 111 + Add dq13 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq14_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq14 delay + #000 + + + 001 + Add dq14 delay of 1 delay unit + #001 + + + 010 + Add dq14 delay of 2 delay units. + #010 + + + 011 + Add dq14 delay of 3 delay units. + #011 + + + 100 + Add dq14 delay of 4 delay units. + #100 + + + 101 + Add dq14 delay of 5 delay units. + #101 + + + 110 + Add dq14 delay of 6 delay units. + #110 + + + 111 + Add dq14 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq15_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq15 delay + #000 + + + 001 + Add dq15 delay of 1 delay unit + #001 + + + 010 + Add dq15 delay of 2 delay units. + #010 + + + 011 + Add dq15 delay of 3 delay units. + #011 + + + 100 + Add dq15 delay of 4 delay units. + #100 + + + 101 + Add dq15 delay of 5 delay units. + #101 + + + 110 + Add dq15 delay of 6 delay units. + #110 + + + 111 + Add dq15 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY2DL + MMDC PHY Read DQ Byte2 Delay Register + 0x824 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq16_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq16 delay + #000 + + + 001 + Add dq16 delay of 1 delay unit + #001 + + + 010 + Add dq16 delay of 2 delay units. + #010 + + + 011 + Add dq16 delay of 3 delay units. + #011 + + + 100 + Add dq16 delay of 4 delay units. + #100 + + + 101 + Add dq16 delay of 5 delay units. + #101 + + + 110 + Add dq16 delay of 6 delay units. + #110 + + + 111 + Add dq16 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq17_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq17 delay + #000 + + + 001 + Add dq17 delay of 1 delay unit + #001 + + + 010 + Add dq17 delay of 2 delay units. + #010 + + + 011 + Add dq17 delay of 3 delay units. + #011 + + + 100 + Add dq17 delay of 4 delay units. + #100 + + + 101 + Add dq17 delay of 5 delay units. + #101 + + + 110 + Add dq17 delay of 6 delay units. + #110 + + + 111 + Add dq17 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq18_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq18 delay + #000 + + + 001 + Add dq18 delay of 1 delay unit + #001 + + + 010 + Add dq18 delay of 2 delay units. + #010 + + + 011 + Add dq18 delay of 3 delay units. + #011 + + + 100 + Add dq18 delay of 4 delay units. + #100 + + + 101 + Add dq18 delay of 5 delay units. + #101 + + + 110 + Add dq18 delay of 6 delay units. + #110 + + + 111 + Add dq18 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq19_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq19 delay + #000 + + + 001 + Add dq19 delay of 1 delay unit + #001 + + + 010 + Add dq19 delay of 2 delay units. + #010 + + + 011 + Add dq19 delay of 3 delay units. + #011 + + + 100 + Add dq19 delay of 4 delay units. + #100 + + + 101 + Add dq19 delay of 5 delay units. + #101 + + + 110 + Add dq19 delay of 6 delay units. + #110 + + + 111 + Add dq19 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq20_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq20 delay + #000 + + + 001 + Add dq20 delay of 1 delay unit + #001 + + + 010 + Add dq20 delay of 2 delay units. + #010 + + + 011 + Add dq20 delay of 3 delay units. + #011 + + + 100 + Add dq20 delay of 4 delay units. + #100 + + + 101 + Add dq20 delay of 5 delay units. + #101 + + + 110 + Add dq20 delay of 6 delay units. + #110 + + + 111 + Add dq20 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq21_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq21 delay + #000 + + + 001 + Add dq21 delay of 1 delay unit + #001 + + + 010 + Add dq21 delay of 2 delay units. + #010 + + + 011 + Add dq21 delay of 3 delay units. + #011 + + + 100 + Add dq21 delay of 4 delay units. + #100 + + + 101 + Add dq21 delay of 5 delay units. + #101 + + + 110 + Add dq21 delay of 6 delay units. + #110 + + + 111 + Add dq21 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq22_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq22 delay + #000 + + + 001 + Add dq22 delay of 1 delay unit + #001 + + + 010 + Add dq22 delay of 2 delay units. + #010 + + + 011 + Add dq22 delay of 3 delay units. + #011 + + + 100 + Add dq22 delay of 4 delay units. + #100 + + + 101 + Add dq22 delay of 5 delay units. + #101 + + + 110 + Add dq22 delay of 6 delay units. + #110 + + + 111 + Add dq22 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq23_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq23 delay + #000 + + + 001 + Add dq23 delay of 1 delay unit + #001 + + + 010 + Add dq23 delay of 2 delay units. + #010 + + + 011 + Add dq23 delay of 3 delay units. + #011 + + + 100 + Add dq23 delay of 4 delay units. + #100 + + + 101 + Add dq23 delay of 5 delay units. + #101 + + + 110 + Add dq23 delay of 6 delay units. + #110 + + + 111 + Add dq23 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDQBY3DL + MMDC PHY Read DQ Byte3 Delay Register + 0x828 + 32 + read-write + 0 + 0xFFFFFFFF + + + rd_dq24_del + no description available + 0 + 3 + read-write + + + 000 + No change in dq24 delay + #000 + + + 001 + Add dq24 delay of 1 delay unit + #001 + + + 010 + Add dq24 delay of 2 delay units. + #010 + + + 011 + Add dq24 delay of 3 delay units. + #011 + + + 100 + Add dq24 delay of 4 delay units. + #100 + + + 101 + Add dq24 delay of 5 delay units. + #101 + + + 110 + Add dq24 delay of 6 delay units. + #110 + + + 111 + Add dq24 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + rd_dq25_del + no description available + 4 + 3 + read-write + + + 000 + No change in dq25 delay + #000 + + + 001 + Add dq25 delay of 1 delay unit + #001 + + + 010 + Add dq25 delay of 2 delay units. + #010 + + + 011 + Add dq25 delay of 3 delay units. + #011 + + + 100 + Add dq25 delay of 4 delay units. + #100 + + + 101 + Add dq25 delay of 5 delay units. + #101 + + + 110 + Add dq25 delay of 6 delay units. + #110 + + + 111 + Add dq25 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + rd_dq26_del + no description available + 8 + 3 + read-write + + + 000 + No change in dq26 delay + #000 + + + 001 + Add dq26 delay of 1 delay unit + #001 + + + 010 + Add dq26 delay of 2 delay units. + #010 + + + 011 + Add dq26 delay of 3 delay units. + #011 + + + 100 + Add dq26 delay of 4 delay units. + #100 + + + 101 + Add dq26 delay of 5 delay units. + #101 + + + 110 + Add dq26 delay of 6 delay units. + #110 + + + 111 + Add dq26 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + rd_dq27_del + no description available + 12 + 3 + read-write + + + 000 + No change in dq27 delay + #000 + + + 001 + Add dq27 delay of 1 delay unit + #001 + + + 010 + Add dq27 delay of 2 delay units. + #010 + + + 011 + Add dq27 delay of 3 delay units. + #011 + + + 100 + Add dq27 delay of 4 delay units. + #100 + + + 101 + Add dq27 delay of 5 delay units. + #101 + + + 110 + Add dq27 delay of 6 delay units. + #110 + + + 111 + Add dq27 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + rd_dq28_del + no description available + 16 + 3 + read-write + + + 000 + No change in dq28 delay + #000 + + + 001 + Add dq28 delay of 1 delay unit + #001 + + + 010 + Add dq28 delay of 2 delay units. + #010 + + + 011 + Add dq28 delay of 3 delay units. + #011 + + + 100 + Add dq28 delay of 4 delay units. + #100 + + + 101 + Add dq28 delay of 5 delay units. + #101 + + + 110 + Add dq28 delay of 6 delay units. + #110 + + + 111 + Add dq28 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + rd_dq29_del + no description available + 20 + 3 + read-write + + + 000 + No change in dq29 delay + #000 + + + 001 + Add dq29 delay of 1 delay unit + #001 + + + 010 + Add dq29 delay of 2 delay units. + #010 + + + 011 + Add dq29 delay of 3 delay units. + #011 + + + 100 + Add dq29 delay of 4 delay units. + #100 + + + 101 + Add dq29 delay of 5 delay units. + #101 + + + 110 + Add dq29 delay of 6 delay units. + #110 + + + 111 + Add dq29 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + rd_dq30_del + no description available + 24 + 3 + read-write + + + 000 + No change in dq30 delay + #000 + + + 001 + Add dq30 delay of 1 delay unit + #001 + + + 010 + Add dq30 delay of 2 delay units. + #010 + + + 011 + Add dq30 delay of 3 delay units. + #011 + + + 100 + Add dq30 delay of 4 delay units. + #100 + + + 101 + Add dq30 delay of 5 delay units. + #101 + + + 110 + Add dq30 delay of 6 delay units. + #110 + + + 111 + Add dq30 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + rd_dq31_del + no description available + 28 + 3 + read-write + + + 000 + No change in dq31 delay + #000 + + + 001 + Add dq31 delay of 1 delay unit + #001 + + + 010 + Add dq31 delay of 2 delay units. + #010 + + + 011 + Add dq31 delay of 3 delay units. + #011 + + + 100 + Add dq31 delay of 4 delay units. + #100 + + + 101 + Add dq31 delay of 5 delay units. + #101 + + + 110 + Add dq31 delay of 6 delay units. + #110 + + + 111 + Add dq31 delay of 7 delay units. + #111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDQBY0DL + MMDC PHY Write DQ Byte0 Delay Register + 0x82C + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq0_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq0 delay + #00 + + + 01 + Add dq0 delay of 1 delay unit. + #01 + + + 10 + Add dq0 delay of 2 delay units. + #10 + + + 11 + Add dq0 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq1_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq1 delay + #00 + + + 01 + Add dq1 delay of 1 delay unit. + #01 + + + 10 + Add dq1 delay of 2 delay units. + #10 + + + 11 + Add dq1 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq2_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq2 delay + #00 + + + 01 + Add dq2 delay of 1 delay unit. + #01 + + + 10 + Add dq2 delay of 2 delay units. + #10 + + + 11 + Add dq2 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq3_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq3 delay + #00 + + + 01 + Add dq3 delay of 1 delay unit. + #01 + + + 10 + Add dq3 delay of 2 delay units. + #10 + + + 11 + Add dq3 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq4_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq4 delay + #00 + + + 01 + Add dq4 delay of 1 delay unit.. + #01 + + + 10 + Add dq4 delay of 2 delay units. + #10 + + + 11 + Add dq4 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq5_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq5 delay + #00 + + + 01 + Add dq5 delay of 1 delay unit. + #01 + + + 10 + Add dq5 delay of 2 delay units. + #10 + + + 11 + Add dq5 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq6_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq6 delay + #00 + + + 01 + Add dq6 delay of 1 delay unit. + #01 + + + 10 + Add dq6 delay of 2 delay units. + #10 + + + 11 + Add dq6 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq7_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq7 delay + #00 + + + 01 + Add dq7 delay of 1 delay unit. + #01 + + + 10 + Add dq7 delay of 2 delay units. + #10 + + + 11 + Add dq7 delay of 3 delay units. + #11 + + + + + wr_dm0_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm0 delay + #00 + + + 01 + Add dm0 delay of 1 delay unit. + #01 + + + 10 + Add dm0 delay of 2 delay units. + #10 + + + 11 + Add dm0 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY1DL + MMDC PHY Write DQ Byte1 Delay Register + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq8_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq8 delay + #00 + + + 01 + Add dq8 delay of 1 delay unit. + #01 + + + 10 + Add dq8 delay of 2 delay units. + #10 + + + 11 + Add dq8 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq9_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq9 delay + #00 + + + 01 + Add dq9 delay of 1 delay unit. + #01 + + + 10 + Add dq9 delay of 2 delay units. + #10 + + + 11 + Add dq9 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq10_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq10 delay + #00 + + + 01 + Add dq10 delay of 1 delay unit. + #01 + + + 10 + Add dq10 delay of 2 delay units. + #10 + + + 11 + Add dq10 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq11_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq11 delay + #00 + + + 01 + Add dq11 delay of 1 delay unit. + #01 + + + 10 + Add dq11 delay of 2 delay units. + #10 + + + 11 + Add dq11 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq12_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq12 delay + #00 + + + 01 + Add dq12 delay of 1 delay unit. + #01 + + + 10 + Add dq12 delay of 2 delay units. + #10 + + + 11 + Add dq12 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq13_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq13 delay + #00 + + + 01 + Add dq13 delay of 1 delay unit. + #01 + + + 10 + Add dq13 delay of 2 delay units. + #10 + + + 11 + Add dq13 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq14_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq14 delay + #00 + + + 01 + Add dq14 delay of 1 delay unit. + #01 + + + 10 + Add dq14 delay of 2 delay units. + #10 + + + 11 + Add dq14 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq15_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq15 delay + #00 + + + 01 + Add dq15 delay of 1 delay unit. + #01 + + + 10 + Add dq15 delay of 2 delay units. + #10 + + + 11 + Add dq15 delay of 3 delay units. + #11 + + + + + wr_dm1_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm1 delay + #00 + + + 01 + Add dm1 delay of 1 delay unit. + #01 + + + 10 + Add dm1 delay of 2 delay units. + #10 + + + 11 + Add dm1 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY2DL + MMDC PHY Write DQ Byte2 Delay Register + 0x834 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq16_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq16 delay + #00 + + + 01 + Add dq16 delay of 1 delay unit. + #01 + + + 10 + Add dq16 delay of 2 delay units. + #10 + + + 11 + Add dq16 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq17_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq17 delay + #00 + + + 01 + Add dq17 delay of 1 delay unit. + #01 + + + 10 + Add dq17 delay of 2 delay units. + #10 + + + 11 + Add dq17 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq18_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq18 delay + #00 + + + 01 + Add dq18 delay of 1 delay unit. + #01 + + + 10 + Add dq18 delay of 2 delay units. + #10 + + + 11 + Add dq18 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq19_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq19 delay + #00 + + + 01 + Add dq19 delay of 1 delay unit. + #01 + + + 10 + Add dq19 delay of 2 delay units. + #10 + + + 11 + Add dq19 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq20_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq20 delay + #00 + + + 01 + Add dq20 delay of 1 delay unit. + #01 + + + 10 + Add dq20 delay of 2 delay units. + #10 + + + 11 + Add dq20 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq21_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq21 delay + #00 + + + 01 + Add dq21 delay of 1 delay unit. + #01 + + + 10 + Add dq21 delay of 2 delay units. + #10 + + + 11 + Add dq21 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq22_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq22 delay + #00 + + + 01 + Add dq22 delay of 1 delay unit. + #01 + + + 10 + Add dq22 delay of 2 delay units. + #10 + + + 11 + Add dq22 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq23_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq23 delay + #00 + + + 01 + Add dq23 delay of 1 delay unit. + #01 + + + 10 + Add dq23 delay of 2 delay units. + #10 + + + 11 + Add dq23 delay of 3 delay units. + #11 + + + + + wr_dm2_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm2 delay + #00 + + + 01 + Add dm2 delay of 1 delay unit. + #01 + + + 10 + Add dm2 delay of 2 delay units. + #10 + + + 11 + Add dm2 delay of 3 delay units. + #11 + + + + + + + MPWRDQBY3DL + MMDC PHY Write DQ Byte3 Delay Register + 0x838 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_dq24_del + no description available + 0 + 2 + read-write + + + 00 + No change in dq24 delay + #00 + + + 01 + Add dq24 delay of 1 delay unit. + #01 + + + 10 + Add dq24 delay of 2 delay units. + #10 + + + 11 + Add dq24 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + wr_dq25_del + no description available + 4 + 2 + read-write + + + 00 + No change in dq25 delay + #00 + + + 01 + Add dq25 delay of 1 delay unit. + #01 + + + 10 + Add dq25 delay of 2 delay units. + #10 + + + 11 + Add dq25 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + wr_dq26_del + no description available + 8 + 2 + read-write + + + 00 + No change in dq26 delay + #00 + + + 01 + Add dq26 delay of 1 delay unit. + #01 + + + 10 + Add dq26 delay of 2 delay units. + #10 + + + 11 + Add dq26 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + wr_dq27_del + no description available + 12 + 2 + read-write + + + 00 + No change in dq27 delay + #00 + + + 01 + Add dq27 delay of 1 delay unit. + #01 + + + 10 + Add dq27 delay of 2 delay units. + #10 + + + 11 + Add dq27 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + wr_dq28_del + no description available + 16 + 2 + read-write + + + 00 + No change in dq28 delay + #00 + + + 01 + Add dq28 delay of 1 delay unit. + #01 + + + 10 + Add dq28 delay of 2 delay units. + #10 + + + 11 + Add dq28 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + wr_dq29_del + no description available + 20 + 2 + read-write + + + 00 + No change in dq29 delay + #00 + + + 01 + Add dq29 delay of 1 delay unit. + #01 + + + 10 + Add dq29 delay of 2 delay units. + #10 + + + 11 + Add dq29 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 22 + 2 + read-only + + + wr_dq30_del + no description available + 24 + 2 + read-write + + + 00 + No change in dq30 delay + #00 + + + 01 + Add dq30 delay of 1 delay unit. + #01 + + + 10 + Add dq30 delay of 2 delay units. + #10 + + + 11 + Add dq30 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 26 + 2 + read-only + + + wr_dq31_del + no description available + 28 + 2 + read-write + + + 00 + No change in dq31 delay + #00 + + + 01 + Add dq31 delay of 1 delay unit. + #01 + + + 10 + Add dq31 delay of 2 delay units. + #10 + + + 11 + Add dq31 delay of 3 delay units. + #11 + + + + + wr_dm3_del + no description available + 30 + 2 + read-write + + + 00 + No change in dm3 delay + #00 + + + 01 + Add dm3 delay of 1 delay unit. + #01 + + + 10 + Add dm3 delay of 2 delay units. + #10 + + + 11 + Add dm3 delay of 3 delay units. + #11 + + + + + + + MPDGCTRL0 + MMDC PHY Read DQS Gating Control Register 0 + 0x83C + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_HC_DEL0 + no description available + 8 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + HW_DG_ERR + no description available + 12 + 1 + read-only + + + 0 + No error was found during the DQS gating HW calibration process. + #0 + + + 1 + An error was found during the DQS gating HW calibration process. + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + DG_DL_ABS_OFFSET1 + no description available + 16 + 7 + read-write + + + DG_EXT_UP + no description available + 23 + 1 + read-write + + + DG_HC_DEL1 + no description available + 24 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + HW_DG_EN + no description available + 28 + 1 + read-write + + + 0 + Disable automatic read DQS gating calibration + #0 + + + 1 + Start automatic read DQS gating calibration + #1 + + + + + DG_DIS + no description available + 29 + 1 + read-write + + + 0 + Read DQS gating mechanism is enbled + #0 + + + 1 + Read DQS gating mechanism is disabled + #1 + + + + + DG_CMP_CYC + no description available + 30 + 1 + read-write + + + 0 + MMDC waits 16 DDR cycles + #0 + + + 1 + MMDC waits 32 DDR cycles + #1 + + + + + RST_RD_FIFO + no description available + 31 + 1 + read-write + + + + + MPDGCTRL1 + MMDC PHY Read DQS Gating Control Register 1 + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + DG_DL_ABS_OFFSET2 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_HC_DEL2 + no description available + 8 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + DG_DL_ABS_OFFSET3 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + DG_HC_DEL3 + no description available + 24 + 4 + read-write + + + 0000 + 0 cycles delay. + #0000 + + + 0001 + Half cycle delay. + #0001 + + + 0010 + 1 cycle delay + #0010 + + + 1101 + 6.5 cycles delay + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + MPDGDLST0 + MMDC PHY Read DQS Gating delay-line Status Register + 0x844 + 32 + read-only + 0 + 0xFFFFFFFF + + + DG_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + DG_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + DG_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + DG_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLCTL + MMDC PHY Read delay-lines Configuration Register + 0x848 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + RD_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + RD_DL_ABS_OFFSET1 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + RD_DL_ABS_OFFSET2 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + RD_DL_ABS_OFFSET3 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLST + MMDC PHY Read delay-lines Status Register + 0x84C + 32 + read-only + 0 + 0xFFFFFFFF + + + RD_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + RD_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + RD_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + RD_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLCTL + MMDC PHY Write delay-lines Configuration Register + 0x850 + 32 + read-write + 0x40404040 + 0xFFFFFFFF + + + WR_DL_ABS_OFFSET0 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + WR_DL_ABS_OFFSET1 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + WR_DL_ABS_OFFSET2 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + WR_DL_ABS_OFFSET3 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLST + MMDC PHY Write delay-lines Status Register + 0x854 + 32 + read-only + 0 + 0xFFFFFFFF + + + WR_DL_UNIT_NUM0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + WR_DL_UNIT_NUM1 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + WR_DL_UNIT_NUM2 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + WR_DL_UNIT_NUM3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPSDCTRL + MMDC PHY CK Control Register + 0x858 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + SDclk0_del + no description available + 8 + 2 + read-write + + + 00 + No change in DDR clock0 delay + #00 + + + 01 + Add DDR clock0 delay of 1 delay unit. + #01 + + + 10 + Add DDR clock0 delay of 2 delay units. + #10 + + + 11 + Add DDR clock0 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + MPZQLP2CTL + MMDC ZQ LPDDR2 HW Control Register + 0x85C + 32 + read-write + 0x1B5F0109 + 0xFFFFFFFF + + + ZQ_LP2_HW_ZQINIT + no description available + 0 + 9 + read-write + + + 110111 + 112 cycles + #110111 + + + 111000 + 114 cycles + #111000 + + + 100001001 + 532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz) + #100001001 + + + 111111110 + 1022 cycles + #111111110 + + + 111111111 + 1024 cycles + #111111111 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + ZQ_LP2_HW_ZQCL + no description available + 16 + 8 + read-write + + + 110111 + 112 cycles + #110111 + + + 111000 + 114 cycles + #111000 + + + 1011111 + 192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz) + #1011111 + + + 11111110 + 510 cycles + #11111110 + + + 11111111 + 512 cycles + #11111111 + + + + + ZQ_LP2_HW_ZQCS + no description available + 24 + 7 + read-write + + + 11011 + 112 cycles (default) + #11011 + + + 11100 + 116 cycles + #11100 + + + 1111110 + 508 cycles + #1111110 + + + 1111111 + 512 cycles + #1111111 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLHWCTL + MMDC PHY Read Delay HW Calibration Control Register + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_RD_DL_ERR0 + no description available + 0 + 1 + read-only + + + 0 + No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + #0 + + + 1 + An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0. + #1 + + + + + HW_RD_DL_ERR1 + no description available + 1 + 1 + read-only + + + 0 + No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + #0 + + + 1 + An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1. + #1 + + + + + HW_RD_DL_ERR2 + no description available + 2 + 1 + read-only + + + 0 + No error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. + #0 + + + 1 + An error was found in read delay-line 2 during the automatic (HW) read calibration process of read delay-line 2. + #1 + + + + + HW_RD_DL_ERR3 + no description available + 3 + 1 + read-only + + + 0 + No error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. + #0 + + + 1 + An error was found in read delay-line 3 during the automatic (HW) read calibration process of read delay-line 3. + #1 + + + + + HW_RD_DL_EN + no description available + 4 + 1 + read-write + + + HW_RD_DL_CMP_CYC + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPWRDLHWCTL + MMDC PHY Write Delay HW Calibration Control Register + 0x864 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_WR_DL_ERR0 + no description available + 0 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 0. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 0. + #1 + + + + + HW_WR_DL_ERR1 + no description available + 1 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 1. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 1. + #1 + + + + + HW_WR_DL_ERR2 + no description available + 2 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 2. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 2. + #1 + + + + + HW_WR_DL_ERR3 + no description available + 3 + 1 + read-only + + + 0 + No error was found during the automatic (HW) write calibration process of write delay-line 3. + #0 + + + 1 + An error was found during the automatic (HW) write calibration process of write delay-line 3. + #1 + + + + + HW_WR_DL_EN + no description available + 4 + 1 + read-write + + + HW_WR_DL_CMP_CYC + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPRDDLHWST0 + MMDC PHY Read Delay HW Calibration Status Register 0 + 0x868 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_RD_DL_UP0 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_RD_DL_LOW1 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_RD_DL_UP1 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPRDDLHWST1 + MMDC PHY Read Delay HW Calibration Status Register 1 + 0x86C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_RD_DL_LOW2 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_RD_DL_UP2 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_RD_DL_LOW3 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_RD_DL_UP3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLHWST0 + MMDC PHY Write Delay HW Calibration Status Register 0 + 0x870 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW0 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_WR_DL_UP0 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_WR_DL_LOW1 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_WR_DL_UP1 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWRDLHWST1 + MMDC PHY Write Delay HW Calibration Status Register 1 + 0x874 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WR_DL_LOW2 + no description available + 0 + 7 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + HW_WR_DL_UP2 + no description available + 8 + 7 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + HW_WR_DL_LOW3 + no description available + 16 + 7 + read-only + + + RESERVED + no description available + 23 + 1 + read-only + + + HW_WR_DL_UP3 + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPWLHWERR + MMDC PHY Write Leveling HW Error Register + 0x878 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_WL0_DQ + no description available + 0 + 8 + read-only + + + HW_WL1_DQ + no description available + 8 + 8 + read-only + + + HW_WL2_DQ + no description available + 16 + 8 + read-only + + + HW_WL3_DQ + no description available + 24 + 8 + read-only + + + + + MPDGHWST0 + MMDC PHY Read DQS Gating HW Status Register 0 + 0x87C + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW0 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP0 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST1 + MMDC PHY Read DQS Gating HW Status Register 1 + 0x880 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW1 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP1 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST2 + MMDC PHY Read DQS Gating HW Status Register 2 + 0x884 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW2 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP2 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPDGHWST3 + MMDC PHY Read DQS Gating HW Status Register 3 + 0x888 + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_DG_LOW3 + no description available + 0 + 11 + read-only + + + RESERVED + no description available + 11 + 5 + read-only + + + HW_DG_UP3 + no description available + 16 + 11 + read-only + + + RESERVED + no description available + 27 + 5 + read-only + + + + + MPPDCMPR1 + MMDC PHY Pre-defined Compare Register 1 + 0x88C + 32 + read-write + 0 + 0xFFFFFFFF + + + PDV1 + no description available + 0 + 16 + read-write + + + PDV2 + no description available + 16 + 16 + read-write + + + + + MPPDCMPR2 + MMDC PHY Pre-defined Compare and CA delay-line Configuration Register + 0x890 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + MPR_CMP + no description available + 0 + 1 + read-write + + + MPR_FULL_CMP + no description available + 1 + 1 + read-write + + + READ_LEVEL_PATTERN + no description available + 2 + 1 + read-write + + + 0 + Compare with read pattern 1010 + #0 + + + 1 + Compare with read pattern 0011 (Used only in LPDDR2 mode) + #1 + + + + + RESERVED + no description available + 3 + 13 + read-only + + + CA_DL_ABS_OFFSET + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + PHY_CA_DL_UNIT + no description available + 24 + 7 + read-only + + + RESERVED + no description available + 31 + 1 + read-only + + + + + MPSWDAR0 + MMDC PHY SW Dummy Access Register + 0x894 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_DUMMY_WR + no description available + 0 + 1 + read-write + + + SW_DUMMY_RD + no description available + 1 + 1 + read-write + + + SW_DUM_CMP0 + no description available + 2 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP1 + no description available + 3 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP2 + no description available + 4 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + SW_DUM_CMP3 + no description available + 5 + 1 + read-only + + + 0 + Dummy read fail + #0 + + + 1 + Dummy read pass + #1 + + + + + RESERVED + no description available + 6 + 26 + read-only + + + + + MPSWDRDR0 + MMDC PHY SW Dummy Read Data Register 0 + 0x898 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD0 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR1 + MMDC PHY SW Dummy Read Data Register 1 + 0x89C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD1 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR2 + MMDC PHY SW Dummy Read Data Register 2 + 0x8A0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD2 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR3 + MMDC PHY SW Dummy Read Data Register 3 + 0x8A4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD3 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR4 + MMDC PHY SW Dummy Read Data Register 4 + 0x8A8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD4 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR5 + MMDC PHY SW Dummy Read Data Register 5 + 0x8AC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD5 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR6 + MMDC PHY SW Dummy Read Data Register 6 + 0x8B0 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD6 + no description available + 0 + 32 + read-only + + + + + MPSWDRDR7 + MMDC PHY SW Dummy Read Data Register 7 + 0x8B4 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + DUM_RD7 + no description available + 0 + 32 + read-only + + + + + MPMUR0 + MMDC PHY Measure Unit Register + 0x8B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MU_BYP_VAL + no description available + 0 + 10 + read-write + + + MU_BYP_EN + no description available + 10 + 1 + read-write + + + 0 + The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM. + #0 + + + 1 + The delay-lines use delay units as indicated at MU_BYPASS_VAL. + #1 + + + + + FRC_MSR + no description available + 11 + 1 + read-write + + + 0 + No measurement is performed + #0 + + + 1 + Perform measurement process + #1 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + MU_UNIT_DEL_NUM + no description available + 16 + 10 + read-only + + + RESERVED + no description available + 26 + 6 + read-only + + + + + MPWRCADL + MMDC Write CA delay-line controller + 0x8BC + 32 + read-write + 0 + 0xFFFFFFFF + + + WR_CA0_DEL + no description available + 0 + 2 + read-write + + + 00 + No change in CA0 delay + #00 + + + 01 + Add CA0 delay of 1 delay unit + #01 + + + 10 + Add CA0 delay of 2 delay units. + #10 + + + 11 + Add CA0 delay of 3 delay units. + #11 + + + + + WR_CA1_DEL + no description available + 2 + 2 + read-write + + + 00 + No change in CA1 delay + #00 + + + 01 + Add CA1 delay of 1 delay unit + #01 + + + 10 + Add CA1 delay of 2 delay units. + #10 + + + 11 + Add CA1 delay of 3 delay units. + #11 + + + + + WR_CA2_DEL + no description available + 4 + 2 + read-write + + + 00 + No change in CA2 delay + #00 + + + 01 + Add CA2 delay of 1 delay unit + #01 + + + 10 + Add CA2 delay of 2 delay units. + #10 + + + 11 + Add CA2 delay of 3 delay units. + #11 + + + + + WR_CA3_DEL + no description available + 6 + 2 + read-write + + + 00 + No change in CA3 delay + #00 + + + 01 + Add CA3 delay of 1 delay unit + #01 + + + 10 + Add CA3 delay of 2 delay units. + #10 + + + 11 + Add CA3 delay of 3 delay units. + #11 + + + + + WR_CA4_DEL + no description available + 8 + 2 + read-write + + + 00 + No change in CA4 delay + #00 + + + 01 + Add CA4 delay of 1 delay unit + #01 + + + 10 + Add CA4 delay of 2 delay units. + #10 + + + 11 + Add CA4 delay of 3 delay units. + #11 + + + + + WR_CA5_DEL + no description available + 10 + 2 + read-write + + + 00 + No change in CA5 delay + #00 + + + 01 + Add CA5 delay of 1 delay unit + #01 + + + 10 + Add CA5 delay of 2 delay units. + #10 + + + 11 + Add CA5 delay of 3 delay units. + #11 + + + + + WR_CA6_DEL + no description available + 12 + 2 + read-write + + + 00 + No change in CA6 delay + #00 + + + 01 + Add CA6 delay of 1 delay unit + #01 + + + 10 + Add CA6 delay of 2 delay units. + #10 + + + 11 + Add CA6 delay of 3 delay units. + #11 + + + + + WR_CA7_DEL + no description available + 14 + 2 + read-write + + + 00 + No change in CA7 delay + #00 + + + 01 + Add CA7 delay of 1 delay unit + #01 + + + 10 + Add CA7 delay of 2 delay units. + #10 + + + 11 + Add CA7 delay of 3 delay units. + #11 + + + + + WR_CA8_DEL + no description available + 16 + 2 + read-write + + + 00 + No change in CA8 delay + #00 + + + 01 + Add CA8 delay of 1 delay unit + #01 + + + 10 + Add CA8 delay of 2 delay units. + #10 + + + 11 + Add CA8 delay of 3 delay units. + #11 + + + + + WR_CA9_DEL + no description available + 18 + 2 + read-write + + + 00 + No change in CA9 delay + #00 + + + 01 + Add CA9 delay of 1 delay unit + #01 + + + 10 + Add CA9 delay of 2 delay units. + #10 + + + 11 + Add CA9 delay of 3 delay units. + #11 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + MPDCCR + MMDC Duty Cycle Control Register + 0x8C0 + 32 + read-only + 0x24922492 + 0xFFFFFFFF + + + WR_DQS0_FT_DCC + no description available + 0 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS1_FT_DCC + no description available + 3 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS2_FT_DCC + no description available + 6 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + WR_DQS3_FT_DCC + no description available + 9 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + CK_FT0_DCC + no description available + 12 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + CK_FT1_DCC + no description available + 16 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS0_FT_DCC + no description available + 19 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS1_FT_DCC + no description available + 22 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS2_FT_DCC + no description available + 25 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RD_DQS3_FT_DCC + no description available + 28 + 3 + read-only + + + 001 + 48.5% low 51.5% high + #001 + + + 010 + 50% duty cycle (default) + #010 + + + 100 + 51.5% low 48.5% high + #100 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + + + EIM + EIM + EIM_ + 0x21B8000 + + 0 + 0xA4 + registers + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sGCR1 + Chip Select n General Configuration Register 1 + 0 + 32 + read-write + 0x10080 + 0xFFFFFFFF + + + CSEN + no description available + 0 + 1 + read-write + + + 0 + Chip select function is disabled; attempts to access an address mapped by this chip select results in an error respond and no assertion of the chip select output + #0 + + + 1 + Chip select is enabled, and is asserted when presented with a valid access. + #1 + + + + + SWR + no description available + 1 + 1 + read-write + + + 0 + write accesses are in Asynchronous mode + #0 + + + 1 + write accesses are in Synchronous mode + #1 + + + + + SRD + no description available + 2 + 1 + read-write + + + 0 + read accesses are in Asynchronous mode + #0 + + + 1 + read accesses are in Synchronous mode + #1 + + + + + MUM + no description available + 3 + 1 + read-write + + + 0 + Multiplexed Mode disable + #0 + + + 1 + Multiplexed Mode enable + #1 + + + + + WFL + no description available + 4 + 1 + read-write + + + 0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + #0 + + + 1 + the state of the External devices is determined internally (Fix latency mode only) + #1 + + + + + RFL + no description available + 5 + 1 + read-write + + + 0 + the External device WAIT signal is being monitored, and it reflect the external data bus state + #0 + + + 1 + the state of the External devices is determined internally (Fix latency mode only) + #1 + + + + + CRE + no description available + 6 + 1 + read-write + + + 0 + CRE signal use is disable + #0 + + + 1 + CRE signal use is enable + #1 + + + + + CREP + no description available + 7 + 1 + read-write + + + 0 + CRE signal is active low + #0 + + + 1 + CRE signal is active high + #1 + + + + + BL + no description available + 8 + 3 + read-write + + + 000 + 4 words Memory wrap burst length (read page burst size when APR = 1) + #000 + + + 001 + 8 words Memory wrap burst length (read page burst size when APR = 1) + #001 + + + 010 + 16 words Memory wrap burst length (read page burst size when APR = 1) + #010 + + + 011 + 32 words Memory wrap burst length (read page burst size when APR = 1) + #011 + + + 100 + Continuous burst length (2 words read page burst size when APR = 1) + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + WC + no description available + 11 + 1 + read-write + + + 0 + Write access burst length occurs according to BL value. + #0 + + + 1 + Write access burst length is continuous. + #1 + + + + + BCD + no description available + 12 + 2 + read-write + + + 00 + Divide EIM clock by 1 + #00 + + + 01 + Divide EIM clock by 2 + #01 + + + 10 + Divide EIM clock by 3 + #10 + + + 11 + Divide EIM clock by 4 + #11 + + + + + BCS + no description available + 14 + 2 + read-write + + + 00 + 0 EIM clock cycle additional delay + #00 + + + 01 + 1 EIM clock cycle additional delay + #01 + + + 10 + 2 EIM clock cycle additional delay + #10 + + + 11 + 3 EIM clock cycle additional delay + #11 + + + + + DSZ + no description available + 16 + 3 + read-write + + + 000 + Reserved. + #000 + + + 001 + 16 bit port resides on DATA[15:0] + #001 + + + 010 + 16 bit port resides on DATA[31:16] + #010 + + + 011 + 32 bit port resides on DATA[31:0] + #011 + + + 100 + 8 bit port resides on DATA[7:0] + #100 + + + 101 + 8 bit port resides on DATA[15:8] + #101 + + + 110 + 8 bit port resides on DATA[23:16] + #110 + + + 111 + 8 bit port resides on DATA[31:24] + #111 + + + + + SP + no description available + 19 + 1 + read-write + + + 0 + User mode accesses are allowed in the memory range defined by chip select. + #0 + + + 1 + User mode accesses are prohibited. All attempts to access an address mapped by this chip select in User mode results in an error response and no assertion of the chip select output. + #1 + + + + + CSREC + no description available + 20 + 3 + read-write + + + 000 + 0 EIM clock cycles minimum width of CS, OE and WE signals (read async. mode only) + #000 + + + 001 + 1 EIM clock cycles minimum width of CS, OE and WE signals + #001 + + + 010 + 2 EIM clock cycles minimum width of CS, OE and WE signals + #010 + + + 111 + 7 EIM clock cycles minimum width of CS, OE and WE signals + #111 + + + + + AUS + no description available + 23 + 1 + read-write + + + 0 + Address shifted according to port size (DSZ config.) + #0 + + + 1 + Address unshifted + #1 + + + + + GBC + no description available + 24 + 3 + read-write + + + 000 + minimum of 0 EIM clock cycles before next access from different chip select (async. mode only) + #000 + + + 001 + minimum of 1 EIM clock cycles before next access from different chip select + #001 + + + 010 + minimum of 2 EIM clock cycles before next access from different chip select + #010 + + + 111 + minimum of 7 EIM clock cycles before next access from different chip select + #111 + + + + + WP + no description available + 27 + 1 + read-write + + + 0 + Writes are allowed in the memory range defined by chip. + #0 + + + 1 + Writes are prohibited. All attempts to write to an address mapped by this chip select result in a error response and no assertion of the chip select output. + #1 + + + + + PSZ + no description available + 28 + 4 + read-write + + + 0000 + 8 words page size + #0000 + + + 0001 + 16 words page size + #0001 + + + 0010 + 32 words page size + #0010 + + + 0011 + 64 words page size + #0011 + + + 0100 + 128 words page size + #0100 + + + 0101 + 256 words page size + #0101 + + + 0110 + 512 words page size + #0110 + + + 0111 + 1024 (1k) words page size + #0111 + + + 1000 + 2048 (2k) words page size + #1000 + + + 1001 + - 1111 Reserved + #1001 + + + + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sGCR2 + Chip Select n General Configuration Register 2 + 0x4 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + ADH + no description available + 0 + 2 + read-write + + + 00 + 0 cycle after ADV negation + #00 + + + 01 + 1 cycle after ADV negation + #01 + + + 10 + 2 cycle after ADV negation + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 2 + 2 + read-only + + + DAPS + no description available + 4 + 4 + read-write + + + 0000 + 3 EIM clk cycle between start of access and first DTACK check + #0000 + + + 0001 + 4 EIM clk cycles between start of access and first DTACK check + #0001 + + + 0010 + 5 EIM clk cycles between start of access and first DTACK check + #0010 + + + 0111 + 10 EIM clk cycles between start of access and first DTACK check + #0111 + + + 1011 + 14 EIM clk cycles between start of access and first DTACK check + #1011 + + + 1111 + 18 EIM clk cycles between start of access and first DTACK check + #1111 + + + + + DAE + no description available + 8 + 1 + read-write + + + 0 + DTACK signal use is disable + #0 + + + 1 + DTACK signal use is enable + #1 + + + + + DAP + no description available + 9 + 1 + read-write + + + 0 + DTACK signal is active high + #0 + + + 1 + DTACK signal is active low + #1 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + MUX16_BYP_GRANT + no description available + 12 + 1 + read-write + + + 0 + EIM waits for grant before driving a 16 bit muxed mode access to the memory. + #0 + + + 1 + EIM ignores the grant signal and immediately drives a 16 bit muxed mode access to the memory. + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sRCR1 + Chip Select n Read Configuration Register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RCSN + no description available + 0 + 3 + read-write + + + 000 + 0 EIM clock cycles between end of read access and CS negation + #000 + + + 001 + 1 EIM clock cycles between end of read access and CS negation + #001 + + + 010 + 2 EIM clock cycles between end of read access and CS negation + #010 + + + 111 + 7 EIM clock cycles between end of read access and CS negation + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + RCSA + no description available + 4 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of read access and CS assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of read access and CS assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of read access and CS assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of read access and CS assertion + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + OEN + no description available + 8 + 3 + read-write + + + 000 + 0 EIM clock cycles between end of access and OE negation + #000 + + + 001 + 1 EIM clock cycles between end of access and OE negation + #001 + + + 010 + 2 EIM clock cycles between end of access and OE negation + #010 + + + 111 + 7 EIM clock cycles between end of access and OE negation + #111 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + OEA + no description available + 12 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and OE assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and OE assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and OE assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of access and OE assertion + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + RADVN + no description available + 16 + 3 + read-write + + + RAL + no description available + 19 + 1 + read-write + + + RADVA + no description available + 20 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and ADV assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and ADV assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and ADV assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of access and ADV assertion + #111 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + RWSC + no description available + 24 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + RWSC value is 1 + #000001 + + + 000010 + RWSC value is 2 + #000010 + + + 111101 + RWSC value is 61 + #111101 + + + 111110 + RWSC value is 62 + #111110 + + + 111111 + RWSC value is 63 + #111111 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sRCR2 + Chip Select n Read Configuration Register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RBEN + no description available + 0 + 3 + read-write + + + 000 + 0 EIM clock cycles between end of read access and BE negation + #000 + + + 001 + 1 EIM clock cycles between end of read access and BE negation + #001 + + + 010 + 2 EIM clock cycles between end of read access and BE negation + #010 + + + 111 + 7 EIM clock cycles between end of read access and BE negation + #111 + + + + + RBE + no description available + 3 + 1 + read-write + + + 0 + - BE are disabled during read access. + #0 + + + + + RBEA + no description available + 4 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of read access and BE assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of read access and BE assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of read access and BE assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of read access and BE assertion + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + RL + no description available + 8 + 2 + read-write + + + 00 + Feedback clock loop delay is up to 1 cycle for BCD = 0 or 1.5 cycles for BCD != 0 + #00 + + + 01 + Feedback clock loop delay is up to 2 cycles for BCD = 0 or 2.5 cycles for BCD != 0 + #01 + + + 10 + Feedback clock loop delay is up to 3 cycles for BCD = 0 or 3.5 cycles for BCD != 0 + #10 + + + 11 + Feedback clock loop delay is up to 4 cycles for BCD = 0 or 4.5 cycles for BCD != 0 + #11 + + + + + RESERVED + no description available + 10 + 2 + read-only + + + PAT + no description available + 12 + 3 + read-write + + + 000 + Address width is 2 EIM clock cycles + #000 + + + 001 + Address width is 3 EIM clock cycles + #001 + + + 010 + Address width is 4 EIM clock cycles + #010 + + + 011 + Address width is 5 EIM clock cycles + #011 + + + 100 + Address width is 6 EIM clock cycles + #100 + + + 101 + Address width is 7 EIM clock cycles + #101 + + + 110 + Address width is 8 EIM clock cycles + #110 + + + 111 + Address width is 9 EIM clock cycles + #111 + + + + + APR + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sWCR1 + Chip Select n Write Configuration Register 1 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + WCSN + no description available + 0 + 3 + read-write + + + 000 + 0 EIM clock cycles between end of read access and CS negation + #000 + + + 001 + 1 EIM clock cycles between end of read access and CS negation + #001 + + + 010 + 2 EIM clock cycles between end of read access and CS negation + #010 + + + 111 + 7 EIM clock cycles between end of read access and CS negation + #111 + + + + + WCSA + no description available + 3 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of write access and CS assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of write access and CS assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of write access and CS assertion + #010 + + + 111 + 7 EIMclock cycles between beginning of write access and CS assertion + #111 + + + + + WEN + no description available + 6 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and WE assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and WE assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and WE assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of access and WE assertion + #111 + + + + + WEA + no description available + 9 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and WE assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and WE assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and WE assertion + #010 + + + 111 + 7 EIMclock cycles between beginning of access and WE assertion + #111 + + + + + WBEN + no description available + 12 + 3 + read-write + + + WBEA + no description available + 15 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and BE assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and BE assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and BE assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of access and BE assertion + #111 + + + + + WADVN + no description available + 18 + 3 + read-write + + + WADVA + no description available + 21 + 3 + read-write + + + 000 + 0 EIM clock cycles between beginning of access and ADV assertion + #000 + + + 001 + 1 EIM clock cycles between beginning of access and ADV assertion + #001 + + + 010 + 2 EIM clock cycles between beginning of access and ADV assertion + #010 + + + 111 + 7 EIM clock cycles between beginning of access and ADV assertion + #111 + + + + + WWSC + no description available + 24 + 6 + read-write + + + 000000 + Reserved + #000000 + + + 000001 + WWSC value is 1 + #000001 + + + 000010 + WWSC value is 2 + #000010 + + + 000011 + WWSC value is 3 + #000011 + + + 111111 + WWSC value is 63 + #111111 + + + + + WBED + no description available + 30 + 1 + read-write + + + WAL + no description available + 31 + 1 + read-write + + + + + 6 + 0x18 + 0,1,2,3,4,5 + CS%sWCR2 + Chip Select n Write Configuration Register 2 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WBCDD + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + WCR + EIM Configuration Register + 0x90 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + BCM + no description available + 0 + 1 + read-write + + + 0 + The burst clock runs only when accessing a chip select range with the SWR/SRD bits set. When the burst clock is not running it remains in a logic 0 state. When the burst clock is running it is configured by the BCD and BCS bit fields in the chip select Configuration Register. + #0 + + + 1 + The burst clock runs whenever ACLK is active (independent of chip select configuration) + #1 + + + + + GBCD + no description available + 1 + 2 + read-write + + + 00 + Divide EIM clock by 1 + #00 + + + 01 + Divide EIM clock by 2 + #01 + + + 10 + Divide EIM clock by 3 + #10 + + + 11 + Divide EIM clock by 4 + #11 + + + + + CONT_BCLK_SEL + Continuous BCLK select + 3 + 1 + read-write + + + 0 + BCLK When nesserary + #0 + + + 1 + BCLK Continuous + #1 + + + + + INTEN + no description available + 4 + 1 + read-write + + + 0 + External interrupt Disable + #0 + + + 1 + External interrupt Enable + #1 + + + + + INTPOL + no description available + 5 + 1 + read-write + + + 0 + External interrupt polarity is active low + #0 + + + 1 + External interrupt polarity is active high + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + WDOG_EN + no description available + 8 + 1 + read-write + + + 0 + Memory WDog is Disabled + #0 + + + 1 + Memory WDog is Enabled + #1 + + + + + WDOG_LIMIT + no description available + 9 + 2 + read-write + + + 00 + 128 BCLK cycles + #00 + + + 01 + 256 BCLK cycles + #01 + + + 10 + 512 BCLK cycles + #10 + + + 11 + 1024 BCLK cycles + #11 + + + + + FRUN_ACLK_EN + Free run ACLK enable + 11 + 1 + read-write + + + RESERVED + Reserved + 12 + 20 + read-only + + + + + DCR + DLL Control Register + 0x94 + 32 + read-write + 0x140000 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + no description available + 0 + 1 + read-write + + + DLL_CTRL_RESET + DLL Reset Bit + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + no description available + 2 + 1 + read-write + + + DLL_CTRL_SLV_OFFSET_DEC + Slave Chain Offset Decrease + 3 + 1 + read-write + + + 0 + DLL_STS_SLV_SEL = DLL_STS_REF_SEL + DLL_CTRL_SLV_OFFSET + #0 + + + 1 + DLL_STS_SLV_SEL = DLL_STS_REF_SEL - DLL_CTRL_SLV_OFFSET + #1 + + + + + DLL_CTRL_SLV_OFFSET + no description available + 4 + 3 + read-write + + + DLL_CTRL_GATE_UPDATE + no description available + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + no description available + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + no description available + 9 + 7 + read-write + + + DLL_CTRL_REF_INITIAL_VAL + no description available + 16 + 7 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + Slave DLL Update Interval + 23 + 5 + read-write + + + DLL_CTRL_REF_UPDATE_INT + Reference DLL Update Interval + 28 + 4 + read-write + + + + + DSR + DLL Status Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + no description available + 0 + 1 + read-write + + + DLL_STS_REF_LOCK + no description available + 1 + 1 + read-write + + + DLL_STS_SLV_SEL + no description available + 2 + 7 + read-write + + + DLL_STS_REF_SEL + no description available + 9 + 7 + read-write + + + RESERVED + Reserved + 16 + 16 + read-only + + + + + WIAR + EIM IP Access Register + 0x9C + 32 + read-write + 0x10 + 0xFFFFFFFF + + + IPS_REQ + no description available + 0 + 1 + read-write + + + 0 + No Master requests ips access + #0 + + + 1 + Master requests ips access + #1 + + + + + IPS_ACK + no description available + 1 + 1 + read-write + + + 0 + Master cannot access ips. + #0 + + + 1 + Master can access ips. + #1 + + + + + INT + no description available + 2 + 1 + read-write + + + ERRST + no description available + 3 + 1 + read-write + + + 0 + RDY_INT After Reset Disable + #0 + + + 1 + RDY_INT After Reset Enable + #1 + + + + + ACLK_EN + no description available + 4 + 1 + read-write + + + 0 + ACLK is disabled + #0 + + + 1 + ACLK is enabled + #1 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + EAR + Error Address Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + Error_ADDR + no description available + 0 + 32 + read-write + + + + + + + OCOTP + OCOTP Register Reference Index + OCOTP_ + 0x21BC000 + + 0 + 0x6F4 + registers + + + + CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + BUSY + no description available + 8 + 1 + read-only + + + ERROR + no description available + 9 + 1 + read-write + + + RELOAD_SHADOWS + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 2 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_UNLOCK + no description available + 16 + 16 + read-write + + + 11111001110111 + KEY + #11111001110111 + + + + + + + CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + BUSY + no description available + 8 + 1 + read-only + + + ERROR + no description available + 9 + 1 + read-write + + + RELOAD_SHADOWS + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 2 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_UNLOCK + no description available + 16 + 16 + read-write + + + 11111001110111 + KEY + #11111001110111 + + + + + + + CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + BUSY + no description available + 8 + 1 + read-only + + + ERROR + no description available + 9 + 1 + read-write + + + RELOAD_SHADOWS + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 2 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_UNLOCK + no description available + 16 + 16 + read-write + + + 11111001110111 + KEY + #11111001110111 + + + + + + + CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + BUSY + no description available + 8 + 1 + read-only + + + ERROR + no description available + 9 + 1 + read-write + + + RELOAD_SHADOWS + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 2 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + WR_UNLOCK + no description available + 16 + 16 + read-write + + + 11111001110111 + KEY + #11111001110111 + + + + + + + TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0x1461299 + 0xFFFFFFFF + + + STROBE_PROG + no description available + 0 + 12 + read-write + + + RELAX + no description available + 12 + 4 + read-write + + + STROBE_READ + no description available + 16 + 6 + read-write + + + WAIT + no description available + 22 + 6 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + SRK_REVOKE_LOCK + no description available + 1 + 1 + read-write + + + FIELD_RETURN_LOCK + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 29 + read-only + + + + + SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + no description available + 0 + 1 + read-write + + + 1 + JTAG debugging is enabled by the HAB (though this signal may be gated off) + #1 + + + + + SPARE + no description available + 1 + 30 + read-write + + + LOCK + no description available + 31 + 1 + read-write + + + + + SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + no description available + 0 + 1 + read-write + + + 1 + JTAG debugging is enabled by the HAB (though this signal may be gated off) + #1 + + + + + SPARE + no description available + 1 + 30 + read-write + + + LOCK + no description available + 31 + 1 + read-write + + + + + SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + no description available + 0 + 1 + read-write + + + 1 + JTAG debugging is enabled by the HAB (though this signal may be gated off) + #1 + + + + + SPARE + no description available + 1 + 30 + read-write + + + LOCK + no description available + 31 + 1 + read-write + + + + + SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + no description available + 0 + 1 + read-write + + + 1 + JTAG debugging is enabled by the HAB (though this signal may be gated off) + #1 + + + + + SPARE + no description available + 1 + 30 + read-write + + + LOCK + no description available + 31 + 1 + read-write + + + + + VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x2000000 + 0xFFFFFFFF + + + STEP + no description available + 0 + 16 + read-only + + + MINOR + no description available + 16 + 8 + read-only + + + MAJOR + no description available + 24 + 8 + read-only + + + + + LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + no description available + 0 + 2 + read-only + + + BOOT_CFG + no description available + 2 + 2 + read-only + + + MEM_TRIM + no description available + 4 + 2 + read-only + + + SJC_RESP + no description available + 6 + 1 + read-only + + + RESERVED + no description available + 7 + 1 + read-only + + + MAC_ADDR + no description available + 8 + 2 + read-only + + + GP1 + no description available + 10 + 2 + read-only + + + GP2 + no description available + 12 + 2 + read-only + + + SRK + no description available + 14 + 1 + read-only + + + RESERVED + no description available + 15 + 1 + read-only + + + RESERVED + no description available + 16 + 2 + read-write + + + ANALOG + no description available + 18 + 2 + read-only + + + RESERVED + no description available + 20 + 2 + read-write + + + MISC_CONF + no description available + 22 + 1 + read-only + + + RESERVED + no description available + 23 + 7 + read-only + + + UNALLOCATED + no description available + 30 + 2 + read-only + + + + + CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + ANA0 + Value of OTP Bank1 Word5 (Memory Related Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + ANA1 + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + ANA2 + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + HSJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + GP1 + Value of OTP Bank4 Word6 (HW Capabilities) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + GP2 + Value of OTP Bank4 Word7 (HW Capabilities) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + MISC_CONF + Value of OTP Bank5 Word5 (HW Capabilities) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + FIELD_RETURN + Value of OTP Bank5 Word6 (HW Capabilities) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + SRK_REVOKE + Value of OTP Bank5 Word7 (HW Capabilities) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + no description available + 0 + 32 + read-write + + + + + + + CSU + CSU Registers + CSU_ + 0x21C0000 + + 0 + 0x360 + registers + + + + 40 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39 + CSL%s + Config security level register + 0 + 32 + read-write + 0x330033 + 0xFFFFFFFF + + + SUR_S2 + no description available + 0 + 1 + read-write + + + 0 + Secure user read access disabled for the second slave. + #0 + + + 1 + Secure user read access enabled for the second slave + #1 + + + + + SSR_S2 + no description available + 1 + 1 + read-write + + + 0 + Secure supervisor read access disabled for the second slave. + #0 + + + 1 + Secure supervisor read access enabled for the second slave. + #1 + + + + + NUR_S2 + no description available + 2 + 1 + read-write + + + 0 + Non-secure user read access disabled for the second slave. + #0 + + + 1 + Non-secure user read access enabled for the second slave. + #1 + + + + + NSR_S2 + no description available + 3 + 1 + read-write + + + 0 + Non-secure supervisor read access disabled for the second slave. + #0 + + + 1 + Non-secure supervisor read access enabled for the second slave. + #1 + + + + + SUW_S2 + no description available + 4 + 1 + read-write + + + 0 + Secure user write access disabled for the second slave. + #0 + + + 1 + Secure user write access enabled for the second slave. + #1 + + + + + SSW_S2 + no description available + 5 + 1 + read-write + + + 0 + Secure supervisor write access disabled for the second slave. + #0 + + + 1 + Secure supervisor write access enabled for the second slave. + #1 + + + + + NUW_S2 + no description available + 6 + 1 + read-write + + + 0 + Non-secure user write access disabled for the second slave. + #0 + + + 1 + Non-secure user write access enabled for the second slave. + #1 + + + + + NSW_S2 + no description available + 7 + 1 + read-write + + + 0 + Non-secure supervisor write access disabled for the second slave. + #0 + + + 1 + Non-secure supervisor write access enabled for the second slave + #1 + + + + + LOCK_S2 + no description available + 8 + 1 + read-write + + + 0 + Not locked. Bits 7-0 may be written by software + #0 + + + 1 + Bits 7-0 locked and cannot be written by software + #1 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + SUR_S1 + no description available + 16 + 1 + read-write + + + 0 + Secure user read access disabled for the first slave. + #0 + + + 1 + Secure user read access enabled for the first slave + #1 + + + + + SSR_S1 + no description available + 17 + 1 + read-write + + + 0 + Secure supervisor read access disabled for the first slave. + #0 + + + 1 + Secure supervisor read access enabled for the first slave. + #1 + + + + + NUR_S1 + no description available + 18 + 1 + read-write + + + 0 + Non-secure user read access disabled for the first slave. + #0 + + + 1 + Non-secure user read access enabled for the first slave. + #1 + + + + + NSR_S1 + no description available + 19 + 1 + read-write + + + 0 + Non-secure supervisor read access disabled for the first slave. + #0 + + + 1 + Non-secure supervisor read access enabled for the first slave. + #1 + + + + + SUW_S1 + no description available + 20 + 1 + read-write + + + 0 + Secure user write access disabled for the first slave. + #0 + + + 1 + Secure user write access enabled for the first slave. + #1 + + + + + SSW_S1 + no description available + 21 + 1 + read-write + + + 0 + Secure supervisor write access disabled for the first slave. + #0 + + + 1 + Secure supervisor write access enabled for the first slave. + #1 + + + + + NUW_S1 + no description available + 22 + 1 + read-write + + + 0 + Non-secure user write access disabled for the first slave. + #0 + + + 1 + Non-secure user write access enabled for the first slave. + #1 + + + + + NSW_S1 + no description available + 23 + 1 + read-write + + + 0 + Non-secure supervisor write access disabled for the first slave. + #0 + + + 1 + Non-secure supervisor write access enabled for the first slave + #1 + + + + + LOCK_S1 + no description available + 24 + 1 + read-write + + + 0 + Not locked. Bits 16-23 may be written by software + #0 + + + 1 + Bits 16-23 locked and cannot be written by software + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + HP0 + HP0 register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_PCIE + no description available + 0 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_PCIE + no description available + 1 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_SATA + no description available + 2 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_SATA + no description available + 3 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_SDMA + no description available + 4 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_SDMA + no description available + 5 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_PU + no description available + 6 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_PU + no description available + 7 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_USB + no description available + 8 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_USB + no description available + 9 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_TEST + no description available + 10 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_TEST + no description available + 11 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_MLB + no description available + 12 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_MLB + no description available + 13 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_CAAM + no description available + 14 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_CAAM + no description available + 15 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_RAWNAND + no description available + 16 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_RAWNAND + no description available + 17 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_APBHDMA + no description available + 18 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_ABPHDMA + no description available + 19 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_ENET + no description available + 20 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_ENET + no description available + 21 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_DAP + no description available + 22 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_DAP + no description available + 23 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_USDHC1 + no description available + 24 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_USDHC1 + no description available + 25 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_USDHC2 + no description available + 26 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_USDHC2 + no description available + 27 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_USDHC3 + no description available + 28 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_USDHC3 + no description available + 29 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HP_USDHC4 + no description available + 30 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_USDHC4 + no description available + 31 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + + + HP1 + HP1 register + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_HDMI_HSI + no description available + 0 + 1 + read-write + + + 0 + User Mode for the corresponding master + #0 + + + 1 + Supervisor Mode for the corresponding master + #1 + + + + + L_HDMI_HSI + no description available + 1 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + RESERVED + no description available + 2 + 30 + read-write + + + + + SA + Secure access register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSA_CP15 + Non-Secure Access Policy indicator bit + 0 + 1 + read-write + + + 0 + ARM CP15 register is accesible + #0 + + + 1 + ARM CP15 register is not accesible + #1 + + + + + L_CP15 + no description available + 1 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_SATA + Non-Secure Access Policy indicator bit + 2 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_SATA + no description available + 3 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_SDMA + Non-Secure Access Policy indicator bit + 4 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_SDMA + no description available + 5 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_PU + Non-Secure Access Policy indicator bit + 6 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_PU + no description available + 7 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_USB_MLB + Non-Secure Access Policy indicator bit + 8 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_USB_MLB + no description available + 9 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_PCIE_TEST + Non-Secure Access Policy indicator bit + 10 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_PCIE_TEST + no description available + 11 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + RESERVED + no description available + 12 + 2 + read-write + + + NSA_RAWNAND_APBHDMA + Non-Secure Access Policy indicator bit + 14 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_RAWNAND_APBHDMA + no description available + 15 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_ENET + Non-Secure Access Policy indicator bit + 16 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_ENET + no description available + 17 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_DAP + Non-Secure Access Policy indicator bit ARM core platform DAP + 18 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_DAP + no description available + 19 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_USDHC1 + Non-Secure Access Policy indicator bit + 20 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_USDHC1 + no description available + 21 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_USDHC2 + Non-Secure Access Policy indicator bit + 22 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_USDHC2 + no description available + 23 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_USDHC3 + Non-Secure Access Policy indicator bit + 24 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_USDHC3 + no description available + 25 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_USDHC4 + Non-Secure Access Policy indicator bit + 26 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_USDHC4 + no description available + 27 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + NSA_HDMI_HSI + Non-Secure Access Policy indicator bit + 28 + 1 + read-write + + + 0 + Secure access for the corresponding Type 1 master + #0 + + + 1 + Non-secure access for the corresponding Type 1 master + #1 + + + + + L_HDMI_HSI + no description available + 29 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + RESERVED + no description available + 30 + 2 + read-write + + + + + HPCONTROL0 + HPCONTROL0 register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_PCIE + no description available + 0 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_PCIE + no description available + 1 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_SATA + no description available + 2 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_SATA + no description available + 3 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_SDMA + no description available + 4 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_SDMA + no description available + 5 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_PU + no description available + 6 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_PU + no description available + 7 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_USB + no description available + 8 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_USB + no description available + 9 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_TEST + no description available + 10 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_TEST + no description available + 11 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_MLB + no description available + 12 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_MLB + no description available + 13 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_CAAM + no description available + 14 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_CAAM + no description available + 15 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_RAWNAND + no description available + 16 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_RAWNAND + no description available + 17 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_APBHDMA + no description available + 18 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_ABPHDMA + no description available + 19 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_ENET + no description available + 20 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_ENET + no description available + 21 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_DAP + no description available + 22 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_DAP + no description available + 23 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_USDHC1 + no description available + 24 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_USDHC1 + no description available + 25 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_USDHC2 + no description available + 26 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_USDHC2 + no description available + 27 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_USDHC3 + no description available + 28 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_USDHC3 + no description available + 29 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + HPC_USDHC4 + no description available + 30 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_USDHC4 + no description available + 31 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + + + HPCONTROL1 + HPCONTROL1 register + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_HDMI_HSI + no description available + 0 + 1 + read-write + + + 0 + Input signal hprot1 value is routed to csu_hprot1 output for the corresponding master + #0 + + + 1 + HP register bit is routed to csu_hprot1 output for the corresponding master + #1 + + + + + L_HDMI_HSI + no description available + 1 + 1 + read-write + + + 0 + No lock -- adjacent (next lower) bit can be written by software + #0 + + + 1 + Lock -- adjacent (next lower) bit cannot be written by software + #1 + + + + + RESERVED + no description available + 2 + 30 + read-write + + + + + + + AUDMUX + AUDMUX Registers + AUDMUX_ + 0x21D8000 + + 0 + 0x38 + registers + + + + PTCR1 + Port Timing Control Register 1 + 0 + 32 + read-write + 0xAD400800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR1 + Port Data Control Register 1 + 0x4 + 32 + read-write + 0xA000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR2 + Port Timing Control Register 2 + 0x8 + 32 + read-write + 0xA5000800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR2 + Port Data Control Register 2 + 0xC + 32 + read-write + 0x8000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR3 + Port Timing Control Register 3 + 0x10 + 32 + read-write + 0x9CC00800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR3 + Port Data Control Register 3 + 0x14 + 32 + read-write + 0x6000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR4 + Port Timing Control Register 4 + 0x18 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR4 + Port Data Control Register 4 + 0x1C + 32 + read-write + 0x4000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR5 + Port Timing Control Register 5 + 0x20 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR5 + Port Data Control Register 5 + 0x24 + 32 + read-write + 0x2000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR6 + Port Timing Control Register 6 + 0x28 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR6 + Port Data Control Register 6 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + PTCR7 + Port Timing Control Register 7 + 0x30 + 32 + read-write + 0x800 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 11 + read-only + + + SYN + no description available + 11 + 1 + read-write + + + 0 + Asynchronous mode + #0 + + + 1 + Synchronous mode (default) + #1 + + + + + RCSEL + no description available + 12 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RCLKDIR + no description available + 16 + 1 + read-write + + + 0 + RXC is an input. + #0 + + + 1 + RXC is an output. + #1 + + + + + RFSEL + no description available + 17 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + RFS_DIR + no description available + 21 + 1 + read-write + + + 0 + RXFS is an input. + #0 + + + 1 + RXFS is an output. + #1 + + + + + TCSEL + no description available + 22 + 4 + read-write + + + 1xxx + Selects RXC from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TCLKDIR + no description available + 26 + 1 + read-write + + + 0 + TXC is an input. + #0 + + + 1 + TXC is an output. + #1 + + + + + TFSEL + no description available + 27 + 4 + read-write + + + 1xxx + Selects RXFS from port. + #1xxx + + + x000 + Port 1 + #x000 + + + x110 + Port 7 + #x110 + + + x111 + Reserved + #x111 + + + + + TFS_DIR + no description available + 31 + 1 + read-write + + + 0 + TXFS is an input. + #0 + + + 1 + TXFS is an output. + #1 + + + + + + + PDCR7 + Port Data Control Register 7 + 0x34 + 32 + read-write + 0xC000 + 0xFFFFFFFF + + + INMMASK + no description available + 0 + 8 + read-write + + + 0 + Includes RXDn for ANDing + #0 + + + 1 + Excludes RXDn from ANDing + #1 + + + + + MODE + no description available + 8 + 1 + read-write + + + 0 + Normal mode + #0 + + + 1 + Internal Network mode + #1 + + + + + RESERVED + no description available + 9 + 3 + read-only + + + TXRXEN + no description available + 12 + 1 + read-write + + + 0 + No switch (Transmit Pin = Transmit, Receive Pin = Receive) + #0 + + + 1 + Switch (Transmit Pin = Receive, Receive Pin = Transmit) + #1 + + + + + RXDSEL + no description available + 13 + 3 + read-write + + + xxx + Port number for RXD + #xxx + + + 000 + Port 1 + #000 + + + 110 + Port 7 + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + + + CSI2IPU + CSI2IPU + CSI2IPU_ + 0x21DC000 + + 0xF00 + 0x4 + registers + + + + SW_RST + CSI 2 IPU Gasket Software Reset + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + no description available + 0 + 1 + read-write + + + 0 + Software Reset Disable + #0 + + + 1 + Software Reset Enable + #1 + + + + + CLK_SEL + no description available + 1 + 1 + read-write + + + 0 + Gated Mode + #0 + + + 1 + Non-Gated Mode + #1 + + + + + YUV422_8BIT_FM + no description available + 2 + 1 + read-write + + + 0 + YUYV + #0 + + + 1 + UYVY + #1 + + + + + RGB444_FM + no description available + 3 + 1 + read-write + + + 0 + {4'h0,r4b4g4} + #0 + + + 1 + {r4,1'b0,g4,2'b00,b4,1'b0} + #1 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + + + MIPI_CSI + MIPI_CSI + MIPI_CSI_ + 0x21DC000 + + 0 + 0x38 + registers + + + + VERSION + Controller Version Identification Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + VERSION + no description available + 0 + 32 + read-only + + + + + N_LANES + Number of Active Data Lanes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + N_LANES + no description available + 0 + 1 + read-write + + + 0 + 1 Data Lane (Lane 0) + #0 + + + 1 + 2 Data Lanes (Lane 0, and 1) + #1 + + + + + RESERVED + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 30 + read-only + + + + + PHY_SHUTDOWNZ + Phy shutdown control + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PHY_SHUTDOWNZ + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + DPHY_RSTZ + Phy reset control + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + DPHY_RSTZ + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CSI2_RESETN + CSI2 controller reset + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI2_RESETN + no description available + 0 + 1 + read-write + + + RESERVED + no description available + 1 + 31 + read-only + + + + + PHY_STATE + General settings for all blocks + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_rxulpsesc_0 + no description available + 0 + 1 + read-only + + + phy_rxulpsesc_1 + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + phy_stopstatedata_0 + no description available + 4 + 1 + read-only + + + phy_stopstatedata_1 + no description available + 5 + 1 + read-only + + + RESERVED + no description available + 6 + 2 + read-only + + + phy_rxclkactivehs + no description available + 8 + 1 + read-only + + + phy_rxulpsclknot + no description available + 9 + 1 + read-only + + + phy_stopstateclk + no description available + 10 + 1 + read-only + + + bypass_2ecc_tst + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + DATA_IDS_1 + Data IDs for which IDI reports line boundary matching errors + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_dt + no description available + 0 + 6 + read-write + + + di0_vc + no description available + 6 + 2 + read-write + + + di1_dt + no description available + 8 + 6 + read-write + + + di1_vc + no description available + 14 + 2 + read-write + + + di2_dt + no description available + 16 + 6 + read-write + + + di2_vc + no description available + 22 + 2 + read-write + + + di3_dt + no description available + 24 + 6 + read-write + + + di3_vc + no description available + 30 + 2 + read-write + + + + + ERR1 + Error state register 1 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + phy_errsotsynchs_0 + no description available + 0 + 1 + read-only + + + phy_errsotsynchs_1 + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + err_f_bndry_match_vc0 + no description available + 4 + 1 + read-only + + + err_f_bndry_match_vc1 + no description available + 5 + 1 + read-only + + + err_f_bndry_match_vc2 + no description available + 6 + 1 + read-only + + + err_f_bndry_match_vc3 + no description available + 7 + 1 + read-only + + + err_f_seq_vc0 + no description available + 8 + 1 + read-only + + + err_f_seq_vc1 + no description available + 9 + 1 + read-only + + + err_f_seq_vc2 + no description available + 10 + 1 + read-only + + + err_f_seq_vc3 + no description available + 11 + 1 + read-only + + + err_frame_data_vc0 + no description available + 12 + 1 + read-only + + + err_frame_data_vc1 + no description available + 13 + 1 + read-only + + + err_frame_data_vc2 + no description available + 14 + 1 + read-only + + + err_frame_data_vc3 + no description available + 15 + 1 + read-only + + + err_l_bndry_match_di0 + no description available + 16 + 1 + read-only + + + err_l_bndry_match_di1 + no description available + 17 + 1 + read-only + + + err_l_bndry_match_di2 + no description available + 18 + 1 + read-only + + + err_l_bndry_match_di3 + no description available + 19 + 1 + read-only + + + err_l_seq_di0 + no description available + 20 + 1 + read-only + + + err_l_seq_di1 + no description available + 21 + 1 + read-only + + + err_l_seq_di2 + no description available + 22 + 1 + read-only + + + err_l_seq_di3 + no description available + 23 + 1 + read-only + + + vc0_err_crc + no description available + 24 + 1 + read-only + + + vc1_err_crc + no description available + 25 + 1 + read-only + + + vc2_err_crc + no description available + 26 + 1 + read-only + + + vc3_err_crc + no description available + 27 + 1 + read-only + + + err_ecc_double + no description available + 28 + 1 + read-only + + + RESERVED + no description available + 29 + 3 + read-only + + + + + ERR2 + Error state register 2 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + phy_erresc_0 + no description available + 0 + 1 + read-only + + + phy_erresc_1 + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 2 + read-only + + + phy_errsoths_0 + no description available + 4 + 1 + read-only + + + phy_errsoths_1 + no description available + 5 + 1 + read-only + + + RESERVED + no description available + 6 + 2 + read-only + + + vc0_err_ecc_corrected + no description available + 8 + 1 + read-only + + + vc1_err_ecc_corrected + no description available + 9 + 1 + read-only + + + vc2_err_ecc_corrected + no description available + 10 + 1 + read-only + + + vc3_err_ecc_corrected + no description available + 11 + 1 + read-only + + + err_id_vc0 + no description available + 12 + 1 + read-only + + + err_id_vc1 + no description available + 13 + 1 + read-only + + + err_id_vc2 + no description available + 14 + 1 + read-only + + + err_id_vc3 + no description available + 15 + 1 + read-only + + + RESERVED + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + MASK2 + Masks for errors 2 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + mask_phy_erresc_0 + no description available + 0 + 1 + read-write + + + mask_phy_erresc_1 + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 2 + read-only + + + mask_phy_errsoths_0 + no description available + 4 + 1 + read-write + + + mask_phy_errsoths_1 + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 2 + read-only + + + mask_vc0_err_ecc_corrected + no description available + 8 + 1 + read-write + + + mask_vc1_err_ecc_corrected + no description available + 9 + 1 + read-write + + + mask_vc2_err_ecc_corrected + no description available + 10 + 1 + read-write + + + mask_vc3_err_ecc_corrected + no description available + 11 + 1 + read-write + + + mask_err_id_vc0 + no description available + 12 + 1 + read-write + + + mask_err_id_vc1 + no description available + 13 + 1 + read-write + + + mask_err_id_vc2 + no description available + 14 + 1 + read-write + + + mask_err_id_vc3 + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + RESERVED + no description available + 24 + 8 + read-only + + + + + PHY_TST_CRTL0 + D-PHY Test interface control 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_testclr + no description available + 0 + 1 + read-write + + + phy_testclk + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 30 + read-only + + + + + PHY_TST_CTRL1 + D-PHY Test interface control 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_testdin + no description available + 0 + 8 + read-write + + + phy_testdout + no description available + 8 + 8 + read-write + + + phy_testen + no description available + 16 + 1 + read-write + + + 1 + configures address write operation on the falling edge of TESTCLK + #1 + + + 0 + configures a data write operation on the rising edge of TESTCLK + #0 + + + + + RESERVED + no description available + 17 + 15 + read-only + + + + + + + MIPI_DSI + MIPI_DSI + MIPI_DSI_ + 0x21E0000 + + 0 + 0x6C + registers + + + + VERSION + Version of the DSI host ctrl + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + version + no description available + 0 + 32 + read-only + + + + + PWR_UP + Core power up + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + shutdownz + no description available + 0 + 1 + read-write + + + 0 + reset; + #0 + + + 1 + power up) + #1 + + + + + RESERVED + no description available + 1 + 31 + read-only + + + + + CLKMGR_CFG + Number of active data lanes + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ESC_CLK_DIVIDSION + no description available + 0 + 8 + read-write + + + TO_CLK_DIVIDSION + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DPI_CFG + DPI interface configuration + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + dpi_vid + no description available + 0 + 2 + read-write + + + dpi_color_coding + no description available + 2 + 3 + read-write + + + 0 + 16bit config1 + #0 + + + 1 + 16bit config2; + #1 + + + + + dataen_active_low + no description available + 5 + 1 + read-write + + + vsync_active_low + no description available + 6 + 1 + read-write + + + hsync_active_low + no description available + 7 + 1 + read-write + + + shutd_active_low + no description available + 8 + 1 + read-write + + + colorm_active_low + no description available + 9 + 1 + read-write + + + en18_loosely + no description available + 10 + 1 + read-write + + + RESERVED + no description available + 11 + 21 + read-only + + + + + DBI_CFG + DBI interface configuration + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + dbi_vid + no description available + 0 + 2 + read-write + + + in_dbi_conf + no description available + 2 + 4 + read-write + + + 0 + 8bit 8bpp; + #0 + + + 1 + 8bit 12bpp; + #1 + + + 10 + 16bit 18bpp, option2; + #10 + + + 11 + 16bit 24bpp, option1; + #11 + + + + + lut_size_conf + no description available + 6 + 2 + read-write + + + 0 + 16-bit color display; + #0 + + + 1 + 18-bit color display; + #1 + + + + + partitioning_en + no description available + 8 + 1 + read-write + + + out_dbi_conf + no description available + 9 + 4 + read-write + + + 0 + 8bit 8bpp; + #0 + + + 1 + 8bit 12bpp; + #1 + + + 10 + 16bit 18bpp, option2; + #10 + + + 11 + 16bit 24bpp, option1; + #11 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + DBIS_CMDSIZE + DBI command size configuration + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + wr_cmd_size + no description available + 0 + 16 + read-write + + + allowed_cmd_size + no description available + 16 + 16 + read-write + + + + + PCKHDL_CFG + Packet handler configuration + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + en_EOTp_tx + no description available + 0 + 1 + read-write + + + en_EOTn_rx + no description available + 1 + 1 + read-write + + + en_BTA + no description available + 2 + 1 + read-write + + + en_ECC_rx + no description available + 3 + 1 + read-write + + + en_CRC_rx + no description available + 4 + 1 + read-write + + + gen_vid_rx + no description available + 5 + 2 + read-write + + + RESERVED + no description available + 7 + 25 + read-only + + + + + VID_MODE_CFG + Video Mode Configuration + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + en_video_mode + no description available + 0 + 1 + read-write + + + vid_mode_type + no description available + 1 + 2 + read-write + + + en_lp_vsa + no description available + 3 + 1 + read-write + + + en_lp_vbp + no description available + 4 + 1 + read-write + + + en_lp_vfp + no description available + 5 + 1 + read-write + + + en_lp_vact + no description available + 6 + 1 + read-write + + + en_lp_hbp + no description available + 7 + 1 + read-write + + + en_lp_hfp + no description available + 8 + 1 + read-write + + + en_multi_pkt + no description available + 9 + 1 + read-write + + + en_null_pkt + no description available + 10 + 1 + read-write + + + frame_BTA_ack + no description available + 11 + 1 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + VID_PKT_CFG + Video packet configuration + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + vid_pkt_size + no description available + 0 + 11 + read-write + + + num_chunks + no description available + 11 + 10 + read-write + + + null_pkt_size + no description available + 21 + 10 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + CMD_MODE_CFG + Command mode configuration + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + en_cmd_mode + no description available + 0 + 1 + read-write + + + gen_sw_0p_tx + no description available + 1 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_sw_1p_tx + no description available + 2 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_sw_2p_tx + no description available + 3 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_sr_0p_tx + no description available + 4 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_sr_1p_tx + no description available + 5 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_sr_2p_tx + no description available + 6 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + dcs_sw_0p_tx + no description available + 7 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + dcs_sw_1p_tx + no description available + 8 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + dcs_sw_2p_tx + no description available + 9 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + max_rd_pkt_size + no description available + 10 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + gen_lw_tx + no description available + 11 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + dcs_lw_tx + no description available + 12 + 1 + read-write + + + 0 + High Speed; + #0 + + + 1 + Low Power + #1 + + + + + en_ack_rqst + no description available + 13 + 1 + read-write + + + en_tear_fx + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 17 + read-only + + + + + TMR_LINE_CFG + Line timer configuration + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + hsa_time + no description available + 0 + 9 + read-write + + + hbp_time + no description available + 9 + 9 + read-write + + + hline_time + no description available + 18 + 14 + read-write + + + + + VTIMING_CFG + Vertical timing configuration + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + vsa_lines + no description available + 0 + 4 + read-write + + + vbp_lines + no description available + 4 + 6 + read-write + + + vfp_lines + no description available + 10 + 6 + read-write + + + v_active_lines + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + PHY_TMR_CFG + D-PHY timing configuration + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + bta_time + no description available + 0 + 12 + read-write + + + phy_lp2hs_time + no description available + 12 + 8 + read-write + + + phy_hs2lp_time + no description available + 20 + 8 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + GEN_HDR + Generic packet Header configuration + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + gen_htype + no description available + 0 + 8 + read-write + + + gen_hdata + no description available + 8 + 16 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + GEN_PLD_DATA + Generic payload data in/out + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + gen_pld_data + no description available + 0 + 32 + read-write + + + + + CMD_PKT_STATUS + Command packet status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + gen_cmd_empty + no description available + 0 + 1 + read-write + + + gen_cmd_full + no description available + 1 + 1 + read-write + + + gen_pld_w_empty + no description available + 2 + 1 + read-write + + + gen_pld_w_full + no description available + 3 + 1 + read-write + + + gen_pld_r_empty + no description available + 4 + 1 + read-write + + + gen_pld_r_full + no description available + 5 + 1 + read-write + + + gen_rd_cmd_busy + no description available + 6 + 1 + read-write + + + RESERVED + no description available + 7 + 1 + read-write + + + dbi_cmd_empty + no description available + 8 + 1 + read-write + + + dbi_cmd_full + no description available + 9 + 1 + read-write + + + dbi_pld_w_empty + no description available + 10 + 1 + read-write + + + dbi_pld_w_full + no description available + 11 + 1 + read-write + + + dbi_pld_r_empty + no description available + 12 + 1 + read-write + + + dbi_pld_r_full + no description available + 13 + 1 + read-write + + + dbi_rd_cmd_busy + no description available + 14 + 1 + read-write + + + RESERVED + no description available + 15 + 1 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + TO_CNT_CFG0 + Time Out timers configuration + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + hstx_to_cnt + no description available + 0 + 16 + read-write + + + lprx_to_cnt + no description available + 16 + 16 + read-write + + + + + ERROR_ST0 + Interrupt status register 0 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + ack_with_err_0 + no description available + 0 + 1 + read-write + + + ack_with_err_1 + no description available + 1 + 1 + read-write + + + ack_with_err_2 + no description available + 2 + 1 + read-write + + + ack_with_err_3 + no description available + 3 + 1 + read-write + + + ack_with_err_4 + no description available + 4 + 1 + read-write + + + ack_with_err_5 + no description available + 5 + 1 + read-write + + + ack_with_err_6 + no description available + 6 + 1 + read-write + + + ack_with_err_7 + no description available + 7 + 1 + read-write + + + ack_with_err_8 + no description available + 8 + 1 + read-write + + + ack_with_err_9 + no description available + 9 + 1 + read-write + + + ack_with_err_10 + no description available + 10 + 1 + read-write + + + ack_with_err_11 + no description available + 11 + 1 + read-write + + + ack_with_err_12 + no description available + 12 + 1 + read-write + + + ack_with_err_13 + no description available + 13 + 1 + read-write + + + ack_with_err_14 + no description available + 14 + 1 + read-write + + + ack_with_err_15 + no description available + 15 + 1 + read-write + + + dphy_errors_0 + no description available + 16 + 1 + read-write + + + dphy_errors_1 + no description available + 17 + 1 + read-write + + + dphy_errors_2 + no description available + 18 + 1 + read-write + + + dphy_errors_3 + no description available + 19 + 1 + read-write + + + dphy_errors_4 + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + ERROR_ST1 + Interrupt status register 1 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + to_hs_tx + no description available + 0 + 1 + read-write + + + to_lp_rx + no description available + 1 + 1 + read-write + + + ecc_sinlge_err + no description available + 2 + 1 + read-write + + + ecc_multi_err + no description available + 3 + 1 + read-write + + + crc_err + no description available + 4 + 1 + read-write + + + pkt_size_err + no description available + 5 + 1 + read-write + + + eopt_err + no description available + 6 + 1 + read-write + + + dpi_pld_wr_err + no description available + 7 + 1 + read-write + + + gen_cmd_wr_err + no description available + 8 + 1 + read-write + + + gen_pld_wr_err + no description available + 9 + 1 + read-write + + + gen_pld_send_err + no description available + 10 + 1 + read-write + + + gen_pld_rd_err + no description available + 11 + 1 + read-write + + + gen_pld_recv_err + no description available + 12 + 1 + read-write + + + dbi_cmd_wr_err + no description available + 13 + 1 + read-write + + + dbi_pld_wr_err + no description available + 14 + 1 + read-write + + + dbi_pld_rd_err + no description available + 15 + 1 + read-write + + + dbi_pld_recv_err + no description available + 16 + 1 + read-write + + + dbi_illegal_comm_err + no description available + 17 + 1 + read-write + + + RESERVED + no description available + 18 + 14 + read-only + + + + + ERROR_MSK0 + Masks Interrupt generation trigged by ERROR_ST0 register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ack_with_err_0 + no description available + 0 + 1 + read-write + + + ack_with_err_1 + no description available + 1 + 1 + read-write + + + ack_with_err_2 + no description available + 2 + 1 + read-write + + + ack_with_err_3 + no description available + 3 + 1 + read-write + + + ack_with_err_4 + no description available + 4 + 1 + read-write + + + ack_with_err_5 + no description available + 5 + 1 + read-write + + + ack_with_err_6 + no description available + 6 + 1 + read-write + + + ack_with_err_7 + no description available + 7 + 1 + read-write + + + ack_with_err_8 + no description available + 8 + 1 + read-write + + + ack_with_err_9 + no description available + 9 + 1 + read-write + + + ack_with_err_10 + no description available + 10 + 1 + read-write + + + ack_with_err_11 + no description available + 11 + 1 + read-write + + + ack_with_err_12 + no description available + 12 + 1 + read-write + + + ack_with_err_13 + no description available + 13 + 1 + read-write + + + ack_with_err_14 + no description available + 14 + 1 + read-write + + + ack_with_err_15 + no description available + 15 + 1 + read-write + + + dphy_errors_0 + no description available + 16 + 1 + read-write + + + dphy_errors_1 + no description available + 17 + 1 + read-write + + + dphy_errors_2 + no description available + 18 + 1 + read-write + + + dphy_errors_3 + no description available + 19 + 1 + read-write + + + dphy_errors_4 + no description available + 20 + 1 + read-write + + + RESERVED + no description available + 21 + 11 + read-only + + + + + ERROR_MSK1 + Masks Interrupt generation trigged by ERROR_ST1 register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + to_hs_tx + no description available + 0 + 1 + read-write + + + to_lp_rx + no description available + 1 + 1 + read-write + + + ecc_sinlge_err + no description available + 2 + 1 + read-write + + + ecc_multi_err + no description available + 3 + 1 + read-write + + + crc_err + no description available + 4 + 1 + read-write + + + pkt_size_err + no description available + 5 + 1 + read-write + + + eopt_err + no description available + 6 + 1 + read-write + + + dpi_pld_wr_err + no description available + 7 + 1 + read-write + + + gen_cmd_wr_err + no description available + 8 + 1 + read-write + + + gen_pld_wr_err + no description available + 9 + 1 + read-write + + + gen_pld_send_err + no description available + 10 + 1 + read-write + + + gen_pld_rd_err + no description available + 11 + 1 + read-write + + + gen_pld_recv_err + no description available + 12 + 1 + read-write + + + dbi_cmd_wr_err + no description available + 13 + 1 + read-write + + + dbi_pld_wr_err + no description available + 14 + 1 + read-write + + + dbi_pld_rd_err + no description available + 15 + 1 + read-write + + + dbi_pld_recv_err + no description available + 16 + 1 + read-write + + + dbi_illegal_comm_err + no description available + 17 + 1 + read-write + + + RESERVED + no description available + 18 + 14 + read-only + + + + + PHY_RSTZ + D-PHY reset control + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_shutdownz + no description available + 0 + 1 + read-write + + + phy_rstz + no description available + 1 + 1 + read-write + + + phy_enableclk + no description available + 2 + 1 + read-write + + + RESERVED + no description available + 3 + 29 + read-only + + + + + PHY_IF_CFG_ + D-PHY interface configuration + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + n_lanes + no description available + 0 + 2 + read-write + + + 00 + 1 Data Lane (Lane 0) + #00 + + + 01 + 2 Data Lanes (Lane 0, and Lane 1) + #01 + + + 10 + Reserved + #10 + + + 11 + Reserved + #11 + + + + + phy_stop_wait_time + no description available + 2 + 8 + read-write + + + RESERVED + no description available + 10 + 22 + read-only + + + + + PHY_IF_CTRL + D-PHY PPI interface control + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_txrequestclkhs + no description available + 0 + 1 + read-write + + + phy_txrequlpsclk + no description available + 1 + 1 + read-write + + + phy_txexitulpsclk + no description available + 2 + 1 + read-write + + + phy_txrequlpslan + no description available + 3 + 1 + read-write + + + phy_txexitulpslan + no description available + 4 + 1 + read-write + + + phy_tx_triggers + no description available + 5 + 4 + read-write + + + RESERVED + no description available + 9 + 23 + read-only + + + + + PHY_STATUS + D-PHY PPI status interface + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + phylock + no description available + 0 + 1 + read-write + + + phydirection + no description available + 1 + 1 + read-write + + + phystopstateclklane + no description available + 2 + 1 + read-write + + + phyrxulpsclknot + no description available + 3 + 1 + read-write + + + phystopstate0lane + no description available + 4 + 1 + read-write + + + ulpsactivenot0lane + no description available + 5 + 1 + read-write + + + rxulpsesc0lane + no description available + 6 + 1 + read-write + + + phystopstate1lane + no description available + 7 + 1 + read-write + + + ulpsactivenot1lane + no description available + 8 + 1 + read-write + + + phystopstate2lane + no description available + 9 + 1 + read-write + + + ulpsactivenot2lane + no description available + 10 + 1 + read-write + + + phystopstate3lane + no description available + 11 + 1 + read-write + + + ulpsactivenot3lane + no description available + 12 + 1 + read-write + + + RESERVED + no description available + 13 + 19 + read-only + + + + + PHY_TST_CTRL0 + D-PHY Test interface control 0 + 0x64 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + phy_testclr + no description available + 0 + 1 + read-write + + + phy_testclk + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 30 + read-only + + + + + PHY_TST_CTRL1 + D-PHY Test interface control 1 + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + phy_testdin + no description available + 0 + 8 + read-write + + + phy_testdout + no description available + 8 + 8 + read-write + + + phy_testen + no description available + 16 + 1 + read-write + + + RESERVED + no description available + 17 + 15 + read-only + + + + + + + VDOA + VDOA + VDOA_ + 0x21E4000 + + 0 + 0x48 + registers + + + + VDOAC + VDOA Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BNDM + no description available + 0 + 2 + read-write + + + 00 + BAND_HEIGHT_8 + #00 + + + 01 + BAND_HEIGHT_16 + #01 + + + 10 + BAND_HEIGHT_32 + #10 + + + 11 + reserved + #11 + + + + + NF + no description available + 2 + 1 + read-write + + + 0 + 1_FRAME + #0 + + + 1 + 3_FRAMES + #1 + + + + + SYNC + no description available + 3 + 1 + read-write + + + 0 + NO_SYNC_MODE + #0 + + + 1 + SYNC_MODE + #1 + + + + + SO + no description available + 4 + 1 + read-write + + + 0 + PROGRESSIVE + #0 + + + 1 + INTERLACED + #1 + + + + + PFS + no description available + 5 + 1 + read-write + + + 0 + 4_2_0 + #0 + + + 1 + 4_2_2 + #1 + + + + + ISEL + no description available + 6 + 1 + read-write + + + 0 + vdoa_buf_rdy_and_ipu_buf_eob_0 + #0 + + + 1 + vdoa_buf_rdy_and_ipu_buf_eob_1 + #1 + + + + + RESERVED + no description available + 7 + 25 + read-only + + + + + VDOASRR + VDOA Start and Reset + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SWRST + no description available + 0 + 1 + read-write + + + Start + no description available + 1 + 1 + read-write + + + 0 + Ignored + #0 + + + 1 + START_TRANSFER + #1 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + VDOAIE + VDOA Interrupt Enable Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + EIEOT + no description available + 0 + 1 + read-write + + + 0 + IRQ_DISABLED + #0 + + + 1 + IRQ_ENABLED + #1 + + + + + EITERR + no description available + 1 + 1 + read-write + + + 0 + IRQ_DISABLED + #0 + + + 1 + IRQ_ENABLED + #1 + + + + + RESERVED + no description available + 2 + 30 + read-only + + + + + VDOAIST + VDOA Interrupt Status Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + EOT + no description available + 0 + 1 + read-write + + + TERR + no description available + 1 + 1 + read-write + + + RESERVED + no description available + 2 + 30 + read-only + + + + + VDOAFP + VDOA Frame Parameters Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + FW + no description available + 0 + 14 + read-write + + + RESERVED + no description available + 14 + 2 + read-only + + + FH + no description available + 16 + 13 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + VDOAIEBA00 + VDOA IPU External Buffer 0 Frame 0 Address Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA00 + no description available + 0 + 32 + read-write + + + + + VDOAIEBA01 + VDOA IPU External Buffer 0 Frame 1 Address Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA01 + no description available + 0 + 32 + read-write + + + + + VDOAIEBA02 + VDOA IPU External Buffer 0 Frame 2 Address Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA02 + no description available + 0 + 32 + read-write + + + + + VDOAIEBA10 + VDOA IPU External Buffer 1 Frame 0 Address Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA10 + no description available + 0 + 32 + read-write + + + + + VDOAIEBA11 + VDOA IPU External Buffer 1 Frame 1 Address Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA11 + no description available + 0 + 32 + read-write + + + + + VDOAIEBA12 + VDOA IPU External Buffer 1 Frame 2 Address Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IEBA12 + no description available + 0 + 32 + read-write + + + + + VDOASL + VDOA IPU Stride Line Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ISLY + no description available + 0 + 15 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + VSLY + no description available + 16 + 14 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + VDOAIUBO + VDOA IPU U (Chroma) Buffer Offset Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + IUBO + no description available + 0 + 27 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDOAVEBA0 + VDOA VPU External Buffer 0 Address Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + VEBA0 + no description available + 0 + 32 + read-write + + + + + VDOAVEBA1 + VDOA VPU External Buffer 1 Address Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + VEBA1 + no description available + 0 + 32 + read-write + + + + + VDOAVEBA2 + VDOA VPU External Buffer 2 Address Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + VEBA2 + no description available + 0 + 32 + read-write + + + + + VDOAVUBO + VDOA VPU U (Chroma) Buffer Offset Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + VUBO + no description available + 0 + 27 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDOASR + VDOA Status Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + Current_Buffer + no description available + 0 + 1 + read-only + + + CURRENT_FRAME + no description available + 1 + 2 + read-only + + + EOB + no description available + 3 + 1 + read-only + + + ERRW + no description available + 4 + 1 + read-only + + + 0 + READ_ERROR + #0 + + + 1 + WRITE_ERROR + #1 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + + + MIPI_HSI + MIPI HSI Registers + MIPI_HSI_ + 0x2208000 + + 0 + 0x230 + registers + + + + CTRL + HSI Control Register + 0 + 32 + read-write + 0xC8000000 + 0xFFFFFFFF + + + TX_CLK_DIVISOR + no description available + 0 + 4 + read-write + + + 1000 + tx_refclk divided by 256 + #1000 + + + 0111 + tx_refclk divided by 128 + #0111 + + + 0110 + tx_refclk divided by 64 + #0110 + + + 0101 + tx_refclkdivided by 32 + #0101 + + + 0100 + tx_refclk divided by 16 + #0100 + + + 0011 + tx_refclk divided by 8 + #0011 + + + 0010 + tx_refclk divided by 4 + #0010 + + + 0001 + tx_refclk divided by 2 + #0001 + + + 0000 + tx_refclk divided by 1 + #0000 + + + + + TX_BREAK + no description available + 4 + 1 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + DATA_TIMEOUT_CNT + no description available + 8 + 4 + read-write + + + 1110 + HSI Tx Clock x 2 ^ 27 + #1110 + + + 0001 + HSI Tx Clock x 2 ^ 14 + #0001 + + + 0000 + HSI Tx Clock x 2 ^ 13 + #0000 + + + + + RX_TAIL_BIT_CNT + no description available + 12 + 2 + read-write + + + 00 + 800-> tx_refclk + #00 + + + 01 + 400-> tx_refclk + #01 + + + 10 + 200-> tx_refclk + #10 + + + 11 + 100-> tx_refclk + #11 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + RX_FRAME_BRST_CNT + no description available + 16 + 8 + read-write + + + RX_DLY_SEL + no description available + 24 + 3 + read-write + + + 000 + 0ns ; + #000 + + + 001 + 1ns ; + #001 + + + 010 + 2ns ; + #010 + + + 011 + 3ns ; + #011 + + + 100 + 4ns ; + #100 + + + 101 + 5ns ; + #101 + + + 110 + 6ns ; + #110 + + + 111 + 7ns ; + #111 + + + + + DMA_DISABLE + no description available + 27 + 1 + read-write + + + RESERVED + no description available + 28 + 2 + read-only + + + CLKGATE + no description available + 30 + 1 + read-write + + + SFTRST + no description available + 31 + 1 + read-write + + + + + TX_CONF + HSI Tx Config Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRANS_MODE + no description available + 0 + 1 + read-write + + + 0 + Stream Transmission Mode + #0 + + + 1 + Frame Transmission Mode + #1 + + + + + WAKEUP + no description available + 1 + 1 + read-write + + + 0 + Transmitter is in Sleep State + #0 + + + 1 + Transmitter is in Wakeup State. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + TIMEOUT_CNT + no description available + 8 + 4 + read-write + + + 0000 + tx timeout value 2^14 tx_refclk + #0000 + + + 0001 + tx timeout value 2^15 tx_refclk + #0001 + + + 0010 + tx timeout value 2^16 tx_refclk + #0010 + + + 0011 + tx timeout value 2^17 tx_refclk + #0011 + + + 1110 + tx timeout value 2^28 tx_refclk + #1110 + + + 1111 + tx timeout value 2^29 tx_refclk + #1111 + + + + + RESERVED + no description available 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available + 23 + 1 + read-write + + + 1 + Tx Ch7 is Enabled. + #1 + + + 0 + Tx Ch7 is Disabled. + #0 + + + + + CH8_EN + no description available + 24 + 1 + read-write + + + 1 + Tx Ch8 is Enabled. + #1 + + + 0 + Tx Ch8 is Disabled. + #0 + + + + + CH9_EN + no description available + 25 + 1 + read-write + + + 1 + Tx Ch9 is Enabled. + #1 + + + 0 + Tx Ch9 is Disabled. + #0 + + + + + CH10_EN + no description available + 26 + 1 + read-write + + + 1 + Tx Ch10 is Enabled. + #1 + + + 0 + Tx Ch10 is Disabled. + #0 + + + + + CH11_EN + no description available + 27 + 1 + read-write + + + 1 + Tx Ch11 is Enabled. + #1 + + + 0 + Tx Ch11 is Disabled. + #0 + + + + + CH12_EN + no description available + 28 + 1 + read-write + + + 1 + Tx Ch12 is Enabled. + #1 + + + 0 + Tx Ch12 is Disabled. + #0 + + + + + CH13_EN + no description available + 29 + 1 + read-write + + + 1 + Tx Ch13 is Enabled. + #1 + + + 0 + Tx Ch13 is Disabled. + #0 + + + + + CH14_EN + no description available + 30 + 1 + read-write + + + 1 + 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read-only + + + TIMEOUT_CNT + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + CH0_EN + no description available + 16 + 1 + read-write + + + 1 + Rx Ch0 is Enabled. + #1 + + + 0 + Rx Ch0 is Disabled. + #0 + + + + + CH1_EN + no description available + 17 + 1 + read-write + + + 1 + Rx Ch1 is Enabled. + #1 + + + 0 + Rx Ch1 is Disabled. + #0 + + + + + CH2_EN + no description available + 18 + 1 + read-write + + + 1 + Rx Ch2 is Enabled. + #1 + + + 0 + Rx Ch2 is Disabled. + #0 + + + + + CH3_EN + no description available + 19 + 1 + read-write + + + 1 + Rx Ch3 is Enabled. + #1 + + + 0 + Rx Ch3 is Disabled. + #0 + + + + + CH4_EN + no description available + 20 + 1 + read-write + + + 1 + Rx Ch4 is Enabled. + #1 + + + 0 + Rx Ch4 is Disabled. + #0 + + + + + CH5_EN + no description available + 21 + 1 + read-write + + + 1 + Rx Ch5 is Enabled. + #1 + + + 0 + Rx Ch5 is Disabled. + #0 + + + + + CH6_EN + no description available + 22 + 1 + read-write + + + 1 + Rx Ch6 is Enabled. + #1 + + + 0 + Rx Ch6 is Disabled. + #0 + + + + + CH7_EN + no description available + 23 + 1 + read-write + + + 1 + Rx Ch7 is Enabled. + #1 + + + 0 + Rx Ch7 is Disabled. + #0 + + + + + CH8_EN + no description available + 24 + 1 + read-write + + + 1 + Rx Ch8 is Enabled. + #1 + + + 0 + Rx Ch8 is Disabled. + #0 + + + + + CH9_EN + no description available + 25 + 1 + read-write + + + 1 + Rx Ch9 is Enabled. + #1 + + + 0 + Rx Ch9 is Disabled. + #0 + + + + + CH10_EN + no description available + 26 + 1 + read-write + + + 1 + Rx Ch10 is Enabled. + #1 + + + 0 + Rx Ch10 is Disabled. + #0 + + + + + CH11_EN + no description available + 27 + 1 + read-write + + + 1 + Rx Ch11 is Enabled. + #1 + + + 0 + Rx Ch11 is Disabled. + #0 + + + + + CH12_EN + no description available + 28 + 1 + read-write + + + 1 + Rx Ch12 is Enabled. + #1 + + + 0 + Rx Ch12 is Disabled. + #0 + + + + + CH13_EN + no description available + 29 + 1 + read-write + + + 1 + Rx Ch13 is Enabled. + #1 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Configuration Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH0 + no description available + 0 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH1 + no description available + 1 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH2 + no description available + 2 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH3 + no description available + 3 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH4 + no description available + 4 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH5 + no description available + 5 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH6 + no description available + 6 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH7 + no description available + 7 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH8 + no description available + 8 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH9 + no description available + 9 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH10 + no description available + 10 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH11 + no description available + 11 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH12 + no description available + 12 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH13 + no description available + 13 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH14 + no description available + 14 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + RX_CH15 + no description available + 15 + 1 + read-write + + + 0 + Half Full (fifo size / 2) + #0 + + + 1 + Almost Full (3/4th of fifo size) + #1 + + + + + TX_CH0 + no description available + 16 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH1 + no description available + 17 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH2 + no description available + 18 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH3 + no description available + 19 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH4 + no description available + 20 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH5 + no description available + 21 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH6 + no description available + 22 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH7 + no description available + 23 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH8 + no description available + 24 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH9 + no description available + 25 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH10 + no description available + 26 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH11 + no description available + 27 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH12 + no description available + 28 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH13 + no description available + 29 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH14 + no description available + 30 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + TX_CH15 + no description available + 31 + 1 + read-write + + + 0 + Half Empty (fifo size / 2) + #0 + + + 1 + Almost Empty (fifo size / 4) + #1 + + + + + + + CH_SFTRST + Tx and Rx Channel Soft Reset Register + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + RX_CH0 + no description available + 0 + 1 + write-only + + + RX_CH1 + no description available + 1 + 1 + write-only + + + RX_CH2 + no description available + 2 + 1 + write-only + + + RX_CH3 + no description available + 3 + 1 + write-only + + + RX_CH4 + no description available + 4 + 1 + write-only + + + RX_CH5 + no description available + 5 + 1 + write-only + + + RX_CH6 + no description available + 6 + 1 + write-only + + + RX_CH7 + no description available + 7 + 1 + write-only + + + RX_CH8 + no description available + 8 + 1 + write-only + + + RX_CH9 + no description available + 9 + 1 + write-only + + + RX_CH10 + no description available + 10 + 1 + write-only + + + RX_CH11 + no description available + 11 + 1 + write-only + + + RX_CH12 + no description available + 12 + 1 + write-only + + + RX_CH13 + no description available + 13 + 1 + write-only + + + RX_CH14 + no description available + 14 + 1 + write-only + + + RX_CH15 + no description available + 15 + 1 + write-only + + + TX_CH0 + no description available + 16 + 1 + write-only + + + TX_CH1 + no description available + 17 + 1 + write-only + + + TX_CH2 + no description available + 18 + 1 + write-only + + + TX_CH3 + no description available + 19 + 1 + write-only + + + TX_CH4 + no description available + 20 + 1 + write-only + + + TX_CH5 + no description available + 21 + 1 + write-only + + + TX_CH6 + no description available + 22 + 1 + write-only + + + TX_CH7 + no description available + 23 + 1 + write-only + + + TX_CH8 + no description available + 24 + 1 + write-only + + + TX_CH9 + no description available + 25 + 1 + write-only + + + TX_CH10 + no description available + 26 + 1 + write-only + + + TX_CH11 + no description available + 27 + 1 + write-only + + + TX_CH12 + no description available + 28 + 1 + write-only + + + TX_CH13 + no description available + 29 + 1 + write-only + + + TX_CH14 + no description available + 30 + 1 + write-only + + + TX_CH15 + no description available + 31 + 1 + write-only + + + + + IRQSTAT + HSI Interrupt Status Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIFO_THRESHOLD_INT + no description available + 0 + 1 + read-only + + + 1 + Threshold amount of data reached in TX/Rx FIFO Interrupt Status + #1 + + + 0 + Threshold amount of data not reached in TX/Rx FIFO Interrupt Status + #0 + + + + + RX_WAKEUP_INT + no description available + 1 + 1 + write-only + + + 1 + Receiver Wakeup event is occurred + #1 + + + 0 + Receiver Wakeup event is not occurred + #0 + + + + + RX_TIMEOUT_INT + no description available + 2 + 1 + read-only + + + 0 + No Error. + #0 + + + 1 + Error. + #1 + + + + + DMA_INT + no description available + 3 + 1 + read-only + + + DMA_ERR_INT + no description available + 4 + 1 + read-only + + + 0 + No Error. + #0 + + + 1 + Error. + #1 + + + + + TX_TIMEOUT_ERR_INT + no description available + 5 + 1 + write-only + + + 0 + No Error. + #0 + + + 1 + Error. + #1 + + + + + RX_ERROR_INT + no description available + 6 + 1 + write-only + + + 0 + No Error. + #0 + + + 1 + Error. + #1 + + + + + RX_BREAK_INT + no description available + 7 + 1 + write-only + + + 0 + No Error. + #0 + + + 1 + Error. + #1 + + + + + TX_EMPTY_INT + no description available + 8 + 1 + read-only + + + 1 + All tx channel empty and tx state IDLE Interrupt Status + #1 + + + 0 + not All tx channel empty and tx state IDLE Interrupt Status + #0 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + IRQSTAT_EN + HSI Interrupt Status Enable Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIFO_THRESHOLD_INT + no description available + 0 + 1 + read-write + + + 1 + Interrupt status enabled for FIFO_THRESHOLD_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked FIFO_THRESHOLD_INT_STATUS interrupt. + #0 + + + + + RX_WAKEUP_INT + no description available + 1 + 1 + read-write + + + 1 + Interrupt status enabled for RX_WAKEUP_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked RX_WAKEUP_INT_STATUS interrupt. + #0 + + + + + RX_TIMEOUT_INT + no description available + 2 + 1 + read-write + + + 1 + Interrupt status enabled for RX_TIMEOUT_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked RX_TIMEOUT_INT_STATUS interrupt. + #0 + + + + + DMA_INT + no description available + 3 + 1 + read-write + + + 1 + Interrupt status enabled for DMA_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked DMA_INT_STATUS interrupt. + #0 + + + + + DMA_ERR_INT + no description available + 4 + 1 + read-write + + + 1 + Interrupt status enabled for DMA_ERROR_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked DMA_ERROR_INT_STATUS interrupt. + #0 + + + + + TX_TIMEOUT_ERR_INT + no description available + 5 + 1 + read-write + + + 1 + Interrupt status enabled for TX_TIMEOUT_ERR status interrupt. + #1 + + + 0 + Interrupt status masked TX_TIMEOUT_ERR status interrupt. + #0 + + + + + RX_ERROR_INT + no description available + 6 + 1 + read-write + + + 1 + Interrupt status enabled for RX_ERROR status interrupt. + #1 + + + 0 + Interrupt status masked RX_ERROR status interrupt. + #0 + + + + + RX_BREAK_INT + no description available + 7 + 1 + read-write + + + 1 + Interrupt status enabled for RX_BREAK status interrupt. + #1 + + + 0 + Interrupt status masked RX_BREAK status interrupt. + #0 + + + + + TX_EMPTY_INT + no description available + 8 + 1 + read-write + + + 1 + Interrupt status enabled for TX_EMPTY_INT_STATUS interrupt. + #1 + + + 0 + Interrupt status masked TX_EMPTY_INT_STATUS interrupt. + #0 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + IRQSIG_EN + HSI Interrupt Signal Enable Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + FIFO_THRESHOLD_INT + no description available + 0 + 1 + read-write + + + 1 + Interrupt signal enabled for HSI FIFO_THRESHOLD interrupt. + #1 + + + 0 + Interrupt signal masked for HSI FIFO_THRESHOLD interrupt. + #0 + + + + + RX_WAKEUP_INT + no description available + 1 + 1 + read-write + + + 1 + Interrupt signal enabled for HSI RX Wakeup interrupt. + #1 + + + 0 + Interrupt signal masked for HSI RX Wakeup interrupt. + #0 + + + + + RX_TIMEOUT_INT + no description available + 2 + 1 + read-write + + + 1 + Interrupt signal enabled for RX TIMEOUT interrupt. + #1 + + + 0 + Interrupt signal masked for RX TIMEOUT interrupt. + #0 + + + + + DMA_INT + no description available + 3 + 1 + read-write + + + 1 + Interrupt signal enabled for DMA Completed interrupt. + #1 + + + 0 + Interrupt signal masked for DMA Completed interrupt. + #0 + + + + + DMA_ERR_INT + no description available + 4 + 1 + read-write + + + 1 + Interrupt signal enabled for DMA Error interrupt. + #1 + + + 0 + Interrupt signal masked for DMA Error interrupt. + #0 + + + + + TX_TIMEOUT_ERR_INT + no description available + 5 + 1 + read-write + + + 1 + Interrupt signal enabled for TX Timeout Error interrupt. + #1 + + + 0 + Interrupt signal masked for TX Timeout Error interrupt. + #0 + + + + + RX_ERROR_INT + no description available + 6 + 1 + read-write + + + 1 + Interrupt signal enabled for RX Error interrupt. + #1 + + + 0 + Interrupt signal masked for RX Error interrupt. + #0 + + + + + RX_BREAK_INT + no description available + 7 + 1 + read-write + + + 1 + Interrupt signal enabled for RX_BREAK interrupt. + #1 + + + 0 + Interrupt signal masked for RX_BREAK interrupt. + #0 + + + + + TX_EMPTY_INT + no description available + 8 + 1 + read-write + + + 1 + Interrupt signal enabled for HSI TX_EMPTY interrupt. + #1 + + + 0 + Interrupt signal masked for HSI TX_EMPTY interrupt. + #0 + + + + + RESERVED + no description available + 9 + 23 + read-only + + + + + FIFO_THR_IRQSTAT + HSI FIFO Threshold Interrupt Status Register + 0x3C + 32 + read-only + 0xFFFF0000 + 0xFFFFFFFF + + + RX_CH0_INT + no description available + 0 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 0 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 0 FIFO + #0 + + + + + RX_CH1_INT + no description available + 1 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 1 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 1 FIFO + #0 + + + + + RX_CH2_INT + no description available + 2 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 2 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 2 FIFO + #0 + + + + + RX_CH3_INT + no description available + 3 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 3 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 3 FIFO + #0 + + + + + RX_CH4_INT + no description available + 4 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 4 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 4 FIFO + #0 + + + + + RX_CH5_INT + no description available + 5 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 5 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 5 FIFO + #0 + + + + + RX_CH6_INT + no description available + 6 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 6 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 6 FIFO + #0 + + + + + RX_CH7_INT + no description available + 7 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 7 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 7 FIFO + #0 + + + + + RX_CH8_INT + no description available + 8 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 8 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 8 FIFO + #0 + + + + + RX_CH9_INT + no description available + 9 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 9 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 9 FIFO + #0 + + + + + RX_CH10_INT + no description available + 10 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 10 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 10 FIFO + #0 + + + + + RX_CH11_INT + no description available + 11 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 11 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 11 FIFO + #0 + + + + + RX_CH12_INT + no description available + 12 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 12 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 12 FIFO + #0 + + + + + RX_CH13_INT + no description available + 13 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 13 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 13 FIFO + #0 + + + + + RX_CH14_INT + no description available + 14 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 14 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 14 FIFO + #0 + + + + + RX_CH15_INT + no description available + 15 + 1 + read-only + + + 1 + Threshold amount of data reached in Rx Channel 15 FIFO + #1 + + + 0 + Threshold amount of data not reached in Rx Channel 15 FIFO + #0 + + + + + TX_CH0_INT + no description available + 16 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 0 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 0 FIFO + #0 + + + + + TX_CH1_INT + no description available + 17 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 1 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 1 FIFO + #0 + + + + + TX_CH2_INT + no description available + 18 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 2 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 2 FIFO + #0 + + + + + TX_CH3_INT + no description available + 19 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 3 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 3 FIFO + #0 + + + + + TX_CH4_INT + no description available + 20 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 4 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 4 FIFO + #0 + + + + + TX_CH5_INT + no description available + 21 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 5 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 5 FIFO + #0 + + + + + TX_CH6_INT + no description available + 22 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 6 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 6 FIFO + #0 + + + + + TX_CH7_INT + no description available + 23 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 7 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 7 FIFO + #0 + + + + + TX_CH8_INT + no description available + 24 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 8 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 8 FIFO + #0 + + + + + TX_CH9_INT + no description available + 25 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 9 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 9 FIFO + #0 + + + + + TX_CH10_INT + no description available + 26 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 10 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 10 FIFO + #0 + + + + + TX_CH11_INT + no description available + 27 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 11 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 11 FIFO + #0 + + + + + TX_CH12_INT + no description available + 28 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 12 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 12 FIFO + #0 + + + + + TX_CH13_INT + no description available + 29 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 13 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 13 FIFO + #0 + + + + + TX_CH14_INT + no description available + 30 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 14 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 14 FIFO + #0 + + + + + TX_CH15_INT + no description available + 31 + 1 + read-only + + + 1 + Threshold amount of data reached in Tx Channel 15 FIFO + #1 + + + 0 + Threshold amount of data not reached in Tx Channel 15 FIFO + #0 + + + + + + + FIFO_THR_IRQSTAT_EN + HSI FIFO Threshold Interrupt Status Enable Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH0_INT + no description available + 0 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch0 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch0 threshold Reached interrupt. + #0 + + + + + RX_CH1_INT + no description available + 1 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch1 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch1 threshold Reached interrupt. + #0 + + + + + RX_CH2_INT + no description available + 2 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch2 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch2 threshold Reached interrupt. + #0 + + + + + RX_CH3_INT + no description available + 3 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch3 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch3 threshold Reached interrupt. + #0 + + + + + RX_CH4_INT + no description available + 4 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch4 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch4 threshold Reached interrupt. + #0 + + + + + RX_CH5_INT + no description available + 5 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch5 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch5 threshold Reached interrupt. + #0 + + + + + RX_CH6_INT + no description available + 6 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch6 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch6 threshold Reached interrupt. + #0 + + + + + RX_CH7_INT + no description available + 7 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch7 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch7 threshold Reached interrupt. + #0 + + + + + RX_CH8_INT + no description available + 8 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch8 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch8 threshold Reached interrupt. + #0 + + + + + RX_CH9_INT + no description available + 9 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch9 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch9 threshold Reached interrupt. + #0 + + + + + RX_CH10_INT + no description available + 10 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch10 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch10 threshold Reached interrupt. + #0 + + + + + RX_CH11_INT + no description available + 11 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch11 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch11 threshold Reached interrupt. + #0 + + + + + RX_CH12_INT + no description available + 12 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch12 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch12 threshold Reached interrupt. + #0 + + + + + RX_CH13_INT + no description available + 13 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch13 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch13 threshold Reached interrupt. + #0 + + + + + RX_CH14_INT + no description available + 14 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch14 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch14 threshold Reached interrupt. + #0 + + + + + RX_CH15_INT + no description available + 15 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch15 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch15 threshold Reached interrupt. + #0 + + + + + TX_CH0_INT + no description available + 16 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch0 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch0 threshold Reached interrupt. + #0 + + + + + TX_CH1_INT + no description available + 17 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch1 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch1 threshold Reached interrupt. + #0 + + + + + TX_CH2_INT + no description available + 18 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch2 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch2 threshold Reached interrupt. + #0 + + + + + TX_CH3_INT + no description available + 19 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch3 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch3 threshold Reached interrupt. + #0 + + + + + TX_CH4_INT + no description available + 20 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch4 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch4 threshold Reached interrupt. + #0 + + + + + TX_CH5_INT + no description available + 21 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch5 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch5 threshold Reached interrupt. + #0 + + + + + TX_CH6_INT + no description available + 22 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch6 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch6 threshold Reached interrupt. + #0 + + + + + TX_CH7_INT + no description available + 23 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch7 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch7 threshold Reached interrupt. + #0 + + + + + TX_CH8_INT + no description available + 24 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch8 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch8 threshold Reached interrupt. + #0 + + + + + TX_CH9_INT + no description available + 25 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch9 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch9 threshold Reached interrupt. + #0 + + + + + TX_CH10_INT + no description available + 26 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch10 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch10 threshold Reached interrupt. + #0 + + + + + TX_CH11_INT + no description available + 27 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch11 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch11 threshold Reached interrupt. + #0 + + + + + TX_CH12_INT + no description available + 28 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch12 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch12 threshold Reached interrupt. + #0 + + + + + TX_CH13_INT + no description available + 29 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch13 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch13 threshold Reached interrupt. + #0 + + + + + TX_CH14_INT + no description available + 30 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch14 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch14 threshold Reached interrupt. + #0 + + + + + TX_CH15_INT + no description available + 31 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch15 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch15 threshold Reached interrupt. + #0 + + + + + + + FIFO_THR_IRQSIG_EN + HSI FIFO Threshold Interrupt Signal Enable Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_CH0_INT + no description available + 0 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch0 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch0 threshold Reached interrupt. + #0 + + + + + RX_CH1_INT + no description available + 1 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch1 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch1 threshold Reached interrupt. + #0 + + + + + RX_CH2_INT + no description available + 2 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch2 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch2 threshold Reached interrupt. + #0 + + + + + RX_CH3_INT + no description available + 3 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch3 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch3 threshold Reached interrupt. + #0 + + + + + RX_CH4_INT + no description available + 4 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch4 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch4 threshold Reached interrupt. + #0 + + + + + RX_CH5_INT + no description available + 5 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch5 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch5 threshold Reached interrupt. + #0 + + + + + RX_CH6_INT + no description available + 6 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch6 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch6 threshold Reached interrupt. + #0 + + + + + RX_CH7_INT + no description available + 7 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch7 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch7 threshold Reached interrupt. + #0 + + + + + RX_CH8_INT + no description available + 8 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch8 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch8 threshold Reached interrupt. + #0 + + + + + RX_CH9_INT + no description available + 9 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch9 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch9 threshold Reached interrupt. + #0 + + + + + RX_CH10_INT + no description available + 10 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch10 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch10 threshold Reached interrupt. + #0 + + + + + RX_CH11_INT + no description available + 11 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch11 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch11 threshold Reached interrupt. + #0 + + + + + RX_CH12_INT + no description available + 12 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch12 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch12 threshold Reached interrupt. + #0 + + + + + RX_CH13_INT + no description available + 13 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch13 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch13 threshold Reached interrupt. + #0 + + + + + RX_CH14_INT + no description available + 14 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch14 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch14 threshold Reached interrupt. + #0 + + + + + RX_CH15_INT + no description available + 15 + 1 + read-write + + + 1 + Interrupt signal enabled for Rx Ch15 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Rx Ch15 threshold Reached interrupt. + #0 + + + + + TX_CH0_INT + no description available + 16 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch0 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch0 threshold Reached interrupt. + #0 + + + + + TX_CH1_INT + no description available + 17 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch1 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch1 threshold Reached interrupt. + #0 + + + + + TX_CH2_INT + no description available + 18 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch2 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch2 threshold Reached interrupt. + #0 + + + + + TX_CH3_INT + no description available + 19 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch3 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch3 threshold Reached interrupt. + #0 + + + + + TX_CH4_INT + no description available + 20 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch4 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch4 threshold Reached interrupt. + #0 + + + + + TX_CH5_INT + no description available + 21 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch5 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch5 threshold Reached interrupt. + #0 + + + + + TX_CH6_INT + no description available + 22 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch6 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch6 threshold Reached interrupt. + #0 + + + + + TX_CH7_INT + no description available + 23 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch7 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch7 threshold Reached interrupt. + #0 + + + + + TX_CH8_INT + no description available + 24 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch8 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch8 threshold Reached interrupt. + #0 + + + + + TX_CH9_INT + no description available + 25 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch9 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch9 threshold Reached interrupt. + #0 + + + + + TX_CH10_INT + no description available + 26 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch10 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch10 threshold Reached interrupt. + #0 + + + + + TX_CH11_INT + no description available + 27 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch11 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch11 threshold Reached interrupt. + #0 + + + + + TX_CH12_INT + no description available + 28 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch12 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch12 threshold Reached interrupt. + #0 + + + + + TX_CH13_INT + no description available + 29 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch13 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch13 threshold Reached interrupt. + #0 + + + + + TX_CH14_INT + no description available + 30 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch14 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch14 threshold Reached interrupt. + #0 + + + + + TX_CH15_INT + no description available + 31 + 1 + read-write + + + 1 + Interrupt signal enabled for Tx Ch15 threshold Reached interrupt. + #1 + + + 0 + Interrupt signal masked for Tx Ch15 threshold Reached interrupt. + #0 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + TX_CH%s_DP + Tx Channel n Data Port Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + RX_CH%s_DP + Rx Channel n Data Port Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + no description available + 0 + 32 + read-write + + + + + ERR_IRQSTAT + HSI Error Interrupt Status Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RX_CH0_TIMEOUT_INT + no description available + 16 + 1 + read-only + + + RX_CH1_TIMEOUT_INT + no description available + 17 + 1 + read-only + + + RX_CH2_TIMEOUT_INT + no description available + 18 + 1 + read-only + + + RX_CH3_TIMEOUT_INT + no description available + 19 + 1 + read-only + + + RX_CH4_TIMEOUT_INT + no description available + 20 + 1 + read-only + + + RX_CH5_TIMEOUT_INT + no description available + 21 + 1 + read-only + + + RX_CH6_TIMEOUT_INT + no description available + 22 + 1 + read-only + + + RX_CH7_TIMEOUT_INT + no description available + 23 + 1 + read-only + + + RX_CH8_TIMEOUT_INT + no description available + 24 + 1 + read-only + + + RX_CH9_TIMEOUT_INT + no description available + 25 + 1 + read-only + + + RX_CH10_TIMEOUT_INT + no description available + 26 + 1 + read-only + + + RX_CH11_TIMEOUT_INT + no description available + 27 + 1 + read-only + + + RX_CH12_TIMEOUT_INT + no description available + 28 + 1 + read-only + + + RX_CH13_TIMEOUT_INT + no description available + 29 + 1 + read-only + + + RX_CH14_TIMEOUT_INT + no description available + 30 + 1 + read-only + + + RX_CH15_TIMEOUT_INT + no description available + 31 + 1 + read-only + + + + + ERR_IRQSTAT_EN + HSI Error Interrupt Status Enable Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RX_CH0_TIMEOUT_INT_EN + no description available + 16 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch0 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch0 interrupt. + #0 + + + + + RX_CH1_TIMEOUT_INT_EN + no description available + 17 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch1 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch1 interrupt. + #0 + + + + + RX_CH2_TIMEOUT_INT_EN + no description available + 18 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch2 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch2 interrupt. + #0 + + + + + RX_CH3_TIMEOUT_INT_EN + no description available + 19 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch3 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch3 interrupt. + #0 + + + + + RX_CH4_TIMEOUT_INT_EN + no description available + 20 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch4 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch4 interrupt. + #0 + + + + + RX_CH5_TIMEOUT_INT_EN + no description available + 21 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch5 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch5 interrupt. + #0 + + + + + RX_CH6_TIMEOUT_INT_EN + no description available + 22 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch6 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch6 interrupt. + #0 + + + + + RX_CH7_TIMEOUT_INT_EN + no description available + 23 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch7 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch7 interrupt. + #0 + + + + + RX_CH8_TIMEOUT_INT_EN + no description available + 24 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch8 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch8 interrupt. + #0 + + + + + RX_CH9_TIMEOUT_INT_EN + no description available + 25 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch9 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch9 interrupt. + #0 + + + + + RX_CH10_TIMEOUT_INT_EN + no description available + 26 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch10 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch10 interrupt. + #0 + + + + + RX_CH11_TIMEOUT_INT_EN + no description available + 27 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch11 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch11 interrupt. + #0 + + + + + RX_CH12_TIMEOUT_INT_EN + no description available + 28 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch12 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch12 interrupt. + #0 + + + + + RX_CH13_TIMEOUT_INT_EN + no description available + 29 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch13 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch13 interrupt. + #0 + + + + + RX_CH14_TIMEOUT_INT_EN + no description available + 30 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch14 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch14 interrupt. + #0 + + + + + RX_CH15_TIMEOUT_INT_EN + no description available + 31 + 1 + read-write + + + 1 + Interrupt status enabled for data timeout for ch15 interrupt. + #1 + + + 0 + Interrupt status masked for data timeout for ch15 interrupt. + #0 + + + + + + + ERR_IRQSIG_EN + HSI Error Interrupt Signal Enable Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + RX_CH0_TIMEOUT_INT_EN + no description available + 16 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch0 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch0 interrupt. + #0 + + + + + RX_CH1_TIMEOUT_INT_EN + no description available + 17 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch1 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch1interrupt. + #0 + + + + + RX_CH2_TIMEOUT_INT_EN + no description available + 18 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch2 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch2 interrupt. + #0 + + + + + RX_CH3_TIMEOUT_INT_EN + no description available + 19 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch3 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch3 interrupt. + #0 + + + + + RX_CH4_TIMEOUT_INT_EN + no description available + 20 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch4 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch4 interrupt. + #0 + + + + + RX_CH5_TIMEOUT_INT_EN + no description available + 21 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch5 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch5 interrupt. + #0 + + + + + RX_CH6_TIMEOUT_INT_EN + no description available + 22 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch6 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch6 interrupt. + #0 + + + + + RX_CH7_TIMEOUT_INT_EN + no description available + 23 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch7 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch7 interrupt. + #0 + + + + + RX_CH8_TIMEOUT_INT_EN + no description available + 24 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch8 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch8 interrupt. + #0 + + + + + RX_CH9_TIMEOUT_INT_EN + no description available + 25 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch9 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch9 interrupt. + #0 + + + + + RX_CH10_TIMEOUT_INT_EN + no description available + 26 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch10 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch10 interrupt. + #0 + + + + + RX_CH11_TIMEOUT_INT_EN + no description available + 27 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch11 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch11 interrupt. + #0 + + + + + RX_CH12_TIMEOUT_INT_EN + no description available + 28 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch12 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch12 interrupt. + #0 + + + + + RX_CH13_TIMEOUT_INT_EN + no description available + 29 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch13 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch13 interrupt. + #0 + + + + + RX_CH14_TIMEOUT_INT_EN + no description available + 30 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch14 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch14 interrupt. + #0 + + + + + RX_CH15_TIMEOUT_INT_EN + no description available + 31 + 1 + read-write + + + 1 + Interrupt signal enabled for data timeout for ch15 interrupt. + #1 + + + 0 + Interrupt signal masked for data timeout for ch15 interrupt. + #0 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + TDMA%s_CONF + Tx DMA Channel n Configuration Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 5 + read-only + + + TRANS_LENGTH + no description available + 5 + 20 + read-write + + + BURST_SIZE + no description available + 25 + 4 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + ENABLE + no description available + 31 + 1 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + RDMA%s_CONF + Rx DMA Channel n Configuration Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 5 + read-only + + + TRANS_LENGTH + no description available + 5 + 20 + read-write + + + BURST_SIZE + no description available + 25 + 4 + read-write + + + RESERVED + no description available + 29 + 2 + read-only + + + ENABLE + no description available + 31 + 1 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + TDMA%s_STA_ADDR + Tx DMA Channel n Start Address Register + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + RDMA%s_STA_ADDR + Rx DMA Channel n Start Address Register + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 2 + read-only + + + DS_ADDR + no description available + 2 + 30 + read-write + + + + + DMA_IRQSTAT + DMA Interrupt Status Register + 0x1DC + 32 + read-only + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-only + + + RDMA1 + no description available + 1 + 1 + read-only + + + RDMA2 + no description available + 2 + 1 + read-only + + + RDMA3 + no description available + 3 + 1 + read-only + + + RDMA4 + no description available + 4 + 1 + read-only + + + RDMA5 + no description available + 5 + 1 + read-only + + + RDMA6 + no description available + 6 + 1 + read-only + + + RDMA7 + no description available + 7 + 1 + read-only + + + RDMA8 + no description available + 8 + 1 + read-only + + + RDMA9 + no description available + 9 + 1 + read-only + + + RDMA10 + no description available + 10 + 1 + read-only + + + RDMA11 + no description available + 11 + 1 + read-only + + + RDMA12 + no description available + 12 + 1 + read-only + + + RDMA13 + no description available + 13 + 1 + read-only + + + RDMA14 + no description available + 14 + 1 + read-only + + + RDMA15 + no description available + 15 + 1 + read-only + + + TDMA0 + no description available + 16 + 1 + read-only + + + TDMA1 + no description available + 17 + 1 + read-only + + + TDMA2 + no description available + 18 + 1 + read-only + + + TDMA3 + no description available + 19 + 1 + read-only + + + TDMA4 + no description available + 20 + 1 + read-only + + + TDMA5 + no description available + 21 + 1 + read-only + + + TDMA6 + no description available + 22 + 1 + read-only + + + TDMA7 + no description available + 23 + 1 + read-only + + + TDMA8 + no description available + 24 + 1 + read-only + + + TDMA9 + no description available + 25 + 1 + read-only + + + TDMA10 + no description available + 26 + 1 + read-only + + + TDMA11 + no description available + 27 + 1 + read-only + + + TDMA12 + no description available + 28 + 1 + read-only + + + TDMA13 + no description available + 29 + 1 + read-only + + + TDMA14 + no description available + 30 + 1 + read-only + + + TDMA15 + no description available + 31 + 1 + read-only + + + + + DMA_IRQSTAT_EN + DMA Interrupt Enable Register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-write + + + RDMA1 + no description available + 1 + 1 + read-write + + + RDMA2 + no description available + 2 + 1 + read-write + + + RDMA3 + no description available + 3 + 1 + read-write + + + RDMA4 + no description available + 4 + 1 + read-write + + + RDMA5 + no description available + 5 + 1 + read-write + + + RDMA6 + no description available + 6 + 1 + read-write + + + RDMA7 + no description available + 7 + 1 + read-write + + + RDMA8 + no description available + 8 + 1 + read-write + + + RDMA9 + no description available + 9 + 1 + read-write + + + RDMA10 + no description available + 10 + 1 + read-write + + + RDMA11 + no description available + 11 + 1 + read-write + + + RDMA12 + no description available + 12 + 1 + read-write + + + RDMA13 + no description available + 13 + 1 + read-write + + + RDMA14 + no description available + 14 + 1 + read-write + + + RDMA15 + no description available + 15 + 1 + read-write + + + TDMA0 + no description available + 16 + 1 + read-write + + + TDMA1 + no description available + 17 + 1 + read-write + + + TDMA2 + no description available + 18 + 1 + read-write + + + TDMA3 + no description available + 19 + 1 + read-write + + + TDMA4 + no description available + 20 + 1 + read-write + + + TDMA5 + no description available + 21 + 1 + read-write + + + TDMA6 + no description available + 22 + 1 + read-write + + + TDMA7 + no description available + 23 + 1 + read-write + + + TDMA8 + no description available + 24 + 1 + read-write + + + TDMA9 + no description available + 25 + 1 + read-write + + + TDMA10 + no description available + 26 + 1 + read-write + + + TDMA11 + no description available + 27 + 1 + read-write + + + TDMA12 + no description available + 28 + 1 + read-write + + + TDMA13 + no description available + 29 + 1 + read-write + + + TDMA14 + no description available + 30 + 1 + read-write + + + TDMA15 + no description available + 31 + 1 + read-write + + + + + DMA_IRQSIG_EN + DMA Interrupt Status Signal Enable Register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-write + + + RDMA1 + no description available + 1 + 1 + read-write + + + RDMA2 + no description available + 2 + 1 + read-write + + + RDMA3 + no description available + 3 + 1 + read-write + + + RDMA4 + no description available + 4 + 1 + read-write + + + RDMA5 + no description available + 5 + 1 + read-write + + + RDMA6 + no description available + 6 + 1 + read-write + + + RDMA7 + no description available + 7 + 1 + read-write + + + RDMA8 + no description available + 8 + 1 + read-write + + + RDMA9 + no description available + 9 + 1 + read-write + + + RDMA10 + no description available + 10 + 1 + read-write + + + RDMA11 + no description available + 11 + 1 + read-write + + + RDMA12 + no description available + 12 + 1 + read-write + + + RDMA13 + no description available + 13 + 1 + read-write + + + RDMA14 + no description available + 14 + 1 + read-write + + + RDMA15 + no description available + 15 + 1 + read-write + + + TDMA0 + no description available + 16 + 1 + read-write + + + TDMA1 + no description available + 17 + 1 + read-write + + + TDMA2 + no description available + 18 + 1 + read-write + + + TDMA3 + no description available + 19 + 1 + read-write + + + TDMA4 + no description available + 20 + 1 + read-write + + + TDMA5 + no description available + 21 + 1 + read-write + + + TDMA6 + no description available + 22 + 1 + read-write + + + TDMA7 + no description available + 23 + 1 + read-write + + + TDMA8 + no description available + 24 + 1 + read-write + + + TDMA9 + no description available + 25 + 1 + read-write + + + TDMA10 + no description available + 26 + 1 + read-write + + + TDMA11 + no description available + 27 + 1 + read-write + + + TDMA12 + no description available + 28 + 1 + read-write + + + TDMA13 + no description available + 29 + 1 + read-write + + + TDMA14 + no description available + 30 + 1 + read-write + + + TDMA15 + no description available + 31 + 1 + read-write + + + + + DMA_ERR_IRQSTAT + DMA Error Interrupt Status Register + 0x1E8 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-only + + + RDMA1 + no description available + 1 + 1 + read-only + + + RDMA2 + no description available + 2 + 1 + read-only + + + RDMA3 + no description available + 3 + 1 + read-only + + + RDMA4 + no description available + 4 + 1 + read-only + + + RDMA5 + no description available + 5 + 1 + read-only + + + RDMA6 + no description available + 6 + 1 + read-only + + + RDMA7 + no description available + 7 + 1 + read-only + + + RDMA8 + no description available + 8 + 1 + read-only + + + RDMA9 + no description available + 9 + 1 + read-only + + + RDMA10 + no description available + 10 + 1 + read-only + + + RDMA11 + no description available + 11 + 1 + read-only + + + RDMA12 + no description available + 12 + 1 + read-only + + + RDMA13 + no description available + 13 + 1 + read-only + + + RDMA14 + no description available + 14 + 1 + read-only + + + RDMA15 + no description available + 15 + 1 + read-only + + + TDMA0 + no description available + 16 + 1 + read-only + + + TDMA1 + no description available + 17 + 1 + read-only + + + TDMA2 + no description available + 18 + 1 + read-only + + + TDMA3 + no description available + 19 + 1 + read-only + + + TDMA4 + no description available + 20 + 1 + read-only + + + TDMA5 + no description available + 21 + 1 + read-only + + + TDMA6 + no description available + 22 + 1 + read-only + + + TDMA7 + no description available + 23 + 1 + read-only + + + TDMA8 + no description available + 24 + 1 + read-only + + + TDMA9 + no description available + 25 + 1 + read-only + + + TDMA10 + no description available + 26 + 1 + read-only + + + TDMA11 + no description available + 27 + 1 + read-only + + + TDMA12 + no description available + 28 + 1 + read-only + + + TDMA13 + no description available + 29 + 1 + read-only + + + TDMA14 + no description available + 30 + 1 + read-only + + + TDMA15 + no description available + 31 + 1 + read-only + + + + + DMA_ERR_IRQSTAT_EN + DMA Error Interrupt Enable Register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-write + + + RDMA1 + no description available + 1 + 1 + read-write + + + RDMA2 + no description available + 2 + 1 + read-write + + + RDMA3 + no description available + 3 + 1 + read-write + + + RDMA4 + no description available + 4 + 1 + read-write + + + RDMA5 + no description available + 5 + 1 + read-write + + + RDMA6 + no description available + 6 + 1 + read-write + + + RDMA7 + no description available + 7 + 1 + read-write + + + RDMA8 + no description available + 8 + 1 + read-write + + + RDMA9 + no description available + 9 + 1 + read-write + + + RDMA10 + no description available + 10 + 1 + read-write + + + RDMA11 + no description available + 11 + 1 + read-write + + + RDMA12 + no description available + 12 + 1 + read-write + + + RDMA13 + no description available + 13 + 1 + read-write + + + RDMA14 + no description available + 14 + 1 + read-write + + + RDMA15 + no description available + 15 + 1 + read-write + + + TDMA0 + no description available + 16 + 1 + read-write + + + TDMA1 + no description available + 17 + 1 + read-write + + + TDMA2 + no description available + 18 + 1 + read-write + + + TDMA3 + no description available + 19 + 1 + read-write + + + TDMA4 + no description available + 20 + 1 + read-write + + + TDMA5 + no description available + 21 + 1 + read-write + + + TDMA6 + no description available + 22 + 1 + read-write + + + TDMA7 + no description available + 23 + 1 + read-write + + + TDMA8 + no description available + 24 + 1 + read-write + + + TDMA9 + no description available + 25 + 1 + read-write + + + TDMA10 + no description available + 26 + 1 + read-write + + + TDMA11 + no description available + 27 + 1 + read-write + + + TDMA12 + no description available + 28 + 1 + read-write + + + TDMA13 + no description available + 29 + 1 + read-write + + + TDMA14 + no description available + 30 + 1 + read-write + + + TDMA15 + no description available + 31 + 1 + read-write + + + + + DMA_ERR_IRQSIG_EN + DMA Error Interrupt Signal Enable Register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-write + + + RDMA1 + no description available + 1 + 1 + read-write + + + RDMA2 + no description available + 2 + 1 + read-write + + + RDMA3 + no description available + 3 + 1 + read-write + + + RDMA4 + no description available + 4 + 1 + read-write + + + RDMA5 + no description available + 5 + 1 + read-write + + + RDMA6 + no description available + 6 + 1 + read-write + + + RDMA7 + no description available + 7 + 1 + read-write + + + RDMA8 + no description available + 8 + 1 + read-write + + + RDMA9 + no description available + 9 + 1 + read-write + + + RDMA10 + no description available + 10 + 1 + read-write + + + RDMA11 + no description available + 11 + 1 + read-write + + + RDMA12 + no description available + 12 + 1 + read-write + + + RDMA13 + no description available + 13 + 1 + read-write + + + RDMA14 + no description available + 14 + 1 + read-write + + + RDMA15 + no description available + 15 + 1 + read-write + + + TDMA0 + no description available + 16 + 1 + read-write + + + TDMA1 + no description available + 17 + 1 + read-write + + + TDMA2 + no description available + 18 + 1 + read-write + + + TDMA3 + no description available + 19 + 1 + read-write + + + TDMA4 + no description available + 20 + 1 + read-write + + + TDMA5 + no description available + 21 + 1 + read-write + + + TDMA6 + no description available + 22 + 1 + read-write + + + TDMA7 + no description available + 23 + 1 + read-write + + + TDMA8 + no description available + 24 + 1 + read-write + + + TDMA9 + no description available + 25 + 1 + read-write + + + TDMA10 + no description available + 26 + 1 + read-write + + + TDMA11 + no description available + 27 + 1 + read-write + + + TDMA12 + no description available + 28 + 1 + read-write + + + TDMA13 + no description available + 29 + 1 + read-write + + + TDMA14 + no description available + 30 + 1 + read-write + + + TDMA15 + no description available + 31 + 1 + read-write + + + + + DMA_SINGLE_REQ_EN + DMA Single Request Enable Register + 0x1F4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDMA0 + no description available + 0 + 1 + read-only + + + RDMA1 + no description available + 1 + 1 + read-only + + + RDMA2 + no description available + 2 + 1 + read-only + + + RDMA3 + no description available + 3 + 1 + read-only + + + RDMA4 + no description available + 4 + 1 + read-only + + + RDMA5 + no description available + 5 + 1 + read-only + + + RDMA6 + no description available + 6 + 1 + read-only + + + RDMA7 + no description available + 7 + 1 + read-only + + + RDMA8 + no description available + 8 + 1 + read-only + + + RDMA9 + no description available + 9 + 1 + read-only + + + RDMA10 + no description available + 10 + 1 + read-only + + + RDMA11 + no description available + 11 + 1 + read-only + + + RDMA12 + no description available + 12 + 1 + read-only + + + RDMA13 + no description available + 13 + 1 + read-only + + + RDMA14 + no description available + 14 + 1 + read-only + + + RDMA15 + no description available + 15 + 1 + read-only + + + TDMA0 + no description available + 16 + 1 + read-only + + + TDMA1 + no description available + 17 + 1 + read-only + + + TDMA2 + no description available + 18 + 1 + read-only + + + TDMA3 + no description available + 19 + 1 + read-only + + + TDMA4 + no description available + 20 + 1 + read-only + + + TDMA5 + no description available + 21 + 1 + read-only + + + TDMA6 + no description available + 22 + 1 + read-only + + + TDMA7 + no description available + 23 + 1 + read-only + + + TDMA8 + no description available + 24 + 1 + read-only + + + TDMA9 + no description available + 25 + 1 + read-only + + + TDMA10 + no description available + 26 + 1 + read-only + + + TDMA11 + no description available + 27 + 1 + read-only + + + TDMA12 + no description available + 28 + 1 + read-only + + + TDMA13 + no description available + 29 + 1 + read-only + + + TDMA14 + no description available + 30 + 1 + read-only + + + TDMA15 + no description available + 31 + 1 + read-only + + + + + TX_FIFO_SIZE_CONF0 + Tx Fifo Size Configuration Register 0 + 0x200 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + CH8 + no description available + 0 + 4 + read-write + + + 0000 + channel 8 buffer size is 1Dword + #0000 + + + 0001 + channel 8 buffer size is 2Dwords + #0001 + + + 0010 + channel 8 buffer size is 4Dwords + #0010 + + + 0011 + channel 8 buffer size is 8Dwords + #0011 + + + 0100 + channel 8 buffer size is 16Dwords + #0100 + + + 0101 + channel 8 buffer size is 32Dwords + #0101 + + + 0110 + channel 8 buffer size is 64Dwords + #0110 + + + 0111 + channel 8 buffer size is 128Dwords + #0111 + + + 1000 + channel 8 buffer size is 256Dwords + #1000 + + + 1001 + channel 8 buffer size is 512Dwords + #1001 + + + 1010 + channel 8 buffer size is 1024Dwords + #1010 + + + + + CH9 + no description available + 4 + 4 + read-write + + + 0000 + channel 9 buffer size is 1Dword + #0000 + + + 0001 + channel 9 buffer size is 2Dwords + #0001 + + + 0010 + channel 9 buffer size is 4Dwords + #0010 + + + 0011 + channel 9 buffer size is 8Dwords + #0011 + + + 0100 + channel 9 buffer size is 16Dwords + #0100 + + + 0101 + channel 9 buffer size is 32Dwords + #0101 + + + 0110 + channel 9 buffer size is 64Dwords + #0110 + + + 0111 + channel 9 buffer size is 128Dwords + #0111 + + + 1000 + channel 9 buffer size is 256Dwords + #1000 + + + 1001 + channel 9 buffer size is 512Dwords + #1001 + + + 1010 + channel 9 buffer size is 1024Dwords + #1010 + + + + + CH10 + no description available + 8 + 4 + read-write + + + 0000 + channel 10 buffer size is 1Dword + #0000 + + + 0001 + channel 10 buffer size is 2Dwords + #0001 + + + 0010 + channel 10 buffer size is 4Dwords + #0010 + + + 0011 + channel 10 buffer size is 8Dwords + #0011 + + + 0100 + channel 10 buffer size is 16Dwords + #0100 + + + 0101 + channel 10 buffer size is 32Dwords + #0101 + + + 0110 + channel 10 buffer size is 64Dwords + #0110 + + + 0111 + channel 10 buffer size is 128Dwords + #0111 + + + 1000 + channel 10 buffer size is 256Dwords + #1000 + + + 1001 + channel 10 buffer size is 512Dwords + #1001 + + + 1010 + channel 10 buffer size is 1024Dwords + #1010 + + + + + CH11 + no description available + 12 + 4 + read-write + + + 0000 + channel 11 buffer size is 1Dword + #0000 + + + 0001 + channel 11 buffer size is 2Dwords + #0001 + + + 0010 + channel 11 buffer size is 4Dwords + #0010 + + + 0011 + channel 11 buffer size is 8Dwords + #0011 + + + 0100 + channel 11 buffer size is 16Dwords + #0100 + + + 0101 + channel 11 buffer size is 32Dwords + #0101 + + + 0110 + channel 11 buffer size is 64Dwords + #0110 + + + 0111 + channel 11 buffer size is 128Dwords + #0111 + + + 1000 + channel 11 buffer size is 256Dwords + #1000 + + + 1001 + channel 11 buffer size is 512Dwords + #1001 + + + 1010 + channel 11 buffer size is 1024Dwords + #1010 + + + + + CH12 + no description available + 16 + 4 + read-write + + + 0000 + channel 12 buffer size is 1Dword + #0000 + + + 0001 + channel 12 buffer size is 2Dwords + #0001 + + + 0010 + channel 12 buffer size is 4Dwords + #0010 + + + 0011 + channel 12 buffer size is 8Dwords + #0011 + + + 0100 + channel 12 buffer size is 16Dwords + #0100 + + + 0101 + channel 12 buffer size is 32Dwords + #0101 + + + 0110 + channel 12 buffer size is 64Dwords + #0110 + + + 0111 + channel 12 buffer size is 128Dwords + #0111 + + + 1000 + channel 12 buffer size is 256Dwords + #1000 + + + 1001 + channel 12 buffer size is 512Dwords + #1001 + + + 1010 + channel 12 buffer size is 1024Dwords + #1010 + + + + + CH13 + no description available + 20 + 4 + read-write + + + 0000 + channel 13 buffer size is 1Dword + #0000 + + + 0001 + channel 13 buffer size is 2Dwords + #0001 + + + 0010 + channel 13 buffer size is 4Dwords + #0010 + + + 0011 + channel 13 buffer size is 8Dwords + #0011 + + + 0100 + channel 13 buffer size is 16Dwords + #0100 + + + 0101 + channel 13 buffer size is 32Dwords + #0101 + + + 0110 + channel 13 buffer size is 64Dwords + #0110 + + + 0111 + channel 13 buffer size is 128Dwords + #0111 + + + 1000 + channel 13 buffer size is 256Dwords + #1000 + + + 1001 + channel 13 buffer size is 512Dwords + #1001 + + + 1010 + channel 13 buffer size is 1024Dwords + #1010 + + + + + CH14 + no description available + 24 + 4 + read-write + + + 0000 + channel 14 buffer size is 1Dword + #0000 + + + 0001 + channel 14 buffer size is 2Dwords + #0001 + + + 0010 + channel 14 buffer size is 4Dwords + #0010 + + + 0011 + channel 14 buffer size is 8Dwords + #0011 + + + 0100 + channel 14 buffer size is 16Dwords + #0100 + + + 0101 + channel 14 buffer size is 32Dwords + #0101 + + + 0110 + channel 14 buffer size is 64Dwords + #0110 + + + 0111 + channel 14 buffer size is 128Dwords + #0111 + + + 1000 + channel 14 buffer size is 256Dwords + #1000 + + + 1001 + channel 14 buffer size is 512Dwords + #1001 + + + 1010 + channel 14 buffer size is 1024Dwords + #1010 + + + + + CH15 + no description available + 28 + 4 + read-write + + + 0000 + channel 15 buffer size is 1Dword + #0000 + + + 0001 + channel 15 buffer size is 2Dwords + #0001 + + + 0010 + channel 15 buffer size is 4Dwords + #0010 + + + 0011 + channel 15 buffer size is 8Dwords + #0011 + + + 0100 + channel 15 buffer size is 16Dwords + #0100 + + + 0101 + channel 15 buffer size is 32Dwords + #0101 + + + 0110 + channel 15 buffer size is 64Dwords + #0110 + + + 0111 + channel 15 buffer size is 128Dwords + #0111 + + + 1000 + channel 15 buffer size is 256Dwords + #1000 + + + 1001 + channel 15 buffer size is 512Dwords + #1001 + + + 1010 + channel 15 buffer size is 1024Dwords + #1010 + + + + + + + TX_FIFO_SIZE_CONF1 + Tx Fifo Size Configuration Register 1 + 0x204 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + CH0 + no description available + 0 + 4 + read-write + + + 0000 + channel 0 buffer size is 1Dword + #0000 + + + 0001 + channel 0 buffer size is 2Dwords + #0001 + + + 0010 + channel 0 buffer size is 4Dwords + #0010 + + + 0011 + channel 0 buffer size is 8Dwords + #0011 + + + 0100 + channel 0 buffer size is 16Dwords + #0100 + + + 0101 + channel 0 buffer size is 32Dwords + #0101 + + + 0110 + channel 0 buffer size is 64Dwords + #0110 + + + 0111 + channel 0 buffer size is 128Dwords + #0111 + + + 1000 + channel 0 buffer size is 256Dwords + #1000 + + + 1001 + channel 0 buffer size is 512Dwords + #1001 + + + 1010 + channel 0 buffer size is 1024Dwords + #1010 + + + + + CH1 + no description available + 4 + 4 + read-write + + + 0000 + channel 1 buffer size is 1Dword + #0000 + + + 0001 + channel 1 buffer size is 2Dwords + #0001 + + + 0010 + channel 1 buffer size is 4Dwords + #0010 + + + 0011 + channel 1 buffer size is 8Dwords + #0011 + + + 0100 + channel 1 buffer size is 16Dwords + #0100 + + + 0101 + channel 1 buffer size is 32Dwords + #0101 + + + 0110 + channel 1 buffer size is 64Dwords + #0110 + + + 0111 + channel 1 buffer size is 128Dwords + #0111 + + + 1000 + channel 1 buffer size is 256Dwords + #1000 + + + 1001 + channel 1 buffer size is 512Dwords + #1001 + + + 1010 + channel 1 buffer size is 1024Dwords + #1010 + + + + + CH2 + no description available + 8 + 4 + read-write + + + 0000 + channel 2 buffer size is 1Dword + #0000 + + + 0001 + channel 2 buffer size is 2Dwords + #0001 + + + 0010 + channel 2 buffer size is 4Dwords + #0010 + + + 0011 + channel 2 buffer size is 8Dwords + #0011 + + + 0100 + channel 2 buffer size is 16Dwords + #0100 + + + 0101 + channel 2 buffer size is 32Dwords + #0101 + + + 0110 + channel 2 buffer size is 64Dwords + #0110 + + + 0111 + channel 2 buffer size is 128Dwords + #0111 + + + 1000 + channel 2 buffer size is 256Dwords + #1000 + + + 1001 + channel 2 buffer size is 512Dwords + #1001 + + + 1010 + channel 2 buffer size is 1024Dwords + #1010 + + + + + CH3 + no description available + 12 + 4 + read-write + + + 0000 + channel 3 buffer size is 1Dword + #0000 + + + 0001 + channel 3 buffer size is 2Dwords + #0001 + + + 0010 + channel 3 buffer size is 4Dwords + #0010 + + + 0011 + channel 3 buffer size is 8Dwords + #0011 + + + 0100 + channel 3 buffer size is 16Dwords + #0100 + + + 0101 + channel 3 buffer size is 32Dwords + #0101 + + + 0110 + channel 3 buffer size is 64Dwords + #0110 + + + 0111 + channel 3 buffer size is 128Dwords + #0111 + + + 1000 + channel 3 buffer size is 256Dwords + #1000 + + + 1001 + channel 3 buffer size is 512Dwords + #1001 + + + 1010 + channel 3 buffer size is 1024Dwords + #1010 + + + + + CH4 + no description available + 16 + 4 + read-write + + + 0000 + channel 4 buffer size is 1Dword + #0000 + + + 0001 + channel 4 buffer size is 2Dwords + #0001 + + + 0010 + channel 4 buffer size is 4Dwords + #0010 + + + 0011 + channel 4 buffer size is 8Dwords + #0011 + + + 0100 + channel 4 buffer size is 16Dwords + #0100 + + + 0101 + channel 4 buffer size is 32Dwords + #0101 + + + 0110 + channel 4 buffer size is 64Dwords + #0110 + + + 0111 + channel 4 buffer size is 128Dwords + #0111 + + + 1000 + channel 4 buffer size is 256Dwords + #1000 + + + 1001 + channel 4 buffer size is 512Dwords + #1001 + + + 1010 + channel 4 buffer size is 1024Dwords + #1010 + + + + + CH5 + no description available + 20 + 4 + read-write + + + 0000 + channel 5 buffer size is 1Dword + #0000 + + + 0001 + channel 5 buffer size is 2Dwords + #0001 + + + 0010 + channel 5 buffer size is 4Dwords + #0010 + + + 0011 + channel 5 buffer size is 8Dwords + #0011 + + + 0100 + channel 5 buffer size is 16Dwords + #0100 + + + 0101 + channel 5 buffer size is 32Dwords + #0101 + + + 0110 + channel 5 buffer size is 64Dwords + #0110 + + + 0111 + channel 5 buffer size is 128Dwords + #0111 + + + 1000 + channel 5 buffer size is 256Dwords + #1000 + + + 1001 + channel 5 buffer size is 512Dwords + #1001 + + + 1010 + channel 5 buffer size is 1024Dwords + #1010 + + + + + CH6 + no description available + 24 + 4 + read-write + + + 0000 + channel 6 buffer size is 1Dword + #0000 + + + 0001 + channel 6 buffer size is 2Dwords + #0001 + + + 0010 + channel 6 buffer size is 4Dwords + #0010 + + + 0011 + channel 6 buffer size is 8Dwords + #0011 + + + 0100 + channel 6 buffer size is 16Dwords + #0100 + + + 0101 + channel 6 buffer size is 32Dwords + #0101 + + + 0110 + channel 6 buffer size is 64Dwords + #0110 + + + 0111 + channel 6 buffer size is 128Dwords + #0111 + + + 1000 + channel 6 buffer size is 256Dwords + #1000 + + + 1001 + channel 6 buffer size is 512Dwords + #1001 + + + 1010 + channel 6 buffer size is 1024Dwords + #1010 + + + + + CH7 + no description available + 28 + 4 + read-write + + + 0000 + channel 7 buffer size is 1Dword + #0000 + + + 0001 + channel 7 buffer size is 2Dwords + #0001 + + + 0010 + channel 7 buffer size is 4Dwords + #0010 + + + 0011 + channel 7 buffer size is 8Dwords + #0011 + + + 0100 + channel 7 buffer size is 16Dwords + #0100 + + + 0101 + channel 7 buffer size is 32Dwords + #0101 + + + 0110 + channel 7 buffer size is 64Dwords + #0110 + + + 0111 + channel 7 buffer size is 128Dwords + #0111 + + + 1000 + channel 7 buffer size is 256Dwords + #1000 + + + 1001 + channel 7 buffer size is 512Dwords + #1001 + + + 1010 + channel 7 buffer size is 1024Dwords + #1010 + + + + + + + RX_FIFO_SIZE_CONF0 + Rx Fifo Size Configuration Register 0 + 0x208 + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + CH8 + no description available + 0 + 4 + read-write + + + 0000 + channel 8 buffer size is 1Dword + #0000 + + + 0001 + channel 8 buffer size is 2Dwords + #0001 + + + 0010 + channel 8 buffer size is 4Dwords + #0010 + + + 0011 + channel 8 buffer size is 8Dwords + #0011 + + + 0100 + channel 8 buffer size is 16Dwords + #0100 + + + 0101 + channel 8 buffer size is 32Dwords + #0101 + + + 0110 + channel 8 buffer size is 64Dwords + #0110 + + + 0111 + channel 8 buffer size is 128Dwords + #0111 + + + 1000 + channel 8 buffer size is 256Dwords + #1000 + + + 1001 + channel 8 buffer size is 512Dwords + #1001 + + + 1010 + channel 8 buffer size is 1024Dwords + #1010 + + + + + CH9 + no description available + 4 + 4 + read-write + + + 0000 + channel 9 buffer size is 1Dword + #0000 + + + 0001 + channel 9 buffer size is 2Dwords + #0001 + + + 0010 + channel 9 buffer size is 4Dwords + #0010 + + + 0011 + channel 9 buffer size is 8Dwords + #0011 + + + 0100 + channel 9 buffer size is 16Dwords + #0100 + + + 0101 + channel 9 buffer size is 32Dwords + #0101 + + + 0110 + channel 9 buffer size is 64Dwords + #0110 + + + 0111 + channel 9 buffer size is 128Dwords + #0111 + + + 1000 + channel 9 buffer size is 256Dwords + #1000 + + + 1001 + channel 9 buffer size is 512Dwords + #1001 + + + 1010 + channel 9 buffer size is 1024Dwords + #1010 + + + + + CH10 + no description available + 8 + 4 + read-write + + + 0000 + channel 10 buffer size is 1Dword + #0000 + + + 0001 + channel 10 buffer size is 2Dwords + #0001 + + + 0010 + channel 10 buffer size is 4Dwords + #0010 + + + 0011 + channel 10 buffer size is 8Dwords + #0011 + + + 0100 + channel 10 buffer size is 16Dwords + #0100 + + + 0101 + channel 10 buffer size is 32Dwords + #0101 + + + 0110 + channel 10 buffer size is 64Dwords + #0110 + + + 0111 + channel 10 buffer size is 128Dwords + #0111 + + + 1000 + channel 10 buffer size is 256Dwords + #1000 + + + 1001 + channel 10 buffer size is 512Dwords + #1001 + + + 1010 + channel 10 buffer size is 1024Dwords + #1010 + + + + + CH11 + no description available + 12 + 4 + read-write + + + 0000 + channel 11 buffer size is 1Dword + #0000 + + + 0001 + channel 11 buffer size is 2Dwords + #0001 + + + 0010 + channel 11 buffer size is 4Dwords + #0010 + + + 0011 + channel 11 buffer size is 8Dwords + #0011 + + + 0100 + channel 11 buffer size is 16Dwords + #0100 + + + 0101 + channel 11 buffer size is 32Dwords + #0101 + + + 0110 + channel 11 buffer size is 64Dwords + #0110 + + + 0111 + channel 11 buffer size is 128Dwords + #0111 + + + 1000 + channel 11 buffer size is 256Dwords + #1000 + + + 1001 + channel 11 buffer size is 512Dwords + #1001 + + + 1010 + channel 11 buffer size is 1024Dwords + #1010 + + + + + CH12 + no description available + 16 + 4 + read-write + + + 0000 + channel 12 buffer size is 1Dword + #0000 + + + 0001 + channel 12 buffer size is 2Dwords + #0001 + + + 0010 + channel 12 buffer size is 4Dwords + #0010 + + + 0011 + channel 12 buffer size is 8Dwords + #0011 + + + 0100 + channel 12 buffer size is 16Dwords + #0100 + + + 0101 + channel 12 buffer size is 32Dwords + #0101 + + + 0110 + channel 12 buffer size is 64Dwords + #0110 + + + 0111 + channel 12 buffer size is 128Dwords + #0111 + + + 1000 + channel 12 buffer size is 256Dwords + #1000 + + + 1001 + channel 12 buffer size is 512Dwords + #1001 + + + 1010 + channel 12 buffer size is 1024Dwords + #1010 + + + + + CH13 + no description available + 20 + 4 + read-write + + + 0000 + channel 13 buffer size is 1Dword + #0000 + + + 0001 + channel 13 buffer size is 2Dwords + #0001 + + + 0010 + channel 13 buffer size is 4Dwords + #0010 + + + 0011 + channel 13 buffer size is 8Dwords + #0011 + + + 0100 + channel 13 buffer size is 16Dwords + #0100 + + + 0101 + channel 13 buffer size is 32Dwords + #0101 + + + 0110 + channel 13 buffer size is 64Dwords + #0110 + + + 0111 + channel 13 buffer size is 128Dwords + #0111 + + + 1000 + channel 13 buffer size is 256Dwords + #1000 + + + 1001 + channel 13 buffer size is 512Dwords + #1001 + + + 1010 + channel 13 buffer size is 1024Dwords + #1010 + + + 1111 + b1011 Reserved + #1111 + + + + + CH14 + no description available + 24 + 4 + read-write + + + 0000 + channel 14 buffer size is 1Dword + #0000 + + + 0001 + channel 14 buffer size is 2Dwords + #0001 + + + 0010 + channel 14 buffer size is 4Dwords + #0010 + + + 0011 + channel 14 buffer size is 8Dwords + #0011 + + + 0100 + channel 14 buffer size is 16Dwords + #0100 + + + 0101 + channel 14 buffer size is 32Dwords + #0101 + + + 0110 + channel 14 buffer size is 64Dwords + #0110 + + + 0111 + channel 14 buffer size is 128Dwords + #0111 + + + 1000 + channel 14 buffer size is 256Dwords + #1000 + + + 1001 + channel 14 buffer size is 512Dwords + #1001 + + + 1010 + channel 14 buffer size is 1024Dwords + #1010 + + + + + CH15 + no description available + 28 + 4 + read-write + + + 0000 + channel 15 buffer size is 1Dword + #0000 + + + 0001 + channel 15 buffer size is 2Dwords + #0001 + + + 0010 + channel 15 buffer size is 4Dwords + #0010 + + + 0011 + channel 15 buffer size is 8Dwords + #0011 + + + 0100 + channel 15 buffer size is 16Dwords + #0100 + + + 0101 + channel 15 buffer size is 32Dwords + #0101 + + + 0110 + channel 15 buffer size is 64Dwords + #0110 + + + 0111 + channel 15 buffer size is 128Dwords + #0111 + + + 1000 + channel 15 buffer size is 256Dwords + #1000 + + + 1001 + channel 15 buffer size is 512Dwords + #1001 + + + 1010 + channel 15 buffer size is 1024Dwords + #1010 + + + + + + + RX_FIFO_SIZE_CONF1 + Rx Fifo Size Configuration Register 1 + 0x20C + 32 + read-write + 0x55555555 + 0xFFFFFFFF + + + CH0 + no description available + 0 + 4 + read-write + + + 0000 + channel 0 buffer size is 1Dword + #0000 + + + 0001 + channel 0 buffer size is 2Dwords + #0001 + + + 0010 + channel 0 buffer size is 4Dwords + #0010 + + + 0011 + channel 0 buffer size is 8Dwords + #0011 + + + 0100 + channel 0 buffer size is 16Dwords + #0100 + + + 0101 + channel 0 buffer size is 32Dwords + #0101 + + + 0110 + channel 0 buffer size is 64Dwords + #0110 + + + 0111 + channel 0 buffer size is 128Dwords + #0111 + + + 1000 + channel 0 buffer size is 256Dwords + #1000 + + + 1001 + channel 0 buffer size is 512Dwords + #1001 + + + 1010 + channel 0 buffer size is 1024Dwords + #1010 + + + + + CH1 + no description available + 4 + 4 + read-write + + + 0000 + channel 1 buffer size is 1Dword + #0000 + + + 0001 + channel 1 buffer size is 2Dwords + #0001 + + + 0010 + channel 1 buffer size is 4Dwords + #0010 + + + 0011 + channel 1 buffer size is 8Dwords + #0011 + + + 0100 + channel 1 buffer size is 16Dwords + #0100 + + + 0101 + channel 1 buffer size is 32Dwords + #0101 + + + 0110 + channel 1 buffer size is 64Dwords + #0110 + + + 0111 + channel 1 buffer size is 128Dwords + #0111 + + + 1000 + channel 1 buffer size is 256Dwords + #1000 + + + 1001 + channel 1 buffer size is 512Dwords + #1001 + + + 1010 + channel 1 buffer size is 1024Dwords + #1010 + + + + + CH2 + no description available + 8 + 4 + read-write + + + 0000 + channel 2 buffer size is 1Dword + #0000 + + + 0001 + channel 2 buffer size is 2Dwords + #0001 + + + 0010 + channel 2 buffer size is 4Dwords + #0010 + + + 0011 + channel 2 buffer size is 8Dwords + #0011 + + + 0100 + channel 2 buffer size is 16Dwords + #0100 + + + 0101 + channel 2 buffer size is 32Dwords + #0101 + + + 0110 + channel 2 buffer size is 64Dwords + #0110 + + + 0111 + channel 2 buffer size is 128Dwords + #0111 + + + 1000 + channel 2 buffer size is 256Dwords + #1000 + + + 1001 + channel 2 buffer size is 512Dwords + #1001 + + + 1010 + channel 2 buffer size is 1024Dwords + #1010 + + + + + CH3 + no description available + 12 + 4 + read-write + + + 0000 + channel 3 buffer size is 1Dword + #0000 + + + 0001 + channel 3 buffer size is 2Dwords + #0001 + + + 0010 + channel 3 buffer size is 4Dwords + #0010 + + + 0011 + channel 3 buffer size is 8Dwords + #0011 + + + 0100 + channel 3 buffer size is 16Dwords + #0100 + + + 0101 + channel 3 buffer size is 32Dwords + #0101 + + + 0110 + channel 3 buffer size is 64Dwords + #0110 + + + 0111 + channel 3 buffer size is 128Dwords + #0111 + + + 1000 + channel 3 buffer size is 256Dwords + #1000 + + + 1001 + channel 3 buffer size is 512Dwords + #1001 + + + 1010 + channel 3 buffer size is 1024Dwords + #1010 + + + + + CH4 + no description available + 16 + 4 + read-write + + + 0000 + channel 4 buffer size is 1Dword + #0000 + + + 0001 + channel 4 buffer size is 2Dwords + #0001 + + + 0010 + channel 4 buffer size is 4Dwords + #0010 + + + 0011 + channel 4 buffer size is 8Dwords + #0011 + + + 0100 + channel 4 buffer size is 16Dwords + #0100 + + + 0101 + channel 4 buffer size is 32Dwords + #0101 + + + 0110 + channel 4 buffer size is 64Dwords + #0110 + + + 0111 + channel 4 buffer size is 128Dwords + #0111 + + + 1000 + channel 4 buffer size is 256Dwords + #1000 + + + 1001 + channel 4 buffer size is 512Dwords + #1001 + + + 1010 + channel 4 buffer size is 1024Dwords + #1010 + + + + + CH5 + no description available + 20 + 4 + read-write + + + 0000 + channel 5 buffer size is 1Dword + #0000 + + + 0001 + channel 5 buffer size is 2Dwords + #0001 + + + 0010 + channel 5 buffer size is 4Dwords + #0010 + + + 0011 + channel 5 buffer size is 8Dwords + #0011 + + + 0100 + channel 5 buffer size is 16Dwords + #0100 + + + 0101 + channel 5 buffer size is 32Dwords + #0101 + + + 0110 + channel 5 buffer size is 64Dwords + #0110 + + + 0111 + channel 5 buffer size is 128Dwords + #0111 + + + 1000 + channel 5 buffer size is 256Dwords + #1000 + + + 1001 + channel 5 buffer size is 512Dwords + #1001 + + + 1010 + channel 5 buffer size is 1024Dwords + #1010 + + + + + CH6 + no description available + 24 + 4 + read-write + + + 0000 + channel 6 buffer size is 1Dword + #0000 + + + 0001 + channel 6 buffer size is 2Dwords + #0001 + + + 0010 + channel 6 buffer size is 4Dwords + #0010 + + + 0011 + channel 6 buffer size is 8Dwords + #0011 + + + 0100 + channel 6 buffer size is 16Dwords + #0100 + + + 0101 + channel 6 buffer size is 32Dwords + #0101 + + + 0110 + channel 6 buffer size is 64Dwords + #0110 + + + 0111 + channel 6 buffer size is 128Dwords + #0111 + + + 1000 + channel 6 buffer size is 256Dwords + #1000 + + + 1001 + channel 6 buffer size is 512Dwords + #1001 + + + 1010 + channel 6 buffer size is 1024Dwords + #1010 + + + + + CH7 + no description available + 28 + 4 + read-write + + + 0000 + channel 7 buffer size is 1Dword + #0000 + + + 0001 + channel 7 buffer size is 2Dwords + #0001 + + + 0010 + channel 7 buffer size is 4Dwords + #0010 + + + 0011 + channel 7 buffer size is 8Dwords + #0011 + + + 0100 + channel 7 buffer size is 16Dwords + #0100 + + + 0101 + channel 7 buffer size is 32Dwords + #0101 + + + 0110 + channel 7 buffer size is 64Dwords + #0110 + + + 0111 + channel 7 buffer size is 128Dwords + #0111 + + + 1000 + channel 7 buffer size is 256Dwords + #1000 + + + 1001 + channel 7 buffer size is 512Dwords + #1001 + + + 1010 + channel 7 buffer size is 1024Dwords + #1010 + + + + + + + TX_FIFO_STAT + Tx Fifo Status Register + 0x210 + 32 + read-only + 0x55555555 + 0xFFFFFFFF + + + CH0 + no description available + 0 + 2 + read-only + + + 00 + Tx channel 0 fifo not Empty and Full; + #00 + + + 01 + Tx channel 0 fifo Empty; + #01 + + + 10 + Tx channel 0 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH1 + no description available + 2 + 2 + read-only + + + 00 + Tx channel 1 fifo not Empty and Full; + #00 + + + 01 + Tx channel 1 fifo Empty; + #01 + + + 10 + Tx channel 1 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH2 + no description available + 4 + 2 + read-only + + + 00 + Tx channel 2 fifo not Empty and Full; + #00 + + + 01 + Tx channel 2 fifo Empty; + #01 + + + 10 + Tx channel 2 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH3 + no description available + 6 + 2 + read-only + + + 00 + Tx channel 3 fifo not Empty and Full; + #00 + + + 01 + Tx channel 3 fifo Empty; + #01 + + + 10 + Tx channel 3 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH4 + no description available + 8 + 2 + read-only + + + 00 + Tx channel 4 fifo not Empty and Full; + #00 + + + 01 + Tx channel 4 fifo Empty; + #01 + + + 10 + Tx channel 4 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH5 + no description available + 10 + 2 + read-only + + + 00 + Tx channel 5 fifo not Empty and Full; + #00 + + + 01 + Tx channel 5 fifo Empty; + #01 + + + 10 + Tx channel 5 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH6 + no description available + 12 + 2 + read-only + + + 00 + Tx channel 6 fifo not Empty and Full; + #00 + + + 01 + Tx channel 6 fifo Empty; + #01 + + + 10 + Tx channel 6 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH7 + no description available + 14 + 2 + read-only + + + 00 + Tx channel 7 fifo not Empty and Full; + #00 + + + 01 + Tx channel 7 fifo Empty; + #01 + + + 10 + Tx channel 7 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH8 + no description available + 16 + 2 + read-only + + + 00 + Tx channel 8 fifo not Empty and Full; + #00 + + + 01 + Tx channel 8 fifo Empty; + #01 + + + 10 + Tx channel 8 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH9 + no description available + 18 + 2 + read-only + + + 00 + Tx channel 9 fifo not Empty and Full; + #00 + + + 01 + Tx channel 9 fifo Empty; + #01 + + + 10 + Tx channel 9 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH10 + no description available + 20 + 2 + read-only + + + 00 + Tx channel 10 fifo not Empty and Full; + #00 + + + 01 + Tx channel 10 fifo Empty; + #01 + + + 10 + Tx channel 10 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH11 + no description available + 22 + 2 + read-only + + + 00 + Tx channel 11 fifo not Empty and Full; + #00 + + + 01 + Tx channel 11 fifo Empty; + #01 + + + 10 + Tx channel 11 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH12 + no description available + 24 + 2 + read-only + + + 00 + Tx channel 12 fifo not Empty and Full; + #00 + + + 01 + Tx channel 12 fifo Empty; + #01 + + + 10 + Tx channel 12 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH13 + no description available + 26 + 2 + read-only + + + 00 + Tx channel 13 fifo not Empty and Full; + #00 + + + 01 + Tx channel 13 fifo Empty; + #01 + + + 10 + Tx channel 13 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH14 + no description available + 28 + 2 + read-only + + + 00 + Tx channel 14 fifo not Empty and Full; + #00 + + + 01 + Tx channel 14 fifo Empty; + #01 + + + 10 + Tx channel 14 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH15 + no description available + 30 + 2 + read-only + + + 00 + Tx channel 15 fifo not Empty and Full; + #00 + + + 01 + Tx channel 15 fifo Empty; + #01 + + + 10 + Tx channel 15 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + + + RX_FIFO_STAT + Rx Fifo Status Register + 0x214 + 32 + read-only + 0x55555555 + 0xFFFFFFFF + + + CH0 + no description available + 0 + 2 + read-only + + + 00 + Rx channel 0 fifo not Empty and Full; + #00 + + + 01 + Rx channel 0 fifo Empty; + #01 + + + 10 + Rx channel 0 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH1 + no description available + 2 + 2 + read-only + + + 00 + Rx channel 1 fifo not Empty and Full; + #00 + + + 01 + Rx channel 1 fifo Empty; + #01 + + + 10 + Rx channel 1 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH2 + no description available + 4 + 2 + read-only + + + 00 + Rx channel 2 fifo not Empty and Full; + #00 + + + 01 + Rx channel 2 fifo Empty; + #01 + + + 10 + Rx channel 2 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH3 + no description available + 6 + 2 + read-only + + + 00 + Rx channel 3 fifo not Empty and Full; + #00 + + + 01 + Rx channel 3 fifo Empty; + #01 + + + 10 + Rx channel 3 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH4 + no description available + 8 + 2 + read-only + + + 00 + Rx channel 4 fifo not Empty and Full; + #00 + + + 01 + Rx channel 4 fifo Empty; + #01 + + + 10 + Rx channel 4 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH5 + no description available + 10 + 2 + read-only + + + 00 + Rx channel 5 fifo not Empty and Full; + #00 + + + 01 + Rx channel 5 fifo Empty; + #01 + + + 10 + Rx channel 5 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH6 + no description available + 12 + 2 + read-only + + + 00 + Rx channel 6 fifo not Empty and Full; + #00 + + + 01 + Rx channel 6 fifo Empty; + #01 + + + 10 + Rx channel 6 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH7 + no description available + 14 + 2 + read-only + + + 00 + Rx channel 7 fifo not Empty and Full; + #00 + + + 01 + Rx channel 7 fifo Empty; + #01 + + + 10 + Rx channel 7 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH8 + no description available + 16 + 2 + read-only + + + 00 + Rx channel 8 fifo not Empty and Full; + #00 + + + 01 + Rx channel 8 fifo Empty; + #01 + + + 10 + Rx channel 8 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH9 + no description available + 18 + 2 + read-only + + + 00 + Rx channel 9 fifo not Empty and Full; + #00 + + + 01 + Rx channel 9 fifo Empty; + #01 + + + 10 + Rx channel 9 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH10 + no description available + 20 + 2 + read-only + + + 00 + Rx channel 10 fifo not Empty and Full; + #00 + + + 01 + Rx channel 10 fifo Empty; + #01 + + + 10 + Rx channel 10 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH11 + no description available + 22 + 2 + read-only + + + 00 + Rx channel 11 fifo not Empty and Full; + #00 + + + 01 + Rx channel 11 fifo Empty; + #01 + + + 10 + Rx channel 11 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH12 + no description available + 24 + 2 + read-only + + + 00 + Rx channel 12 fifo not Empty and Full; + #00 + + + 01 + Rx channel 12 fifo Empty; + #01 + + + 10 + Rx channel 12 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH13 + no description available + 26 + 2 + read-only + + + 00 + Rx channel 13 fifo not Empty and Full; + #00 + + + 01 + Rx channel 13 fifo Empty; + #01 + + + 10 + Rx channel 13 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH14 + no description available + 28 + 2 + read-only + + + 00 + Rx channel 14 fifo not Empty and Full; + #00 + + + 01 + Rx channel 14 fifo Empty; + #01 + + + 10 + Rx channel 14 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + CH15 + no description available + 30 + 2 + read-only + + + 00 + Rx channel 15 fifo not Empty and Full; + #00 + + + 01 + Rx channel 15 fifo Empty; + #01 + + + 10 + Rx channel 15 fifo Full; + #10 + + + 11 + Reserved. + #11 + + + + + + + AHB_MASTER_CONF + Ahb Master Config Register + 0x228 + 32 + read-write + 0x180 + 0xFFFFFFFF + + + DMA_INSERT_IDLE_NUM + no description available + 0 + 4 + read-write + + + DMA_MODE + no description available + 4 + 2 + read-write + + + 00 + Once AHB master get hgrant from bus, it will set htrans "IDLE" for serval ahb cycles.In the serval cycles, once it found dataport is accessing fifo, it will release bus. + #00 + + + 01 + Once AHB master get hgrant from bus, it will set htrans "IDLE" for serval ahb cycles.After the serval cycles, once it found dataport is accessing fifo, it will keep on sending "IDLE" out untill dataport finish accessing fifo. + #01 + + + 1x + Once AHB master get hgrant from bus, dataport can not access fifo untill a dma operation done. + #1x + + + + + DP_HOLD_CYCLE + no description available + 6 + 4 + read-write + + + RESERVED + no description available + 10 + 22 + read-only + + + + + TX_BREAK_LEN + TX Break Length Register + 0x22C + 32 + read-write + 0x25 + 0xFFFFFFFF + + + COUNT + no description available + 0 + 6 + read-write + + + RESERVED + no description available + 6 + 26 + read-only + + + + + + + IPU + IPU Registers + IPU_ + 0x2600000 + + 0 + 0x68024 + registers + + + + CONF + Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_EN + no description available + 0 + 1 + read-write + + + 0 + CSI0 is disabled + #0 + + + 1 + CSI0 is enabled + #1 + + + + + CSI1_EN + no description available + 1 + 1 + read-write + + + 0 + CSI1 is disabled + #0 + + + 1 + CSI1 is enabled + #1 + + + + + IC_EN + no description available + 2 + 1 + read-write + + + 0 + IC is disabled + #0 + + + 1 + IC is enabled + #1 + + + + + IRT_EN + no description available + 3 + 1 + read-write + + + 0 + IRT is disabled + #0 + + + 1 + IRT is enabled + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + DP_EN + no description available + 5 + 1 + read-write + + + 0 + DP is disabled + #0 + + + 1 + DP is enabled + #1 + + + + + DI0_EN + no description available + 6 + 1 + read-write + + + 0 + DI0 is disabled + #0 + + + 1 + DI0 is enabled + #1 + + + + + DI1_EN + no description available + 7 + 1 + read-write + + + 0 + DI1 is disabled + #0 + + + 1 + DI1 is enabled + #1 + + + + + SMFC_EN + no description available + 8 + 1 + read-write + + + 0 + SMFC is disabled + #0 + + + 1 + SMFC is enabled + #1 + + + + + DC_EN + no description available + 9 + 1 + read-write + + + 0 + DC is disabled + #0 + + + 1 + DC is enabled + #1 + + + + + DMFC_EN + no description available + 10 + 1 + read-write + + + 0 + DMFC is disabled + #0 + + + 1 + DMFC is enabled + #1 + + + + + SISG_EN + no description available + 11 + 1 + read-write + + + 0 + SISG is disabled + #0 + + + 1 + SISG is enabled + #1 + + + + + VDI_EN + no description available + 12 + 1 + read-write + + + 0 + VDIC is disabled + #0 + + + 1 + VDIC is enabled + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + IPU_DIAGBUS_MODE + no description available + 16 + 5 + read-write + + + IPU_DIAGBUS_ON + no description available + 21 + 1 + read-write + + + 1 + diagnostics bus is on + #1 + + + 0 + diagnostics bus is off + #0 + + + + + IDMAC_DISABLE + no description available + 22 + 1 + read-write + + + 0 + IDMAC is enabled + #0 + + + 1 + IDMAC is disabled + #1 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + RESERVED + no description available + 24 + 1 + read-only + + + IC_DMFC_SEL + no description available + 25 + 1 + read-write + + + 0 + DMAIC_1 (channel 21) is routed to the IDMAC + #0 + + + 1 + DMAIC_1 (channel 21) is routed to DMFCIn case DMFC was selected the IDMAC_CH_EN[21] must be clear. + #1 + + + + + IC_DMFC_SYNC + no description available + 26 + 1 + read-write + + + 0 + async flow + #0 + + + 1 + Sync flow + #1 + + + + + VDI_DMFC_SYNC + no description available + 27 + 1 + read-write + + + 0 + the flow is disabled + #0 + + + 1 + the flow is enabled + #1 + + + + + CSI0_DATA_SOURCE + no description available + 28 + 1 + read-write + + + 0 + Parallel interface is connected to CSI0 + #0 + + + 1 + MCT (MIPI) is connected to CSI0 + #1 + + + + + CSI1_DATA_SOURCE + no description available + 29 + 1 + read-write + + + 0 + Parallel interface is connected to CSI1 + #0 + + + 1 + MCT (MIPI) is connected to CSI1 + #1 + + + + + IC_INPUT + no description available + 30 + 1 + read-write + + + 0 + CSI0/1 is selected; In order to select between the CSIs use the CSI_SEL bit. + #0 + + + 1 + VDI + #1 + + + + + CSI_SEL + no description available + 31 + 1 + read-write + + + 0 + CSI0 is selected + #0 + + + 1 + CSI1 is selected + #1 + + + + + + + SISG_CTRL0 + SISG Control 0 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + VSYNC_RST_CNT + no description available + 0 + 1 + read-write + + + 1 + The counters are stopped at VSYNC + #1 + + + 0 + The counters are stooped when the counters reach the VAL_STOP_SISG_COUNTER value. + #0 + + + + + NO_VSYNC_2_STRT_CNT + no description available + 1 + 3 + read-write + + + VAL_STOP_SISG_COUNTER + no description available + 4 + 25 + read-write + + + MCU_ACTV_TRIG + no description available + 29 + 1 + read-write + + + EXT_ACTV + no description available + 30 + 1 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + SISG_CTRL1 + SISG Control 1 Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SISG_STROBE_CNT + no description available + 0 + 5 + read-write + + + RESERVED + no description available + 5 + 3 + read-only + + + SISG_OUT_POL + no description available + 8 + 6 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + SISG_SET_i + SISG Set<i> Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SISG_SET_i + no description available + 0 + 25 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + SISG_CLR_i + SISG Clear <i> Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SISG_CLEAR_i + no description available + 0 + 25 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + INT_CTRL_1 + Interrupt Control Register 1 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOF_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_2 + Interrupt Control Register 2 + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOF_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_3 + Interrupt Control Register 3 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_NFACK_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_4 + Interrupt Control Register 4 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFACK_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_5 + Interrupt Control Register 5 + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_NFB4EOF_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_6 + Interrupt Control Register 6 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_NFB4EOF_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_7 + Interrupt Control Register 7 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 19 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_8 + Interrupt Control Register 8 + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 13 + 6 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOS_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_9 + Interrupt Control Register 9 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_FIFO1_OVF_EN + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 1 + 25 + read-only + + + IC_BAYER_BUF_OVF_EN + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_ENC_BUF_OVF_EN + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_VF_BUF_OVF_EN + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + CSI0_PUPE_EN + no description available + 30 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + CSI1_PUPE_EN + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_10 + Interrupt Control Register 10 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMFC0_FRM_LOST_EN + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + SMFC1_FRM_LOST_EN + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + SMFC2_FRM_LOST_EN + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + SMFC3_FRM_LOST_EN + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 12 + read-only + + + DC_TEARING_ERR_1_EN + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_TEARING_ERR_2_EN + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_TEARING_ERR_6_EN + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_SYNC_DISP_ERR_EN + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI1_SYNC_DISP_ERR_EN + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_TIME_OUT_ERR_EN + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI1_TIME_OUT_ERR_EN + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + IC_VF_FRM_LOST_ERR_EN + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_ENC_FRM_LOST_ERR_EN + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_BAYER_FRM_LOST_ERR_EN + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + NON_PRIVILEGED_ACC_ERR_EN + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + AXIW_ERR_EN + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + AXIR_ERR_EN + no description available + 30 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + INT_CTRL_11 + Interrupt Control Register 11 + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOBND_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 6 + 5 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 13 + 7 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 23 + 2 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_12 + Interrupt Control Register 12 + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_EOBND_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_13 + Interrupt Control Register 13 + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_TH_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_14 + Interrupt Control Register 14 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IDMAC_TH_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + INT_CTRL_15 + Interrupt Control Register15 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + SNOOPING1_INT_EN + no description available + 0 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + SNOOPING2_INT_EN + no description available + 1 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_SF_START_EN + no description available + 2 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_SF_END_EN + no description available + 3 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_ASF_START_EN + no description available + 4 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_ASF_END_EN + no description available + 5 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_SF_BRAKE_EN + no description available + 6 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DP_ASF_BRAKE_EN + no description available + 7 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_0_EN + no description available + 8 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_1_EN + no description available + 9 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_2_EN + no description available + 10 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_3_EN + no description available + 11 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_4_EN + no description available + 12 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_FC_6_EN + no description available + 13 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI_VSYNC_PRE_0_EN + no description available + 14 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI_VSYNC_PRE_1_EN + no description available + 15 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_DP_START_EN + no description available + 16 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DC_ASYNC_STOP_EN + no description available + 17 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_0_EN + no description available + 18 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_1_EN + no description available + 19 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_2_EN + no description available + 20 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_3_EN + no description available + 21 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_4_EN + no description available + 22 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_5_EN + no description available + 23 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_6_EN + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_7_EN + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_8_EN + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_9_EN + no description available + 27 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI0_CNT_EN_PRE_10_EN + no description available + 28 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI1_DISP_CLK_EN_PRE_EN + no description available + 29 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI1_CNT_EN_PRE_3_EN + no description available + 30 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + DI1_CNT_EN_PRE_8_EN + no description available + 31 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + + + SDMA_EVENT_1 + SDMA Event Control Register 1 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOF_SDMA_EN_0 + no description available + 0 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_1 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_2 + no description available + 2 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_3 + no description available + 3 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_5 + no description available + 5 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_8 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_9 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_10 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_11 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_12 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_13 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_14 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_15 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_17 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_18 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_19 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_20 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_21 + no description available + 21 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_22 + no description available + 22 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_23 + no description available + 23 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_24 + no description available + 24 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_25 + no description available + 25 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_26 + no description available + 26 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_27 + no description available + 27 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_28 + no description available + 28 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_29 + no description available + 29 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_31 + no description available + 31 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_2 + SDMA Event Control Register 2 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_33 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_40 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_41 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_42 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_43 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_44 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_45 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_46 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_47 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_48 + no description available + 16 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_49 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_50 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_51 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOF_SDMA_EN_52 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_3 + SDMA Event Control Register 3 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_NFACK_SDMA_EN_0 + no description available + 0 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_1 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_2 + no description available + 2 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_3 + no description available + 3 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_5 + no description available + 5 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_8 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_9 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_10 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_11 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_12 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_13 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_14 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_15 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_17 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_18 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_19 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_20 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_21 + no description available + 21 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_22 + no description available + 22 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_23 + no description available + 23 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_24 + no description available + 24 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_25 + no description available + 25 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_26 + no description available + 26 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_27 + no description available + 27 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_28 + no description available + 28 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_29 + no description available + 29 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_31 + no description available + 31 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_4 + SDMA Event Control Register 4 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_33 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_40 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_41 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_42 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_43 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_44 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_45 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_46 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_47 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_48 + no description available + 16 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_49 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_50 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_51 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_NFACK_SDMA_EN_52 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_7 + SDMA Event Control Register 7 + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 19 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_19 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_23 + no description available + 23 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_24 + no description available + 24 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_25 + no description available + 25 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_26 + no description available + 26 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_27 + no description available + 27 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_28 + no description available + 28 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_29 + no description available + 29 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_31 + no description available + 31 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_8 + SDMA Event Control Register 8 + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_33 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_41 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_42 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_43 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_44 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 13 + 6 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_51 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOS_SDMA_EN_52 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_11 + SDMA Event Control Register 11 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOBND_SDMA_EN_0 + no description available + 0 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_1 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_2 + no description available + 2 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_3 + no description available + 3 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_5 + no description available + 5 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 6 + 5 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_11 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_12 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 13 + 7 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_20 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_21 + no description available + 21 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_22 + no description available + 22 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 23 + 2 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_25 + no description available + 25 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_26 + no description available + 26 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_12 + SDMA Event Control Register 12 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_45 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_46 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_47 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_48 + no description available + 16 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_49 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_EOBND_SDMA_EN_50 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_13 + SDMA Event Control Register 13 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_TH_SDMA_EN_0 + no description available + 0 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_1 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_2 + no description available + 2 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_3 + no description available + 3 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_5 + no description available + 5 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_8 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_9 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_10 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_11 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_12 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_13 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_14 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_15 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_17 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_18 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_19 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_20 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_21 + no description available + 21 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_22 + no description available + 22 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_23 + no description available + 23 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_24 + no description available + 24 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_25 + no description available + 25 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_26 + no description available + 26 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_27 + no description available + 27 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_28 + no description available + 28 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_29 + no description available + 29 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_31 + no description available + 31 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SDMA_EVENT_14 + SDMA Event Control Register 14 + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_33 + no description available + 1 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_40 + no description available + 8 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_41 + no description available + 9 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_42 + no description available + 10 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_43 + no description available + 11 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_44 + no description available + 12 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_45 + no description available + 13 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_46 + no description available + 14 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_47 + no description available + 15 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_48 + no description available + 16 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_49 + no description available + 17 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_50 + no description available + 18 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_51 + no description available + 19 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + IDMAC_TH_SDMA_EN_52 + no description available + 20 + 1 + read-write + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + SDMA event is disabled. + #0 + + + 1 + SDMA event is enabled. + #1 + + + + + + + SRM_PRI1 + Shadow Registers Memory Priority 1 Register + 0xA0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + CSI1_SRM_PRI + no description available + 0 + 3 + read-write + + + CSI1_SRM_MODE + no description available + 3 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the CSI0's region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + RESERVED + no description available + 5 + 3 + read-only + + + CSI0_SRM_PRI + no description available + 8 + 3 + read-write + + + CSI0_SRM_MODE + no description available + 11 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the CSI1's region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM Platform. The Register will be update now + #11 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + SRM_PRI2 + Shadow Registers Memory Priority 2 Register + 0xA4 + 32 + read-write + 0x6050803 + 0xFFFFFFFF + + + DP_SRM_PRI + no description available + 0 + 3 + read-write + + + DP_S_SRM_MODE + no description available + 3 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DP sync flow region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done on the next frame. + #01 + + + 10 + Reserved + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + DP_A0_SRM_MODE + no description available + 5 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DP Async flow #0 region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + DP_A1_SRM_MODE + no description available + 7 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DP Async flow #1 region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + DC_SRM_PRI + no description available + 9 + 3 + read-write + + + DC_2_SRM_MODE + no description available + 12 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DC Group #2's region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + DC_6_SRM_MODE + no description available + 14 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DC Group #6's region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + DI0_SRM_PRI + no description available + 16 + 3 + read-write + + + DI0_SRM_MCU_USE + no description available + 19 + 2 + read-write + + + 1 + DI0 SRM is currently updated by the ARM platform + #1 + + + 0 + DI0 SRM s currently not updated by the ARM platform + #0 + + + + + RESERVED + no description available + 21 + 3 + read-only + + + DI1_SRM_PRI + no description available + 24 + 3 + read-write + + + DI1_SRM_MODE + no description available + 27 + 2 + read-write + + + 00 + Automatic swapping is disabled; ARM platform is allowed to access the DI1 region in the RAM + #00 + + + 01 + The SRM logic is controlled by the FSU. The update will be done of the next frame. + #01 + + + 10 + The SRM logic is controlled by the FSU. Registers are swapped continuously frame by frame + #10 + + + 11 + Update now. The SRM is controlled by the ARM platform. The Register will be update now + #11 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + FS_PROC_FLOW1 + FSU Processing Flow 1 Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRPENC_ROT_SRC_SEL + no description available + 0 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture1 (smfc1) + #0010 + + + 0011 + capture2 (smfc2) + #0011 + + + 0100 + capture3 (smfc3) + #0100 + + + 0101 + IC direct (cb7) + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + encoding + #0111 + + + 1000 + Reserved + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + PRPVF_ROT_SRC_SEL + no description available + 8 + 4 + read-write + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture1 (smfc1) + #0010 + + + 0011 + capture2 (smfc2) + #0011 + + + 0100 + capture3 (smfc3) + #0100 + + + 0101 + IC direct (cb7) + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + Reserved + #0111 + + + 1000 + View-finder + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + PP_SRC_SEL + no description available + 12 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + capture2 (smfc2) + #0011 + + + 0100 + Reserved + #0100 + + + 0101 + Reserved + #0101 + + + 0110 + Rotation for post-processing + #0110 + + + 0111 + Reserved + #0111 + + + 1000 + Reserved + #1000 + + + 1000 + VDOA + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + PP_ROT_SRC_SEL + no description available + 16 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + capture2 (smfc2) + #0011 + + + 0100 + Reserved + #0100 + + + 0101 + Post-processing + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + Reserved + #0111 + + + 1000 + Reserved + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + VDI1_SRC_SEL + no description available + 20 + 2 + read-write + + + 00 + ARM platform + #00 + + + 01 + IRT viewfinder + #01 + + + 10 + IRT playback + #10 + + + 11 + post-processing + #11 + + + + + VDI3_SRC_SEL + no description available + 22 + 2 + read-write + + + 00 + ARM platformThis field is relevant only if the VDIC works in combining mode (VDI_CMB_EN bit is set) + #00 + + + 01 + IRT viewfinder (ch 49) + #01 + + + 10 + IRT playback (ch 50) + #10 + + + 11 + post-processing (ch 22) + #11 + + + + + PRP_SRC_SEL + no description available + 24 + 4 + read-write + + + 0001 + capture0 (smfc0) + #0001 + + + 0011 + capture2 (smfc2) + #0011 + + + 0101 + IC direct (cb7) + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + Reserved + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + VDI_SRC_SEL + no description available + 28 + 2 + read-write + + + 00 + ARM platform + #00 + + + 01 + CSI direct (cb7) + #01 + + + 10 + Reserved + #10 + + + 10 + VDOA + #10 + + + 11 + Reserved + #11 + + + + + ENC_IN_VALID + no description available + 30 + 1 + read-write + + + 0 + Encoding should skip buffer in memory. + #0 + + + 1 + Encoding should use buffer in memory. + #1 + + + + + VF_IN_VALID + no description available + 31 + 1 + read-write + + + 0 + View-finder should skip buffer in memory. + #0 + + + 1 + View-finder should use buffer in memory. + #1 + + + + + + + FS_PROC_FLOW2 + FSU Processing Flow 2 Register + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + PRP_ENC_DEST_SEL + no description available + 0 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + IRT Encoding + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + Reserved + #0011 + + + 0100 + Reserved + #0100 + + + 0101 + Reserved + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PRPVF_DEST_SEL + no description available + 4 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + IRT viewfinder + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + Reserved + #0011 + + + 0100 + Reserved + #0100 + + + 0101 + Reserved + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PRPVF_ROT_DEST_SEL + no description available + 8 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + Reserved + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + VDI_PLANE3 (Ch 25) + #0011 + + + 0100 + VDI_PLANE1 (Ch 26) + #0100 + + + 0101 + IC Pre Processing + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PP_DEST_SEL + no description available + 12 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + Reserved + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + IRT playback + #0011 + + + 0100 + VDI_PLANE3 (Ch 25) + #0100 + + + 0101 + VDI_PLANE1 (Ch 26) + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PP_ROT_DEST_SEL + no description available + 16 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + Reserved + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + Reserved + #0011 + + + 0100 + IC Playback (Post Processing) + #0100 + + + 0101 + VDI_PLANE3 (Ch 25) + #0101 + + + 0110 + VDI_PLANE1 (Ch 26) + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PRPENC_ROT_DEST_SEL + no description available + 20 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + Reserved + #0001 + + + 0010 + Reserved + #0010 + + + 0011 + Reserved + #0011 + + + 0100 + Reserved + #0100 + + + 0101 + IC Pre Processing + #0101 + + + 0110 + Reserved + #0110 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + PRP_DEST_SEL + no description available + 24 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + IC input buffer (ch12) + #0001 + + + 0010 + PP (ch11) + #0010 + + + 0011 + PP_ROT (ch47) + #0011 + + + 0100 + DC1 (ch28) + #0100 + + + 0101 + DC2 (ch41) + #0101 + + + 0110 + DP_ASYNC1 (ch24) + #0110 + + + 0111 + DP_ASYNC0 (ch29) + #0111 + + + 1000 + DP_SYNC1 (ch27) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + Alt DC2 (ch41) + #1010 + + + 1011 + Alt DP_ASYNC1 (ch24) + #1011 + + + 1100 + Alt DP_ASYNC0 (ch29) + #1100 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + FS_PROC_FLOW3 + FSU Processing Flow 3 Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMFC0_DEST_SEL + no description available + 0 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + IRT Encoding + #0001 + + + 0010 + IRT viewfinder + #0010 + + + 0011 + IRT playback + #0011 + + + 0100 + IC Playback (Post Processing) + #0100 + + + 0101 + IC Pre Processing + #0101 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + SMFC1_DEST_SEL + no description available + 4 + 3 + read-write + + + 000 + ARM platform + #000 + + + 001 + IRT Encoding + #001 + + + 010 + IRT viewfinder + #010 + + + 011 + IRT playback + #011 + + + 100 + IC Playback (Post Processing) + #100 + + + 101 + IC Pre Processing + #101 + + + 111 + Reserved + #111 + + + + + SMFC2_DEST_SEL + no description available + 7 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + IRT Encoding + #0001 + + + 0010 + IRT viewfinder + #0010 + + + 0011 + IRT playback + #0011 + + + 0100 + IC Playback (Post Processing) + #0100 + + + 0101 + IC Pre Processing + #0101 + + + 0111 + DC1 (ch28) + #0111 + + + 1000 + DC2 (ch41) + #1000 + + + 1001 + DP_SYNC0 (ch23) + #1001 + + + 1010 + DP_SYNC1 (ch27) + #1010 + + + 1011 + DP_ASYNC1 (ch24) + #1011 + + + 1100 + DP_ASYNC0 (ch29) + #1100 + + + 1101 + Alt DC2 (ch41) + #1101 + + + 1110 + Alt DP_ASYNC1 (ch24) + #1110 + + + 1111 + Alt DP_ASYNC0 (ch29) + #1111 + + + + + SMFC3_DEST_SEL + no description available + 11 + 3 + read-write + + + 000 + ARM platform + #000 + + + 001 + IRT Encoding + #001 + + + 010 + IRT viewfinder + #010 + + + 011 + IRT playback + #011 + + + 100 + IC Playback (Post Processing) + #100 + + + 101 + IC Pre Processing + #101 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 14 + 2 + read-only + + + VDOA_DEST_SEL + no description available + 16 + 2 + read-write + + + 00 + disabled + #00 + + + 01 + IC Playback (Post Processing) + #01 + + + 10 + VDI (ch8,ch9 & ch10 or ch9 according to VDI_MOT_SEL settings) + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + EXT_SRC1_DEST_SEL + no description available + 20 + 2 + read-write + + + 00 + disabled + #00 + + + 01 + DP_SYNC0 (ch23) + #01 + + + 10 + DP_SYNC1 (ch27) + #10 + + + 11 + DC1 (ch28) + #11 + + + + + EXT_SRC2_DEST_SEL + no description available + 22 + 2 + read-write + + + 00 + disabled + #00 + + + 01 + DP_SYNC0 (ch23) + #01 + + + 10 + DP_SYNC1 (ch27) + #10 + + + 11 + DC1 (ch28) + #11 + + + + + VPU_DEST_SEL + no description available + 24 + 2 + read-write + + + 00 + disabled + #00 + + + 01 + capture0 (smfc0) (ch0) + #01 + + + 10 + capture2 (smfc2) (ch2) + #10 + + + 11 + IC viewfinder (ch21) + #11 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + FS_DISP_FLOW1 + FSU Displaying Flow 1 Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_SYNC0_SRC_SEL + no description available + 0 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DP_SYNC1_SRC_SEL + no description available + 4 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DP_ASYNC0_SRC_SEL + no description available + 8 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DP_ASYNC1_SRC_SEL + no description available + 12 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DC2_SRC_SEL + no description available + 16 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DC1_SRC_SEL + no description available + 20 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + External source #1 (e.g. an external block like GPU) + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + External source #2 (e.g. an external block like GPU) + #1111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + FS_DISP_FLOW2 + FSU Displaying Flow 2 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_ASYNC0_ALT_SRC_SEL + no description available + 0 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + DP_ASYNC1_ALT_SRC_SEL + no description available + 4 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + DC2_ALT_SRC_SEL + no description available + 16 + 4 + read-write + + + 0000 + ARM platform + #0000 + + + 0001 + capture0 (smfc0) + #0001 + + + 0010 + capture2 (smfc2) + #0010 + + + 0011 + IC encoding + #0011 + + + 0100 + IC viewfinder + #0100 + + + 0101 + IC playback + #0101 + + + 0110 + IRT Encoding + #0110 + + + 0111 + IRT viewfinder + #0111 + + + 1000 + IRT playback + #1000 + + + 1001 + Reserved + #1001 + + + 1010 + Reserved + #1010 + + + 1011 + autoref + #1011 + + + 1100 + autoref+snoop1 + #1100 + + + 1101 + autoref+snoop2 + #1101 + + + 1110 + snoop1 + #1110 + + + 1111 + snoop2 + #1111 + + + + + RESERVED + no description available + 20 + 12 + read-only + + + + + SKIP + SKIP Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI_MAX_RATIO_SKIP_IC_ENC + no description available + 0 + 3 + read-write + + + CSI_SKIP_IC_ENC + no description available + 3 + 5 + read-write + + + CSI_MAX_RATIO_SKIP_IC_VF + no description available + 8 + 3 + read-write + + + CSI_SKIP_IC_VF + no description available + 11 + 5 + read-write + + + VDI_MAX_RATIO_SKIP + no description available + 16 + 4 + read-write + + + VDI_SKIP + no description available + 20 + 12 + read-write + + + + + DISP_ALT_CONF + Display Alternate Configuration Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 32 + read-only + + + + + DISP_GEN + Display General Control Register + 0xC4 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + DI0_DUAL_MODE + no description available + 0 + 1 + read-write + + + 1 + DI0 operates in dual mode + #1 + + + 0 + DI0 is not in dual mode + #0 + + + + + DI1_DUAL_MODE + no description available + 1 + 1 + read-write + + + 1 + DI1 operates in dual mode + #1 + + + 0 + DI1 is not in dual mode + #0 + + + + + DC2_DOUBLE_FLOW + no description available + 2 + 1 + read-write + + + 1 + 2 flows are handled via DC2 + #1 + + + 0 + single flow is handled via DC2 + #0 + + + + + DP_ASYNC_DOUBLE_FLOW + no description available + 3 + 1 + read-write + + + 1 + 2 flows are handled via DP + #1 + + + 0 + single flow is handled via DP + #0 + + + + + DP_FG_EN_ASYNC0 + no description available + 4 + 1 + read-write + + + 1 + partial plane channel is enabled. + #1 + + + 0 + partial plane channel is disabled. + #0 + + + + + DP_FG_EN_ASYNC1 + no description available + 5 + 1 + read-write + + + 1 + partial plane channel is enabled. + #1 + + + 0 + partial plane channel is disabled. + #0 + + + + + DP_PIPE_CLR + no description available + 6 + 1 + write-only + + + 1 + Clear the internal pipe of the DP + #1 + + + 0 + Idle - does nothing + #0 + + + + + RESERVED + no description available + 7 + 9 + read-only + + + MCU_DI_ID_8 + no description available + 16 + 1 + read-write + + + 1 + ARM platform accesses DC's channel #8 via DI1. + #1 + + + 0 + ARM platform accesses DC's channel #8 via DI0. + #0 + + + + + MCU_DI_ID_9 + no description available + 17 + 1 + read-write + + + 1 + ARM platform accesses DC's channel #9 via DI1. + #1 + + + 0 + ARM platform accesses DC's channel #9 via DI0. + #0 + + + + + MCU_T + no description available + 18 + 4 + read-write + + + MCU_MAX_BURST_STOP + no description available + 22 + 1 + read-write + + + 1 + The maximum unspecified burst length is 8-beat + #1 + + + 0 + The unspecified burst length is unlimited + #0 + + + + + CSI_VSYNC_DEST + no description available + 23 + 1 + read-write + + + 1 + csi1_vsync is connected to DI0; csi0_vsync is connected to DI1 + #1 + + + 0 + csi0_vsync is connected to DI0; csi1_vsync is connected to DI1 + #0 + + + + + DI0_COUNTER_RELEASE + no description available + 24 + 1 + read-write + + + 1 + counter is released and running + #1 + + + 0 + counter is cleared and stopped + #0 + + + + + DI1_COUNTER_RELEASE + no description available + 25 + 1 + read-write + + + 1 + counter is released and running + #1 + + + 0 + counter is cleared and stopped + #0 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + DISP_ALT1 + Display Alternate Flow Control Register 1 + 0xC8 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + run_value_m1_alt_0 + no description available + 0 + 12 + read-write + + + cnt_clr_sel_alt_0 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + cnt_auto_reload_alt_0 + no description available + 15 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the step_repeat_alt_0 field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the step_repeat_alt_0 field + #0 + + + + + step_repeat_alt_0 + no description available + 16 + 12 + read-write + + + sel_alt_0 + no description available + 28 + 4 + read-write + + + 0001 + instead of counter 1 + #0001 + + + 0010 + instead of counter 2 + #0010 + + + 1000 + instead of counter 8 + #1000 + + + + + + + DISP_ALT2 + Display Alternate Flow Control Register 2 + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + offset_value_alt_0 + no description available + 0 + 12 + read-write + + + offset_resolution_alt_0 + no description available + 12 + 3 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + run_resolution_alt_0 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + DISP_ALT3 + Display Alternate Flow Control Register 3 + 0xD0 + 32 + read-write + 0x400000 + 0xFFFFFFFF + + + run_value_m1_alt_1 + no description available + 0 + 12 + read-write + + + cnt_clr_sel_alt_1 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + cnt_auto_reload_alt_1 + no description available + 15 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the step_repeat_alt_0 field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the step_repeat_alt_0 field + #0 + + + + + step_repeat_alt_1 + no description available + 16 + 12 + read-write + + + sel_alt_1 + no description available + 28 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + instead of counter 1 + #0001 + + + 0010 + instead of counter 2 + #0010 + + + 1000 + instead of counter 8 + #1000 + + + + + + + DISP_ALT4 + Display Alternate Flow Control Register 4 + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + offset_value_alt_1 + no description available + 0 + 12 + read-write + + + offset_resolution_alt_1 + no description available + 12 + 3 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + run_resolution_alt_1 + no description available + 16 + 3 + read-write + + + RESERVED + no description available + 19 + 13 + read-only + + + + + MEM_RST + Memory Reset Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + RST_MEM_EN + no description available + 0 + 23 + read-write + + + RESERVED + no description available + 23 + 8 + read-only + + + RST_MEM_START + no description available + 31 + 1 + read-write + + + 1 + The memory reset mechanism is activated and busy + #1 + + + 0 + Idle, the memory reset mechanism is not working. + #0 + + + + + + + PM + Power Modes Control Register + 0xE0 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + DI0_CLK_PERIOD_0 + no description available + 0 + 7 + read-write + + + DI0_CLK_PERIOD_1 + no description available + 7 + 7 + read-write + + + DI0_SRM_CLOCK_CHANGE_MODE + no description available + 14 + 1 + read-write + + + 1 + SRM clock change mode is enabled; the next clock change will be done by updating the DI settings from the SRM + #1 + + + 0 + SRM clock change mode is disabled. + #0 + + + + + CLCOK_MODE_STAT + no description available + 15 + 1 + read-only + + + 1 + current clock mode is 1 + #1 + + + 0 + current clock mode is 0 + #0 + + + + + DI1_CLK_PERIOD_0 + no description available + 16 + 7 + read-write + + + DI1_CLK_PERIOD_1 + no description available + 23 + 7 + read-write + + + DI1_SRM_CLOCK_CHANGE_MODE + no description available + 30 + 1 + read-write + + + 1 + SRM clock change mode is enabled; the next clock change will be done by updating the DI settings from the SRM + #1 + + + 0 + SRM clock change mode is disabled. + #0 + + + + + LPSR_MODE + no description available + 31 + 1 + read-write + + + 1 + Next low power mode will be LPSR + #1 + + + 0 + Next low power mode is not LPSR + #0 + + + + + + + GPR + General Purpose Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPU_GPn + no description available + 0 + 20 + read-write + + + IPU_CH_BUF2_RDY0_CLR + no description available + 20 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF2_RDY0 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF2_RDY0 is w1s register + #0 + + + + + IPU_CH_BUF2_RDY1_CLR + no description available + 21 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF2_RDY1 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF2_RDY1 is w1s register + #0 + + + + + IPU_DI0_CLK_CHANGE_ACK_DIS + no description available + 22 + 1 + read-write + + + 1 + clock change mechanism is disabled. DI automatically acknowledges a clock change request + #1 + + + 0 + clock change mechanism is disabled. DI performs the clock change procedure + #0 + + + + + IPU_DI1_CLK_CHANGE_ACK_DIS + no description available + 23 + 1 + read-write + + + 1 + clock change mechanism is disabled. DI automatically acknowledges a clock change request + #1 + + + 0 + clock change mechanism is disabled. DI performs the clock change procedure + #0 + + + + + IPU_ALT_CH_BUF0_RDY0_CLR + no description available + 24 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF0_RDY0 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_ALT_CH_BUF0_RDY0 is w1s register + #0 + + + + + IPU_ALT_CH_BUF0_RDY1_CLR + no description available + 25 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF0_RDY1 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_ALT_CH_BUF0_RDY1 is w1s register + #0 + + + + + IPU_ALT_CH_BUF1_RDY0_CLR + no description available + 26 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF1_RDY0 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_ALT_CH_BUF1_RDY0 is w1s register + #0 + + + + + IPU_ALT_CH_BUF1_RDY1_CLR + no description available + 27 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_ALT_CH_BUF1_RDY1 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_ALT_CH_BUF1_RDY1 is w1s register + #0 + + + + + IPU_CH_BUF0_RDY0_CLR + no description available + 28 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF0_RDY0 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF0_RDY0 is w1s register + #0 + + + + + IPU_CH_BUF0_RDY1_CLR + no description available + 29 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF0_RDY1 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF0_RDY1 is w1s register + #0 + + + + + IPU_CH_BUF1_RDY0_CLR + no description available + 30 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF1_RDY0 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF1_RDY0 is w1s register + #0 + + + + + IPU_CH_BUF1_RDY1_CLR + no description available + 31 + 1 + read-write + + + 1 + writing one to a bit of this register clears this bit; IPU_CH_BUF1_RDY1 is w1c register + #1 + + + 0 + writing one to a bit of this register sets this bit IPU_CH_BUF1_RDY1 is w1s register + #0 + + + + + + + CH_DB_MODE_SEL0 + Channel Double Buffer Mode Select 0 Register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_CH_DB_MODE_SEL_0 + no description available + 0 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_1 + no description available + 1 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_2 + no description available + 2 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_3 + no description available + 3 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_5 + no description available + 5 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_8 + no description available + 8 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_9 + no description available + 9 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_10 + no description available + 10 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_11 + no description available + 11 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_12 + no description available + 12 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_13 + no description available + 13 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_14 + no description available + 14 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_15 + no description available + 15 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_17 + no description available + 17 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_18 + no description available + 18 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_19 + no description available + 19 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_20 + no description available + 20 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_21 + no description available + 21 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_22 + no description available + 22 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_23 + no description available + 23 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_24 + no description available + 24 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_25 + no description available + 25 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_26 + no description available + 26 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_27 + no description available + 27 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_28 + no description available + 28 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_29 + no description available + 29 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_31 + no description available + 31 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + + + CH_DB_MODE_SEL1 + Channel Double Buffer Mode Select 1 Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_33 + no description available + 1 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_40 + no description available + 8 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_41 + no description available + 9 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_42 + no description available + 10 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_43 + no description available + 11 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_44 + no description available + 12 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_45 + no description available + 13 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_46 + no description available + 14 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_47 + no description available + 15 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_48 + no description available + 16 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_49 + no description available + 17 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_50 + no description available + 18 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_51 + no description available + 19 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_DB_MODE_SEL_52 + no description available + 20 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + + + ALT_CH_DB_MODE_SEL0 + Alternate Channel Double Buffer Mode Select 0 Register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 4 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_4 + no description available + 4 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_5 + no description available + 5 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_6 + no description available + 6 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_7 + no description available + 7 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 8 + 16 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_24 + no description available + 24 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 25 + 4 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_29 + no description available + 29 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + + + ALT_CH_DB_MODE_SEL1 + Alternate Channel Double Buffer Mode Select1 Register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_33 + no description available + 1 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_41 + no description available + 9 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 10 + 10 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + DMA_CH_ALT_DB_MODE_SEL_52 + no description available + 20 + 1 + read-write + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Double buffer is not used for this channel. + #0 + + + 1 + Double buffer is used for this channel. + #1 + + + + + + + ALT_CH_TRB_MODE_SEL0 + Alternate Channel Triple Buffer Mode Select 0 Register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_8 + no description available + 8 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_9 + no description available + 9 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_10 + no description available + 10 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 11 + 2 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_13 + no description available + 13 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 14 + 7 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_21 + no description available + 21 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 22 + 1 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_23 + no description available + 23 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 24 + 3 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_27 + no description available + 27 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + DMA_CH_TRB_MODE_SEL_28 + no description available + 28 + 1 + read-write + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + + + ALT_CH_TRB_MODE_SEL1 + Alternate Channel Triple Buffer Mode Select 1 Register + 0x17C + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_CH_TRB_MODE_SEL_n + no description available + 0 + 32 + read-only + + + 0 + Triple buffer is not used for this channel. + #0 + + + 1 + Triple buffer is used for this channel. + #1 + + + + + + + INT_STAT_1 + Interrupt Status Register 1 + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOF_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_2 + Interrupt Status Register2 + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOF_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_3 + Interrupt Status Register 3 + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_NFACK_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_4 + Interrupt Status Register 4 + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFACK_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_5 + Interrupt Status Register 5 + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_NFB4EOF_ERR_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_6 + Interrupt Status Register 6 + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_NFB4EOF_ERR_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_7 + Interrupt Status Register7 1 + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 19 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 20 + 3 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_8 + Interrupt Status Register 8 + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 13 + 6 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOS_EN_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_9 + Interrupt Status Register 9 + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_FIFO1_OVF + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 1 + 25 + read-only + + + IC_BAYER_BUF_OVF + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IC_ENC_BUF_OVF + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IC_VF_BUF_OVF + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 29 + 1 + read-only + + + CSI0_PUPE + no description available + 30 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + CSI1_PUPE + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_10 + Interrupt Status Register 10 + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMFC0_FRM_LOST + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + SMFC1_FRM_LOST + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + SMFC2_FRM_LOST + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + SMFC3_FRM_LOST + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 12 + read-only + + + DC_TEARING_ERR_1 + no description available + 16 + 1 + read-write + + + DC_TEARING_ERR_2 + no description available + 17 + 1 + read-write + + + DC_TEARING_ERR_6 + no description available + 18 + 1 + read-write + + + DI0_SYNC_DISP_ERR + no description available + 19 + 1 + read-write + + + DI1_SYNC_DISP_ERR + no description available + 20 + 1 + read-write + + + DI0_TIME_OUT_ERR + no description available + 21 + 1 + read-write + + + DI1_TIME_OUT_ERR + no description available + 22 + 1 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + IC_VF_FRM_LOST_ERR + no description available + 24 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_ENC_FRM_LOST_ERR + no description available + 25 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + IC_BAYER_FRM_LOST_ERR + no description available + 26 + 1 + read-write + + + 0 + Interrupt is disabled. + #0 + + + 1 + Interrupt is enabled. + #1 + + + + + RESERVED + no description available + 27 + 1 + read-only + + + NON_PRIVILEGED_ACC_ERR + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + AXIW_ERR + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + AXIR_ERR + no description available + 30 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + INT_STAT_11 + Interrupt Status Register 11 + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_EOBND_EN_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 6 + 5 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 13 + 7 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 23 + 2 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_12 + Interrupt Status Register 12 + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_EOBND_EN_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_13 + Interrupt Status Register 13 + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_TH_0 + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_1 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_2 + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_3 + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_5 + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_8 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_9 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_10 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_11 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_12 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_13 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_14 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_15 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_17 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_18 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_19 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_20 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_21 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_22 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_23 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_24 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_25 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_26 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_27 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_28 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_29 + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_31 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_14 + Interrupt Status Register 14 + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_33 + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_40 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_41 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_42 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_43 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_44 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_45 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_46 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_47 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_48 + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_49 + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_50 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_51 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + IDMAC_TH_52 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + INT_STAT_15 + Interrupt Status Register 15 + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + SNOOPING1_INT + no description available + 0 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + SNOOPING2_INT + no description available + 1 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_SF_START + no description available + 2 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_SF_END + no description available + 3 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_ASF_START + no description available + 4 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_ASF_END + no description available + 5 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_SF_BRAKE + no description available + 6 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DP_ASF_BRAKE + no description available + 7 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_0 + no description available + 8 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_1 + no description available + 9 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_2 + no description available + 10 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_3 + no description available + 11 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_4 + no description available + 12 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_FC_6 + no description available + 13 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI_VSYNC_PRE_0 + no description available + 14 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI_VSYNC_PRE_1 + no description available + 15 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_DP_START + no description available + 16 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DC_ASYNC_STOP + no description available + 17 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_0 + no description available + 18 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_1 + no description available + 19 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_2 + no description available + 20 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_3 + no description available + 21 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_4 + no description available + 22 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_5 + no description available + 23 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_6 + no description available + 24 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_7 + no description available + 25 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_8 + no description available + 26 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_9 + no description available + 27 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI0_CNT_EN_PRE_10 + no description available + 28 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI1_DISP_CLK_EN_PRE + no description available + 29 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI1_CNT_EN_PRE_3 + no description available + 30 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + DI1_CNT_EN_PRE_8 + no description available + 31 + 1 + read-write + + + 0 + Interrupt is cleared. + #0 + + + 1 + Interrupt is requested. + #1 + + + + + + + CUR_BUF_0 + Current Buffer Register 0 + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_CH_CUR_BUF_0 + no description available + 0 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_1 + no description available + 1 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_2 + no description available + 2 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_3 + no description available + 3 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_5 + no description available + 5 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_8 + no description available + 8 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_9 + no description available + 9 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_10 + no description available + 10 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_11 + no description available + 11 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_12 + no description available + 12 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_13 + no description available + 13 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_14 + no description available + 14 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_15 + no description available + 15 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_17 + no description available + 17 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_18 + no description available + 18 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_19 + no description available + 19 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_20 + no description available + 20 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_21 + no description available + 21 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_22 + no description available + 22 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_23 + no description available + 23 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_24 + no description available + 24 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_25 + no description available + 25 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_26 + no description available + 26 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_27 + no description available + 27 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_28 + no description available + 28 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_29 + no description available + 29 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_31 + no description available + 31 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + + + CUR_BUF_1 + Current Buffer Register 1 + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_33 + no description available + 1 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_40 + no description available + 8 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_41 + no description available + 9 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_42 + no description available + 10 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_43 + no description available + 11 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_44 + no description available + 12 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_45 + no description available + 13 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_46 + no description available + 14 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_47 + no description available + 15 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_48 + no description available + 16 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_49 + no description available + 17 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_50 + no description available + 18 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_51 + no description available + 19 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_CUR_BUF_52 + no description available + 20 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + + + ALT_CUR_0 + Alternate Current Buffer Register 0 + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_ALT_CUR_BUF_24 + no description available + 24 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 25 + 4 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_ALT_CUR_BUF_29 + no description available + 29 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + + + ALT_CUR_1 + Alternate Current Buffer Register 1 + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_ALT_CUR_BUF0_n + no description available + 1 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_ALT_CUR_BUF1_n + no description available + 9 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 10 + 10 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + DMA_CH_ALT_CUR_BUF_52 + no description available + 20 + 1 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + 0 + Current buffer used by DMA is buffer 0. + #0 + + + 1 + Current buffer used by DMA is buffer 1. + #1 + + + + + + + SRM_STAT + Shadow Registers Memory Status Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + DP_S_SRM_STAT + no description available + 0 + 1 + read-only + + + 1 + SRM is busy updating the DP sync flow registers + #1 + + + 0 + SRM is not updating the DP sync flow registers + #0 + + + + + DP_A0_SRM_STAT + no description available + 1 + 1 + read-only + + + 1 + SRM is busy updating the DP async flow 0 registers + #1 + + + 0 + SRM is not updating the DP async flow 0 registers + #0 + + + + + DP_A1_SRM_STAT + no description available + 2 + 1 + read-only + + + 1 + SRM is busy updating the DP sync flow registers + #1 + + + 0 + SRM is not updating the DP sync flow registers + #0 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + DC_2_SRM_STAT + no description available + 4 + 1 + read-only + + + 1 + SRM is busy updating the DC group #6 registers + #1 + + + 0 + SRM is not updating the DC group #2 registers + #0 + + + + + DC_6_SRM_STAT + no description available + 5 + 1 + read-only + + + 1 + SRM is busy updating the DC registers + #1 + + + 0 + SRM is not updating the DC registers + #0 + + + + + CSI0_SRM_STAT + no description available + 6 + 1 + read-only + + + CSI1_SRM_STAT + no description available + 7 + 1 + read-only + + + DI0_SRM_STAT + no description available + 8 + 1 + read-only + + + 1 + SRM is busy updating the DI0 registers + #1 + + + 0 + SRM is not updating the DI0 registers + #0 + + + + + DI1_SRM_STAT + no description available + 9 + 1 + read-only + + + 1 + SRM is busy updating the DI1 registers + #1 + + + 0 + SRM is not updating the DI1 registers + #0 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + PROC_TASKS_STAT + Processing Status Tasks Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENC_TSTAT + no description available + 0 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + VF_TSTAT + no description available + 2 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + PP_TSTAT + no description available + 4 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + ENC_ROT_TSTAT + no description available + 6 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + VF_ROT_TSTAT + no description available + 8 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + PP_ROT_TSTAT + no description available + 10 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - The primary flow of this task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + MEM2PRP_TSTAT + no description available + 12 + 3 + read-only + + + 000 + IDLE - Both pre processing tasks are idle + #000 + + + 001 + BOTH_ACTIVE - Both pre processing tasks are idle + #001 + + + 010 + ENC_ACTIVE - Encoding task is active + #010 + + + 011 + VF_ACTIVE - View finder task is active + #011 + + + 100 + BOTH_PAUSE - both tasks are paused + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserve + #111 + + + + + RESERVED + no description available + 15 + 17 + read-only + + + + + DISP_TASKS_STAT + Display Tasks Status Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + DP_ASYNC_STAT + no description available + 0 + 3 + read-only + + + 000 + IDLE - the task is idle + #000 + + + 001 + PRIM_ACTIVE - The primary flow of this task is currently active + #001 + + + 010 + ALT_ACTIVE - The alternate flow of this task is currently active + #010 + + + 011 + UPDATE_PARAM - The FSU is busy updating parameters from the SRM + #011 + + + 100 + PAUSE - The task is paused + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + DP_ASYNC_CUR_FLOW + no description available + 3 + 1 + read-only + + + 1 + alternate flow + #1 + + + 0 + main flow + #0 + + + + + DC_ASYNC1_STAT + no description available + 4 + 2 + read-only + + + 00 + IDLE - The task is idle + #00 + + + 01 + ACTIVE - This task is currently active + #01 + + + 10 + WAIT_FOR_ READY - The task is waiting for a buffer to be ready + #10 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + DC_ASYNCH2_STAT + no description available + 8 + 3 + read-only + + + 000 + IDLE - the task is idle + #000 + + + 001 + PRIM_ACTIVE - The primary flow of this task is currently active + #001 + + + 010 + ALT_ACTIVE - The alternate flow of this task is currently active + #010 + + + 011 + UPDATE_PARAM - The FSU is busy updating parameters from the SRM + #011 + + + 100 + PAUSE - The task is paused + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + DC_ASYNC2_CUR_FLOW + no description available + 11 + 1 + read-only + + + 1 + alternate flow + #1 + + + 0 + main flow + #0 + + + + + RESERVED + no description available + 12 + 20 + read-only + + + + + TRIPLE_CUR_BUF_0 + Triple Current Buffer Register 0 + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 16 + read-only + + + DMA_CH_TRIPLE_CUR_BUF_8 + no description available + 16 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + DMA_CH_TRIPLE_CUR_BUF_9 + no description available + 18 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + DMA_CH_TRIPLE_CUR_BUF_10 + no description available + 20 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + RESERVED + no description available + 22 + 4 + read-only + + + DMA_CH_TRIPLE_CUR_BUF_13 + no description available + 26 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + TRIPLE_CUR_BUF_1 + Triple Current Buffer Register 1 + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 10 + read-only + + + DMA_CH_TRIPLE_CUR_BUF_21 + no description available + 10 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + RESERVED + no description available + 12 + 2 + read-only + + + DMA_CH_TRIPLE_CUR_BUF_23 + no description available + 14 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + RESERVED + no description available + 16 + 6 + read-only + + + DMA_CH_TRIPLE_CUR_BUF_27 + no description available + 22 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + DMA_CH_TRIPLE_CUR_BUF_28 + no description available + 24 + 2 + read-only + + + 11 + NA + #11 + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + TRIPLE_CUR_BUF_2 + Triple Current Buffer Register 2 + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_CH_TRIPLE_CUR_BUF_n + no description available + 0 + 32 + read-only + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + + + TRIPLE_CUR_BUF_3 + Triple Current Buffer Register 3 + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + DMA_CH_TRIPLE_CUR_BUF_n + no description available + 0 + 32 + read-only + + + 00 + Current buffer used by DMA is buffer 0. + #00 + + + 01 + Current buffer used by DMA is buffer 1. + #01 + + + 10 + Current buffer used by DMA is buffer 2. + #10 + + + + + + + CH_BUF0_RDY0 + IPU Channels Buffer 0 Ready 0 Register + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_CH_BUF0_RDY_0 + no description available + 0 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_1 + no description available + 1 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_2 + no description available + 2 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_3 + no description available + 3 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_4 + no description available + 4 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_5 + no description available + 5 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_6 + no description available + 6 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_7 + no description available + 7 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_8 + no description available + 8 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_9 + no description available + 9 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_10 + no description available + 10 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_11 + no description available + 11 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_12 + no description available + 12 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_13 + no description available + 13 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_14 + no description available + 14 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_15 + no description available + 15 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + DMA_CH_BUF0_RDY_17 + no description available + 17 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_18 + no description available + 18 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + DMA_CH_BUF0_RDY_20 + no description available + 20 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_21 + no description available + 21 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_22 + no description available + 22 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_23 + no description available + 23 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_24 + no description available + 24 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 25 + 2 + read-only + + + DMA_CH_BUF0_RDY_27 + no description available + 27 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_28 + no description available + 28 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_29 + no description available + 29 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + DMA_CH_BUF0_RDY_31 + no description available + 31 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + + + CH_BUF0_RDY1 + IPU Channels Buffer 0 Ready 1 Register + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DMA_CH_BUF0_RDY_33 + no description available + 1 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + DMA_CH_BUF0_RDY_40 + no description available + 8 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_41 + no description available + 9 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_42 + no description available + 10 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_43 + no description available + 11 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_44 + no description available + 12 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_45 + no description available + 13 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_46 + no description available + 14 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_47 + no description available + 15 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_48 + no description available + 16 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_49 + no description available + 17 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_50 + no description available + 18 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_51 + no description available + 19 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_52 + no description available + 20 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + CH_BUF1_RDY0 + IPU Channels Buffer 1 Ready 0 Register + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_CH_BUF1_RDY_0 + no description available + 0 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_1 + no description available + 1 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_2 + no description available + 2 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_3 + no description available + 3 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + DMA_CH_BUF1_RDY_5 + no description available + 5 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + DMA_CH_BUF1_RDY_8 + no description available + 8 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_9 + no description available + 9 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_10 + no description available + 10 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_ + no description available + 11 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_12 + no description available + 12 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_13 + no description available + 13 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_14 + no description available + 14 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_15 + no description available + 15 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + DMA_CH_BUF1_RDY_17 + no description available + 17 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_18 + no description available + 18 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_19 + no description available + 19 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_20 + no description available + 20 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_21 + no description available + 21 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_22 + no description available + 22 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_23 + no description available + 23 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_24 + no description available + 24 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_25 + no description available + 25 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_26 + no description available + 26 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_27 + no description available + 27 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_28 + no description available + 28 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + DMA_CH_BUF1_RDY_29 + no description available + 29 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + DMA_CH_BUF1_RDY_31 + no description available + 31 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + + + CH_BUF1_RDY1 + IPU Channels Buffer 1 Ready 1Register + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DMA_CH_BUF0_RDY_33 + no description available + 1 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + DMA_CH_BUF0_RDY_40 + no description available + 8 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_41 + no description available + 9 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_42 + no description available + 10 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_43 + no description available + 11 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_44 + no description available + 12 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_45 + no description available + 13 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_46 + no description available + 14 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_47 + no description available + 15 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_48 + no description available + 16 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_49 + no description available + 17 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_50 + no description available + 18 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_51 + no description available + 19 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + DMA_CH_BUF0_RDY_52 + no description available + 20 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + Buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + ALT_CH_BUF0_RDY0 + IPU Alternate Channels Buffer 0 Ready 0 Register + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + DMA_CH_ALT_BUF0_RDY_24 + no description available + 24 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 25 + 4 + read-only + + + DMA_CH_ALT_BUF0_RDY_29 + no description available + 29 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + ALT_CH_BUF0_RDY1 + IPU Alternate Channels Buffer 0 Ready 1 Register + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DMA_CH_ALT_BUF0_RDY_33 + no description available + 1 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + DMA_CH_ALT_BUF0_RDY_41 + no description available + 9 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 10 + 10 + read-only + + + DMA_CH_ALT_BUF0_RDY_52 + no description available + 20 + 1 + read-write + + + 0 + Buffer 0 is not ready. + #0 + + + 1 + Buffer 0 is ready. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + ALT_CH_BUF1_RDY0 + IPU Alternate Channels Buffer1 Ready 0 Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 24 + read-only + + + DMA_CH_ALT_BUF1_RDY_24 + no description available + 24 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 25 + 4 + read-only + + + DMA_CH_ALT_BUF1_RDY_29 + no description available + 29 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + ALT_CH_BUF1_RDY1 + IPU Alternate Channels Buffer 1 Ready 1 Register + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DMA_CH_ALT_BUF1_RDY_33 + no description available + 1 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 2 + 7 + read-only + + + DMA_CH_ALT_BUF1_RDY_41 + no description available + 9 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 10 + 10 + read-only + + + DMA_CH_ALT_BUF1_RDY_52 + no description available + 20 + 1 + read-write + + + 0 + buffer 1 is not ready. + #0 + + + 1 + buffer 1 is ready. + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + CH_BUF2_RDY0 + IPU Channels Buffer 2 Ready 0 Register + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_CH_BUF2_RDY_0 + no description available + 0 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 1 + 1 + read-only + + + DMA_CH_BUF2_RDY_2 + no description available + 2 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + DMA_CH_BUF2_RDY_8 + no description available + 8 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + DMA_CH_BUF2_RDY_9 + no description available + 9 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + DMA_CH_BUF2_RDY_10 + no description available + 10 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 11 + 2 + read-only + + + DMA_CH_BUF2_RDY_13 + no description available + 13 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 14 + 7 + read-only + + + DMA_CH_BUF2_RDY_21 + no description available + 21 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 22 + 1 + read-only + + + DMA_CH_BUF2_RDY_23 + no description available + 23 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 24 + 3 + read-only + + + DMA_CH_ALT_BUF1_RDY_27 + no description available + 27 + 1 + read-write + + + 0 + buffer 2 is not ready. + #0 + + + 1 + buffer 2 is ready. + #1 + + + + + DMA_CH_BUF2_RDY_28 + no description available + 28 + 1 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + CH_BUF2_RDY1 + IPU Channels Buffer 2 Ready 1 Register + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DMA_CH_BUF2_RDY_x + no description available + 0 + 32 + read-write + + + 0 + Buffer 2 is not ready. + #0 + + + 1 + Buffer 2 is ready. + #1 + + + + + + + IDMAC_CONF + IDMAC Configuration Register + 0x8000 + 32 + read-write + 0x2F + 0xFFFFFFFF + + + MAX_REQ_READ + no description available + 0 + 3 + read-write + + + WIDPT + no description available + 3 + 2 + read-write + + + RDI + no description available + 5 + 1 + read-write + + + RESERVED + no description available + 6 + 10 + read-only + + + P_ENDIAN + no description available + 16 + 1 + read-write + + + USED_BUFS_MAX_W + no description available + 17 + 3 + read-write + + + USED_BUFS_EN_W + no description available + 20 + 1 + read-write + + + USED_BUFS_MAX_R + no description available + 21 + 4 + read-write + + + USED_BUFS_EN_R + no description available + 25 + 1 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + IDMAC_CH_EN_1 + IDMAC Channel Enable 1 Register + 0x8004 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_CH_EN_0 + no description available + 0 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_1 + no description available + 1 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_2 + no description available + 2 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_3 + no description available + 3 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + IDMAC_CH_EN_5 + no description available + 5 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + IDMAC_CH_EN_8 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_9 + no description available + 9 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_10 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_11 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_12 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_13 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_14 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_15 + no description available + 15 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + IDMAC_CH_EN_17 + no description available + 17 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_18 + no description available + 18 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_19 + no description available + 19 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_20 + no description available + 20 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_21 + no description available + 21 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_22 + no description available + 22 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_23 + no description available + 23 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_24 + no description available + 24 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_25 + no description available + 25 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_26 + no description available + 26 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_27 + no description available + 27 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_28 + no description available + 28 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_29 + no description available + 29 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + IDMAC_CH_EN_31 + no description available + 31 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + + + IDMAC_CH_EN_2 + IDMAC Channel Enable 2 Register + 0x8008 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-write + + + IDMAC_CH_EN_33 + no description available + 1 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + IDMAC_CH_EN_40 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_41 + no description available + 9 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_42 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_43 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_44 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_45 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_46 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_47 + no description available + 15 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_48 + no description available + 16 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_49 + no description available + 17 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_50 + no description available + 18 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_51 + no description available + 19 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + IDMAC_CH_EN_52 + no description available + 20 + 1 + read-write + + + 0 + IDMAC channel is disabled + #0 + + + 1 + IDMAC channel is enabled + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + IDMAC_SEP_ALPHA + IDMAC Separate Alpha Indication Register + 0x800C + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 14 + read-only + + + IDMAC_SEP_AL_14 + no description available + 14 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + IDMAC_SEP_AL_15 + no description available + 15 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 16 + 7 + read-only + + + IDMAC_SEP_AL_23 + no description available + 23 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + IDMAC_SEP_AL_24 + no description available + 24 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + IDMAC_SEP_AL_25 + no description available + 25 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 26 + 1 + read-only + + + IDMAC_SEP_AL_27 + no description available + 27 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 28 + 1 + read-only + + + IDMAC_SEP_AL_29 + no description available + 29 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IDMAC_ALT_SEP_ALPHA + IDMAC Alternate Separate Alpha Indication Register + 0x8010 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 23 + read-only + + + IDMAC_ALT_SEP_AL_23 + no description available + 23 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + IDMAC_ALT_SEP_AL_24 + no description available + 24 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 25 + 4 + read-only + + + IDMAC_ALT_SEP_AL_29 + no description available + 29 + 1 + read-write + + + 0 + Channel [i] does not read Alpha transparency data from a separate buffer. + #0 + + + 1 + Channel [i] reads Alpha transparency data from a separate buffer. + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IDMAC_CH_PRI_1 + IDMAC Channel Priority 1 Register + 0x8014 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_CH_PRI_0 + no description available + 0 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_1 + no description available + 1 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_2 + no description available + 2 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_3 + no description available + 3 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + IDMAC_CH_PRI_5 + no description available + 5 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + IDMAC_CH_PRI_8 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_9 + no description available + 9 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_10 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_11 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_12 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_13 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_14 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_15 + no description available + 15 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + RESERVED + no description available + 16 + 4 + read-only + + + IDMAC_CH_PRI_20 + no description available + 20 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_21 + no description available + 21 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_22 + no description available + 22 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_23 + no description available + 23 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_24 + no description available + 24 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_25 + no description available + 25 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_26 + no description available + 26 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_27 + no description available + 27 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_28 + no description available + 28 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_29 + no description available + 29 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IDMAC_CH_PRI_2 + IDMAC Channel Priority 2 Register + 0x8018 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + IDMAC_CH_PRI_8 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_9 + no description available + 9 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_10 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_11 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_12 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_13 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_14 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_15 + no description available + 15 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_16 + no description available + 16 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_17 + no description available + 17 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + IDMAC_CH_PRI_18 + no description available + 18 + 1 + read-write + + + 0 + IDMAC channel [i] is in low priority + #0 + + + 1 + IDMAC channel [i] is in high priority + #1 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + IDMAC_WM_EN_1 + IDMAC Channel Watermark Enable 1 Register + 0x801C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_WM_EN_0 + no description available + 0 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_1 + no description available + 1 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_2 + no description available + 2 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_3 + no description available + 3 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + IDMAC_WM_EN_8 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 9 + 1 + read-only + + + IDMAC_WM_EN_10 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 11 + 1 + read-only + + + IDMAC_WM_EN_12 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_13 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_14 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 15 + 8 + read-only + + + IDMAC_WM_EN_23 + no description available + 23 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_24 + no description available + 24 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_25 + no description available + 25 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_26 + no description available + 26 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_27 + no description available + 27 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_28 + no description available + 28 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_29 + no description available + 29 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IDMAC_WM_EN_2 + IDMAC Channel Watermark Enable 2 Register + 0x8020 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + IDMAC_WM_EN_40 + no description available + 8 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_41 + no description available + 9 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_42 + no description available + 10 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_43 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + IDMAC_WM_EN_44 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel [i] watermark feature is disabled + #0 + + + 1 + IDMAC channel [i] watermark feature is enabled + #1 + + + + + RESERVED + no description available + 13 + 19 + read-only + + + + + IDMAC_LOCK_EN_1 + IDMAC Channel Lock Enable 1Register + 0x8024 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_LOCK_EN_5 + no description available + 0 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_11 + no description available + 2 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_12 + no description available + 4 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_14 + no description available + 6 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_15 + no description available + 8 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_20 + no description available + 10 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_21 + no description available + 12 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_22 + no description available + 14 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_23 + no description available + 16 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_27 + no description available + 18 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_EN_28 + no description available + 20 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + RESERVED + no description available + 22 + 10 + read-only + + + + + IDMAC_LOCK_EN_2 + IDMAC Channel Lock Enable 2Register + 0x8028 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_LOCK_45 + no description available + 0 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_46 + no description available + 2 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_47 + no description available + 4 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_48 + no description available + 6 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_49 + no description available + 8 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + IDMAC_LOCK_50 + no description available + 10 + 2 + read-write + + + 00 + The lock feature is disabled. The IDMAC will generate one AXI burst upon the assertion of the DMA request. + #00 + + + 01 + The IDMAC will generate two AXI bursts upon the assertion of the DMA request. + #01 + + + 10 + The IDMAC will generate four AXI bursts upon the assertion of the DMA request. + #10 + + + 11 + The IDMAC will generate eight AXI bursts upon the assertion of the DMA request. + #11 + + + + + RESERVED + no description available + 12 + 20 + read-only + + + + + IDMAC_SUB_ADDR_0 + IDMAC Channel Alternate Address 0 Register + 0x802C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_SUB_ADDR_i + no description available + 0 + 32 + read-write + + + + + IDMAC_SUB_ADDR_1 + IDMAC Channel Alternate Address 1 Register + 0x8030 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_SUB_ADDR_23 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDMAC_SUB_ADDR_24 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + IDMAC_SUB_ADDR_29 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + IDMAC_SUB_ADDR_33 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + IDMAC_SUB_ADDR_2 + IDMAC Channel Alternate Address 2 Register + 0x8034 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_SUB_ADDR_41 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDMAC_SUB_ADDR_51 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + IDMAC_SUB_ADDR_52 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 9 + read-only + + + + + IDMAC_SUB_ADDR_3 + IDMAC Channel Alternate Address 3 Register + 0x8038 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_SUB_ADDR_9 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDMAC_SUB_ADDR_10 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + IDMAC_SUB_ADDR_13 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 1 + read-only + + + IDMAC_SUB_ADDR_27 + no description available + 24 + 7 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + IDMAC_SUB_ADDR_4 + IDMAC Channel Alternate Address 4 Register + 0x803C + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_SUB_ADDR_28 + no description available + 0 + 7 + read-write + + + RESERVED + no description available + 7 + 1 + read-only + + + IDMAC_SUB_ADDR_8 + no description available + 8 + 7 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + IDMAC_SUB_ADDR_21 + no description available + 16 + 7 + read-write + + + RESERVED + no description available + 23 + 9 + read-only + + + + + IDMAC_BNDM_EN_1 + IDMAC Band Mode Enable 1 Register + 0x8040 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDMAC_BNDM_EN_0 + no description available + 0 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_1 + no description available + 1 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_2 + no description available + 2 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_3 + no description available + 3 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + IDMAC_BNDM_EN_5 + no description available + 5 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 6 + 5 + read-only + + + IDMAC_BNDM_EN_11 + no description available + 11 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_12 + no description available + 12 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 13 + 7 + read-only + + + IDMAC_BNDM_EN_20 + no description available + 20 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_21 + no description available + 21 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_22 + no description available + 22 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 23 + 2 + read-only + + + IDMAC_BNDM_EN_25 + no description available + 25 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_26 + no description available + 26 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + IDMAC_BNDM_EN_2 + IDMAC Band Mode Enable 2 Register + 0x8044 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 13 + read-only + + + IDMAC_BNDM_EN_45 + no description available + 13 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_46 + no description available + 14 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_47 + no description available + 15 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_48 + no description available + 16 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_49 + no description available + 17 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + IDMAC_BNDM_EN_50 + no description available + 18 + 1 + read-write + + + 0 + IDMAC channel [i] is not in band mode + #0 + + + 1 + IDMAC channel [i] is in band mode + #1 + + + + + RESERVED + no description available + 19 + 13 + read-only + + + + + IDMAC_SC_CORD + IDMAC Scroll Coordinations Register + 0x8048 + 32 + read-write + 0 + 0xFFFFFFFF + + + SY0 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + SX0 + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + IDMAC_SC_CORD_1 + IDMAC Scroll Coordinations Register 1 + 0x804C + 32 + read-write + 0 + 0xFFFFFFFF + + + SY1 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + SX1 + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + IDMAC_CH_BUSY_1 + IDMAC Channel Busy 1 Register + 0x8100 + 32 + read-only + 0 + 0xFFFFFFFF + + + IDMAC_CH_BUSY_0 + no description available + 0 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_1 + no description available + 1 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_2 + no description available + 2 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_3 + no description available + 3 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + IDMAC_CH_BUSY_5 + no description available + 5 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + IDMAC_CH_BUSY_8 + no description available + 8 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_9 + no description available + 9 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_10 + no description available + 10 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_11 + no description available + 11 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_12 + no description available + 12 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_13 + no description available + 13 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_14 + no description available + 14 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_15 + no description available + 15 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 16 + 1 + read-only + + + IDMAC_CH_BUSY_17 + no description available + 17 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_18 + no description available + 18 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 19 + 1 + read-only + + + IDMAC_CH_BUSY_20 + no description available + 20 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_21 + no description available + 21 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_22 + no description available + 22 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_23 + no description available + 23 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_24 + no description available + 24 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_25 + no description available + 25 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_26 + no description available + 26 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_27 + no description available + 27 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_28 + no description available + 28 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_29 + no description available + 29 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + IDMAC_CH_BUSY_ + no description available + 31 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + + + IDMAC_CH_BUSY_2 + IDMAC Channel Busy 2 Register + 0x8104 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + IDMAC_CH_BUSY_33 + no description available + 1 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + IDMAC_CH_BUSY_40 + no description available + 8 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_41 + no description available + 9 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_42 + no description available + 10 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_43 + no description available + 11 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_44 + no description available + 12 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_45 + no description available + 13 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_46 + no description available + 14 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_47 + no description available + 15 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_48 + no description available + 16 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_49 + no description available + 17 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_50 + no description available + 18 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_51 + no description available + 19 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + IDMAC_CH_BUSY_52 + no description available + 20 + 1 + read-only + + + 0 + IDMAC channel [i] is not busy + #0 + + + 1 + IDMAC channel [i] is busy + #1 + + + + + RESERVED + no description available + 21 + 11 + read-only + + + + + DP_COM_CONF_SYNC + DP Common Configuration Sync Flow Register + 0x18000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_FG_EN_SYNC + no description available + 0 + 1 + read-write + + + 1 + partial plane channel is enabled. + #1 + + + 0 + partial plane channel is disabled. + #0 + + + + + DP_GWSEL_SYNC + no description available + 1 + 1 + read-write + + + 1 + Graphic window is partial plane. + #1 + + + 0 + Graphic window is full plane. + #0 + + + + + DP_GWAM_SYNC + no description available + 2 + 1 + read-write + + + 1 + Global Alpha. + #1 + + + 0 + Local Alpha. + #0 + + + + + DP_GWCKE_SYNC + no description available + 3 + 1 + read-write + + + 1 + Enable color keying of graphic window + #1 + + + 0 + Disable color keying of graphic window + #0 + + + + + DP_COC_SYNC + no description available + 4 + 3 + read-write + + + 000 + Transparent, cursor is disabled. + #000 + + + 001 + Full cursor. + #001 + + + 010 + Reversed cursor. + #010 + + + 011 + AND between full plane and cursor. + #011 + + + 100 + Reserved + #100 + + + 101 + OR between full plane and cursor. + #101 + + + 110 + XOR between full plane and cursor. + #110 + + + 111 + Reserved. + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + DP_CSC_DEF_SYNC + no description available + 8 + 2 + read-write + + + 00 + CSC disable + #00 + + + 01 + CSC enable after combining + #01 + + + 10 + CSC enable before combining on BG channel + #10 + + + 11 + CSC enable before combining on FG channel + #11 + + + + + DP_CSC_GAMUT_SAT_EN_SYNC + no description available + 10 + 1 + read-write + + + 0 + disable GAMUT mapping + #0 + + + 1 + enable GAMUT mapping + #1 + + + + + DP_CSC_YUV_SAT_MODE_SYNC + no description available + 11 + 1 + read-write + + + 0 + Y/U/V range 0 -255 + #0 + + + 1 + Y range 16-235, U/V range 16-240 + #1 + + + + + DP_GAMMA_EN_SYNC + no description available + 12 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + DP_GAMMA_YUV_EN_SYNC + no description available + 13 + 1 + read-write + + + 0 + YUV mode is OFF. + #0 + + + 1 + YUV mode is ON. + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + DP_Graph_Wind_CTRL_SYNC + DP Graphic Window Control Sync Flow Register + 0x18004 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GWCKB_SYNC + no description available + 0 + 8 + read-write + + + 00000000 + No blue + #00000000 + + + 11111111 + Full blue + #11111111 + + + + + DP_GWCKG_SYNC + no description available + 8 + 8 + read-write + + + 00000000 + No Green + #00000000 + + + 11111111 + Full Green + #11111111 + + + + + DP_GWCKR_SYNC + no description available + 16 + 8 + read-write + + + 00000000 + No red + #00000000 + + + 11111111 + Full red + #11111111 + + + + + DP_GWAV_SYNC + no description available + 24 + 8 + read-write + + + 00000000 + Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen + #00000000 + + + 01111111 + Actual value is 01111111; + #01111111 + + + 10000000 + Actual value is 10000001 + #10000000 + + + 10000001 + Actual value is 10000010 + #10000001 + + + 11111110 + Actual value is 11111111 + #11111110 + + + 11111111 + Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen + #11111111 + + + + + + + DP_FG_POS_SYNC + DP Partial Plane Window Position Sync Flow Register + 0x18008 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_FGYP_SYNC + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + DP_FGXP_SYNC + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DP_CUR_POS_SYNC + DP Cursor Position and Size Sync Flow Register + 0x1800C + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CXW_SYNC + no description available + 0 + 11 + read-write + + + DP_CXP_SYNC + no description available + 11 + 5 + read-write + + + DP_CYH_SYNC + no description available + 16 + 11 + read-write + + + DP_CYP_SYNC + no description available + 27 + 5 + read-write + + + + + DP_CUR_MAP_SYNC + DP Color Cursor Mapping Sync Flow Register + 0x18010 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CUR_COL_R_SYNC + no description available + 0 + 8 + read-write + + + 00000000 + No Red. + #00000000 + + + 11111111 + Full Red. + #11111111 + + + + + DP_CUR_COL_G_SYNC + no description available + 8 + 8 + read-write + + + 00000000 + No Green. + #00000000 + + + 11111111 + Full Green. + #11111111 + + + + + DP_CUR_COL_B_SYNC + no description available + 16 + 8 + read-write + + + 00000000 + No Blue. + #00000000 + + + 11111111 + Full Blue. + #11111111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DP_GAMMA_C_SYNC_i + DP Gamma Constants Sync Flow Register i + 0x18014 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_C_SYNC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + DP_GAMMA_C_SYNC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DP_GAMMA_S_SYNC_i + DP Gamma Correction Slope Sync Flow Register i + 0x18034 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_S_SYNC_4i + no description available + 0 + 8 + read-write + + + DP_GAMMA_S_SYNC_4i_1 + no description available + 8 + 8 + read-write + + + DP_GAMMA_S_SYNC_4i_2 + no description available + 16 + 8 + read-write + + + DP_GAMMA_S_SYNC_4i_3 + no description available + 24 + 8 + read-write + + + + + DP_CSCA_SYNC_i + DP Color Space Conversion Control Sync Flow Registers + 0x18044 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A_SYNC_2i + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_A_SYNC_2i_1 + no description available + 16 + 10 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + DP_SCS_SYNC_0 + DP Color Conversion Control Sync Flow Register 0 + 0x18054 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A8_SYNC + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_B0_SYNC + no description available + 16 + 14 + read-write + + + DP_CSC_S0_SYNC + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 0 + #10 + + + 11 + scale factor of -1 + #11 + + + + + + + DP_SCS_SYNC_1 + DP Color Conversion Control Sync Flow Register 1 + 0x18058 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_B1_SYNC + no description available + 0 + 14 + read-write + + + DP_CSC_S1_SYNC + no description available + 14 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + DP_CSC_B2_SYNC + no description available + 16 + 14 + read-write + + + DP_CSC_S2_SYNC + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + + + DP_CUR_POS_ALT + DP Cursor Position and Size Alternate Register + 0x1805C + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CXW_SYNC_ALT + no description available + 0 + 11 + read-write + + + DP_CXP_SYNC_ALT + no description available + 11 + 5 + read-write + + + DP_CYH_SYNC_ALT + no description available + 16 + 11 + read-write + + + DP_CYP_SYNC_ALT + no description available + 27 + 5 + read-write + + + + + DP_COM_CONF_ASYNC0 + DP Common Configuration Async 0 Flow Register + 0x18060 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DP_GWSEL_ASYNC0 + no description available + 1 + 1 + read-write + + + 1 + Graphic window is partial plane. + #1 + + + 0 + Graphic window is full plane.5 + #0 + + + + + DP_GWAM_ASYNC0 + no description available + 2 + 1 + read-write + + + 1 + Global Alpha. + #1 + + + 0 + Local Alpha. + #0 + + + + + DP_GWCKE_ASYNC0 + no description available + 3 + 1 + read-write + + + 1 + Enable color keying of graphic window + #1 + + + 0 + Disable color keying of graphic window + #0 + + + + + DP_COC_ASYNC0 + no description available + 4 + 3 + read-write + + + 000 + Transparent, cursor is disabled. + #000 + + + 001 + Full cursor. + #001 + + + 010 + Reversed cursor. + #010 + + + 011 + AND between full plane and cursor. + #011 + + + 100 + Reserved + #100 + + + 101 + OR between full plane and cursor. + #101 + + + 110 + XOR between full plane and cursor. + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + DP_CSC_DEF_ASYNC0 + no description available + 8 + 2 + read-write + + + 00 + CSC disable + #00 + + + 01 + CSC enable after combining + #01 + + + 10 + CSC enable before combining on BG channel + #10 + + + 11 + CSC enable before combining on FG channel + #11 + + + + + DP_CSC_GAMUT_SAT_EN_ASYNC0 + no description available + 10 + 1 + read-write + + + 0 + disable GAMUT mapping + #0 + + + 1 + enable GAMUT mapping + #1 + + + + + DP_CSC_YUV_SAT_MODE_ASYNC0 + no description available + 11 + 1 + read-write + + + 0 + Y/U/V range 0 -255 + #0 + + + 1 + Y range 16-235, U/V range 16-240 + #1 + + + + + DP_GAMMA_EN_ASYNC0 + no description available + 12 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + DP_GAMMA_YUV_EN_ASYNC0 + no description available + 13 + 1 + read-write + + + 0 + YUV mode is OFF. + #0 + + + 1 + YUV mode is ON. + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + DP_GRAPH_WIND_CTRL_ASYNC0 + DP Graphic Window Control Async 0 Flow Register + 0x18064 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GWCKB_ASYNC0 + no description available + 0 + 8 + read-write + + + 00000000 + No blue + #00000000 + + + 11111111 + Full blue + #11111111 + + + + + DP_GWCKG_ASYNC0 + no description available + 8 + 8 + read-write + + + 00000000 + No Green + #00000000 + + + 11111111 + Full Green + #11111111 + + + + + DP_GWCKR_ASYNC0 + no description available + 16 + 8 + read-write + + + 00000000 + No red + #00000000 + + + 11111111 + Full red + #11111111 + + + + + DP_GWAV_ASYNC0 + no description available + 24 + 8 + read-write + + + 00000000 + Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen + #00000000 + + + 01111111 + Actual value is 01111111; + #01111111 + + + 10000000 + Actual value is 10000001 + #10000000 + + + 10000001 + Actual value is 10000010 + #10000001 + + + 11111110 + Actual value is 11111111 + #11111110 + + + 11111111 + Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen + #11111111 + + + + + + + DP_FG_POS_ASYNC0 + DP Partial Plane Window Position Async 0 Flow Register + 0x18068 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_FGYP_ASYNC0 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + DP_FGXP_ASYNC0 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DP_CUR_POS_ASYNC0 + DP Cursor Position and Size Async 0 Flow Register + 0x1806C + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CXW_ASYNC0 + no description available + 0 + 11 + read-write + + + DP_CXP_ASYNC0 + no description available + 11 + 5 + read-write + + + DP_CYH_ASYNC0 + no description available + 16 + 11 + read-write + + + DP_CYP_ASYNC0 + no description available + 27 + 5 + read-write + + + + + DP_CUR_MAP_ASYNC0 + DP Color Cursor Mapping Async 0 Flow Register + 0x18070 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CUR_COL_R_ASYNC0 + no description available + 0 + 8 + read-write + + + 00000000 + No Red. + #00000000 + + + 11111111 + Full Red. + #11111111 + + + + + DP_CUR_COL_G_ASYNC0 + no description available + 8 + 8 + read-write + + + 00000000 + No Green. + #00000000 + + + 11111111 + Full Green. + #11111111 + + + + + DP_CUR_COL_B_ASYNC0 + no description available + 16 + 8 + read-write + + + 00000000 + No Blue. + #00000000 + + + 11111111 + Full Blue. + #11111111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DP_GAMMA_C_ASYNC0_i + DP Gamma Constant Async 0 Flow Register i + 0x18074 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_C_ASYNC0_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + DP_GAMMA_C_ASYNC0_2i_1 + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DP_GAMMA_S_ASYNC0_i + DP Gamma Correction Slope Async 0 Flow Register i + 0x18094 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_S_ASYNC0_4i + no description available + 0 + 8 + read-write + + + DP_GAMMA_S_ASYNC0_4i_1 + no description available + 8 + 8 + read-write + + + DP_GAMMA_S_ASYNC0_4i_2 + no description available + 16 + 8 + read-write + + + DP_GAMMA_S_ASYNC0_4i_3 + no description available + 24 + 8 + read-write + + + + + DP_CSCA_ASYNC0_i + DP Color Space Conversion Control Async 0 Flow Register i + 0x180A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A_ASYNC0_2i + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_A_ASYNC0_2i_1 + no description available + 16 + 10 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + DP_CSC_ASYNC0_0 + DP Color Conversion Control Async 0 Flow Register 0 + 0x180B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A8_ASYNC0 + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_B0_ASYNC0 + no description available + 16 + 14 + read-write + + + DP_CSC_S0_ASYNC0 + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 0 + #10 + + + 11 + scale factor of -1 + #11 + + + + + + + DP_CSC_ASYNC_1 + DP Color Conversion Control Async 1 Flow Register + 0x180B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_B1_ASYNC0 + no description available + 0 + 14 + read-write + + + DP_CSC_S1_ASYNC0 + no description available + 14 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + DP_CSC_B2_ASYNC0 + no description available + 16 + 14 + read-write + + + DP_CSC_S2_ASYNC0 + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + + + DP_COM_CONF_ASYNC1 + DP Common Configuration Async 1 Flow Register + IPU + 0x180BC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + DP_GWSEL_ASYNC1 + no description available + 1 + 1 + read-write + + + 1 + Graphic window is partial plane. + #1 + + + 0 + Graphic window is full plane. + #0 + + + + + DP_GWAM_ASYNC1 + no description available + 2 + 1 + read-write + + + 1 + Global Alpha. + #1 + + + 0 + Local Alpha. + #0 + + + + + DP_GWCKE_ASYNC1 + no description available + 3 + 1 + read-write + + + 1 + Enable color keying of graphic window + #1 + + + 0 + Disable color keying of graphic window + #0 + + + + + DP_COC_ASYNC1 + no description available + 4 + 3 + read-write + + + 000 + Transparent, cursor is disabled. + #000 + + + 001 + Full cursor. + #001 + + + 010 + Reversed cursor. + #010 + + + 011 + AND between full plane and cursor. + #011 + + + 100 + Reserved + #100 + + + 101 + OR between full plane and cursor. + #101 + + + 110 + XOR between full plane and cursor. + #110 + + + 111 + Reserved + #111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + DP_CSC_DEF_ASYNC1 + no description available + 8 + 2 + read-write + + + 00 + CSC disable + #00 + + + 01 + CSC enable after combining + #01 + + + 10 + CSC enable before combining on BG channel + #10 + + + 11 + CSC enable before combining on FG channel + #11 + + + + + DP_CSC_GAMUT_SAT_EN_ASYNC1 + no description available + 10 + 1 + read-write + + + 0 + disable GAMUT mapping + #0 + + + 1 + enable GAMUT mapping + #1 + + + + + DP_CSC_YUV_SAT_MODE_ASYNC1 + no description available + 11 + 1 + read-write + + + 0 + Y/U/V range 0 -255 + #0 + + + 1 + Y range 16-235, U/V range 16-240 + #1 + + + + + DP_GAMMA_EN_ASYNC1 + no description available + 12 + 1 + read-write + + + 0 + disable + #0 + + + 1 + enable + #1 + + + + + DP_GAMMA_YUV_EN_ASYNC1 + no description available + 13 + 1 + read-write + + + 0 + YUV mode is OFF. + #0 + + + 1 + YUV mode is ON. + #1 + + + + + RESERVED + no description available + 14 + 18 + read-only + + + + + DP_DEBUG_CNT + DP Debug Control Register + IPU + 0x180BC + 32 + read-write + 0 + 0xFFFFFFFF + + + BRAKE_STATUS_EN_0 + no description available + 0 + 1 + read-write + + + BRAKE_CNT_0 + no description available + 1 + 3 + read-write + + + BRAKE_STATUS_EN_1 + no description available + 4 + 1 + read-write + + + BRAKE_CNT_1 + no description available + 5 + 3 + read-write + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DP_GRAPH_WIND_CTRL_ASYNC1 + DP Graphic Window Control Async 1 Flow Register + IPU + 0x180C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GWCKB_ASYNC1 + no description available + 0 + 8 + read-write + + + 00000000 + No blue + #00000000 + + + 11111111 + Full blue + #11111111 + + + + + DP_GWCKG_ASYNC1 + no description available + 8 + 8 + read-write + + + 00000000 + No Green + #00000000 + + + 11111111 + Full Green + #11111111 + + + + + DP_GWCKR_ASYNC1 + no description available + 16 + 8 + read-write + + + 00000000 + No red + #00000000 + + + 11111111 + Full red + #11111111 + + + + + DP_GWAV_ASYNC1 + no description available + 24 + 8 + read-write + + + 00000000 + Actual value is 00000000; Graphic window totally opaque i.e. overlay on LCD screen + #00000000 + + + 01111111 + Actual value is 01111111; + #01111111 + + + 10000000 + Actual value is 10000001 + #10000000 + + + 10000001 + Actual value is 10000010 + #10000001 + + + 11111110 + Actual value is 11111111 + #11111110 + + + 11111111 + Actual value is 100000000;Graphic window totally transparent i.e. not displayed on LCD screen + #11111111 + + + + + + + DP_DEBUG_STAT + DP Debug Status Register + IPU + 0x180C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + V_CNT_OLD_0 + no description available + 0 + 11 + read-only + + + FG_ACTIVE_0 + no description available + 11 + 1 + read-only + + + COMBYP_EN_OLD_0 + no description available + 12 + 1 + read-only + + + CYP_EN_OLD_0 + no description available + 13 + 1 + read-only + + + RESERVED + no description available + 14 + 2 + read-only + + + V_CNT_OLD_1 + no description available + 16 + 11 + read-only + + + FG_ACTIVE_1 + no description available + 27 + 1 + read-only + + + COMBYP_EN_OLD_1 + no description available + 28 + 1 + read-only + + + CYP_EN_OLD_1 + no description available + 29 + 1 + read-only + + + RESERVED + no description available + 30 + 2 + read-only + + + + + DP_FG_POS_ASYNC1 + DP Partial Plane Window Position Async 1 Flow Register + 0x180C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_FGYP_ASYNC1 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + DP_FGXP_ASYNC1 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DP_CUR_POS_ASYNC1 + DP Cursor Postion and Size Async 1 Flow Register + 0x180C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CXW_ASYNC1 + no description available + 0 + 11 + read-write + + + DP_CXP_ASYNC1 + no description available + 11 + 5 + read-write + + + DP_CYH_ASYNC1 + no description available + 16 + 11 + read-write + + + DP_CYP_ASYNC1 + no description available + 27 + 5 + read-write + + + + + DP_CUR_MAP_ASYNC1 + DP Color Cursor Mapping Async 1 Flow Register + 0x180CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CUR_COL_R_ASYNC1 + no description available + 0 + 8 + read-write + + + 00000000 + No Red. + #00000000 + + + 11111111 + Full Red. + #11111111 + + + + + DP_CUR_COL_G_ASYNC1 + no description available + 8 + 8 + read-write + + + 00000000 + No Green. + #00000000 + + + 11111111 + Full Green. + #11111111 + + + + + DP_CUR_COL_B_ASYNC1 + no description available + 16 + 8 + read-write + + + 00000000 + No Blue. + #00000000 + + + 11111111 + Full Blue. + #11111111 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DP_GAMMA_C_ASYNC1_i + DP Gamma Constants Async 1 Flow Register i + 0x180D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_C_ASYNC1_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + DP_GAMMA_C_ASYNC1_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DP_GAMMA_S_ASYN1_i + DP Gamma Correction Slope Async 1 Flow Register i + 0x180F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_GAMMA_S_ASYNC1_4i + no description available + 0 + 8 + read-write + + + DP_GAMMA_S_ASYNC1_4i_1 + no description available + 8 + 8 + read-write + + + DP_GAMMA_S_ASYNC1_4i_2 + no description available + 16 + 8 + read-write + + + DP_GAMMA_S_ASYNC1_4i_3 + no description available + 24 + 8 + read-write + + + + + DP_CSCA_ASYNC1_i + DP Color Space Converstion Control Async 1 Flow Register i + 0x18100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A_ASYNC1_2i + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_A_ASYNC1_2i_1 + no description available + 16 + 10 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + DP_CSC_ASYNC1_0 + DP Color Conversion Control Async 1 Flow Register 0 + 0x18110 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_A8_ASYNC1 + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 6 + read-only + + + DP_CSC_B0_ASYNC1 + no description available + 16 + 14 + read-write + + + DP_CSC_S0_ASYNC1 + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 0 + #10 + + + 11 + scale factor of -1 + #11 + + + + + + + DP_CSC_ASYNC1_1 + DP Color Conversion Control Async 1 Flow Register 1 + 0x18114 + 32 + read-write + 0 + 0xFFFFFFFF + + + DP_CSC_B1_ASYNC1 + no description available + 0 + 14 + read-write + + + DP_CSC_S1_ASYNC1 + no description available + 14 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + DP_CSC_B2_ASYNC1 + no description available + 16 + 14 + read-write + + + DP_CSC_S2_ASYNC1 + no description available + 30 + 2 + read-write + + + 00 + scale factor of 2 + #00 + + + 01 + scale factor of 1 + #01 + + + 10 + scale factor of 011 scale factor of -1 + #10 + + + + + + + IC_CONF + IC Configuration Register + 0x20000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRPENC_EN + no description available + 0 + 1 + read-write + + + 0 + Task is disabled. + #0 + + + 1 + Task is enabled. + #1 + + + + + PRPENC_CSC1 + no description available + 1 + 1 + read-write + + + 0 + Color conversion is disabled. + #0 + + + 1 + Color conversion is enabled. + #1 + + + + + PRPENC_ROT_EN + no description available + 2 + 1 + read-write + + + 0 + Rotation is disabled. + #0 + + + 1 + Rotation is enabled. + #1 + + + + + RESERVED + no description available + 3 + 5 + read-only + + + PRPVF_EN + no description available + 8 + 1 + read-write + + + 0 + Task is disabled. + #0 + + + 1 + Task is enabled. + #1 + + + + + PRPVF_CSC1 + no description available + 9 + 1 + read-write + + + 0 + First color conversion is disabled. + #0 + + + 1 + First color conversion is enabled. + #1 + + + + + PRPVF_CSC2 + no description available + 10 + 1 + read-write + + + PRPVF_CMB + no description available + 11 + 1 + read-write + + + 0 + Combining is disabled. + #0 + + + 1 + Combining is enabled. + #1 + + + + + PRPVF_ROT_EN + no description available + 12 + 1 + read-write + + + 0 + Rotation is disabled. + #0 + + + 1 + Rotation is enabled. + #1 + + + + + RESERVED + no description available + 13 + 3 + read-only + + + PP_EN + no description available + 16 + 1 + read-write + + + 0 + Task is disabled. + #0 + + + 1 + Task is enabled. + #1 + + + + + PP_CSC1 + no description available + 17 + 1 + read-write + + + 0 + YUV-->RGB is disabled. + #0 + + + 1 + YUV-->RGB is enabled. + #1 + + + + + PP_CSC2 + no description available + 18 + 1 + read-write + + + 0 + RGB-->YUV is disabled. + #0 + + + 1 + RGB-->YUV is enabled. + #1 + + + + + PP_CMB + no description available + 19 + 1 + read-write + + + 0 + Combining is disabled. + #0 + + + 1 + Combining is enabled. + #1 + + + + + PP_ROT_EN + no description available + 20 + 1 + read-write + + + 0 + Rotation is disabled. + #0 + + + 1 + Rotation is enabled. + #1 + + + + + RESERVED + no description available + 21 + 7 + read-only + + + IC_GLB_LOC_A + no description available + 28 + 1 + read-write + + + 0 + Alpha parameter is local. + #0 + + + 1 + Alpha parameter is global. + #1 + + + + + IC_KEY_COLOR_EN + no description available + 29 + 1 + read-write + + + 0 + Key color is disabled. + #0 + + + 1 + Key color is enabled. + #1 + + + + + RWS_EN + no description available + 30 + 1 + read-write + + + 0 + Raw sensor is not attached. + #0 + + + 1 + Raw sensor is attached. + #1 + + + + + CSI_MEM_WR_EN + no description available + 31 + 1 + read-write + + + 0 + CSI direct writing to memory is disabled. + #0 + + + 1 + CSI direct writing to memory is enabled. + #1 + + + + + + + IC_PRP_ENC_RSC + IC Preprocessing Encoder Resizing Coefficients Register + 0x20004 + 32 + read-write + 0x20002000 + 0xFFFFFFFF + + + PRPENC_RS_R_H + no description available + 0 + 14 + read-write + + + PRPENC_DS_R_H + no description available + 14 + 2 + read-write + + + 00 + 1 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + RSV + #11 + + + + + PRPENC_RS_R_V + no description available + 16 + 14 + read-write + + + PRPENC_DS_R_V + no description available + 30 + 2 + read-write + + + + + IC_PRP_VF_RSC + IC Preprocessing View-Finder Resizing Coefficients Register + 0x20008 + 32 + read-write + 0x20002000 + 0xFFFFFFFF + + + PRPVF_RS_R_H + no description available + 0 + 14 + read-write + + + PRPVF_DS_R_H + no description available + 14 + 2 + read-write + + + 00 + 1 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + RSV + #11 + + + + + PRPVF_RS_R_V + no description available + 16 + 14 + read-write + + + PRPVF_DS_R_V + no description available + 30 + 2 + read-write + + + + + IC_PP_RSC + IC Postprocessing Encoder Resizing Coefficients Register + 0x2000C + 32 + read-write + 0x20002000 + 0xFFFFFFFF + + + PP_RS_R_H + no description available + 0 + 14 + read-write + + + PP_DS_R_H + no description available + 14 + 2 + read-write + + + 00 + 1 + #00 + + + 01 + 2 + #01 + + + 10 + 4 + #10 + + + 11 + RSV + #11 + + + + + PP_RS_R_V + no description available + 16 + 14 + read-write + + + PP_DS_R_V + no description available + 30 + 2 + read-write + + + + + IC_CMBP_1 + IC Combining Parameters Register 1 + 0x20010 + 32 + read-write + 0 + 0xFFFFFFFF + + + IC_PRPVF_ALPHA_V + no description available + 0 + 8 + read-write + + + IC_PP_ALPHA_V + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + IC_CMBP_2 + IC Combining Parameters Register 2 + 0x20014 + 32 + read-write + 0 + 0xFFFFFFFF + + + IC_KEY_COLOR_B + no description available + 0 + 8 + read-write + + + IC_KEY_COLOR_G + no description available + 8 + 8 + read-write + + + IC_KEY_COLOR_R + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + IC_IDMAC_1 + IC IDMAC Parameters 1 Register + 0x20018 + 32 + read-write + 0 + 0xFFFFFFFF + + + CB0_BURST_16 + no description available + 0 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB1_BURST_16 + no description available + 1 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB2_BURST_16 + no description available + 2 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB3_BURST_16 + no description available + 3 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB4_BURST_16 + no description available + 4 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB5_BURST_16 + no description available + 5 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB6_BURST_16 + no description available + 6 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + CB7_BURST_16 + no description available + 7 + 1 + read-write + + + 0 + Burst size is 8 pixels; The Matching NPB[6:2] should be 00111 + #0 + + + 1 + Burst size is 16 pixels; The Matching NPB[6:2] should be 01111 + #1 + + + + + RESERVED + no description available + 8 + 3 + read-only + + + T1_ROT + no description available + 11 + 1 + read-write + + + 1 + 90 degree rotation clockwise + #1 + + + 0 + no rotation + #0 + + + + + T1_FLIP_LR + no description available + 12 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + T1_FLIP_UD + no description available + 13 + 1 + read-write + + + 1 + Vertical flip enable + #1 + + + 0 + no flip + #0 + + + + + T2_ROT + no description available + 14 + 1 + read-write + + + 1 + 90 degree rotation clockwise + #1 + + + 0 + no rotation + #0 + + + + + T2_FLIP_LR + no description available + 15 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + T2_FLIP_UD + no description available + 16 + 1 + read-write + + + 1 + Vertical flip enable + #1 + + + 0 + no flip + #0 + + + + + T3_ROT + no description available + 17 + 1 + read-write + + + 1 + 90 degree rotation clockwise + #1 + + + 0 + no rotation + #0 + + + + + T3_FLIP_LR + no description available + 18 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + T3_FLIP_UD + no description available + 19 + 1 + read-write + + + 1 + Vertical flip enable + #1 + + + 0 + no flip + #0 + + + + + T1_FLIP_RS + no description available + 20 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + T2_FLIP_RS + no description available + 21 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + T3_FLIP_RS + no description available + 22 + 1 + read-write + + + 1 + horizontal flip enabled + #1 + + + 0 + no flip + #0 + + + + + RESERVED + no description available + 23 + 1 + read-only + + + ALT_CB6_BURST_16 + no description available + 24 + 1 + read-write + + + ALT_CB7_BURST_16 + no description available + 25 + 1 + read-write + + + RESERVED + no description available + 26 + 6 + read-only + + + + + IC_IDMAC_2 + IC IDMAC Parameters 2 Register + 0x2001C + 32 + read-write + 0 + 0xFFFFFFFF + + + T1_FR_HEIGHT + no description available + 0 + 10 + read-write + + + T2_FR_HEIGHT + no description available + 10 + 10 + read-write + + + T3_FR_HEIGHT + no description available + 20 + 10 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IC_IDMAC_3 + IC IDMAC Parameters 3Register + 0x20020 + 32 + read-write + 0 + 0xFFFFFFFF + + + T1_FR_WIDTH + no description available + 0 + 10 + read-write + + + T2_FR_WIDTH + no description available + 10 + 10 + read-write + + + T3_FR_WIDTH + no description available + 20 + 10 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + IC_IDMAC_4 + IC IDMAC Parameters 4 Register + 0x20024 + 32 + read-write + 0 + 0xFFFFFFFF + + + mpm_rw_brdg_max_rq + no description available + 0 + 4 + read-write + + + 0000 + Feature is disabled + #0000 + + + 0001 + Max request is 1 + #0001 + + + 1111 + Max request are15 + #1111 + + + + + mpm_dmfc_brdg_max_rq + no description available + 4 + 4 + read-write + + + 0000 + Feature is disabled + #0000 + + + 0001 + Max request is 1 + #0001 + + + 1111 + Max request are15 + #1111 + + + + + ibm_brdg_max_rq + no description available + 8 + 4 + read-write + + + 0000 + Feature is disabled + #0000 + + + 0001 + Max request is 1 + #0001 + + + 1111 + Max request are15 + #1111 + + + + + rm_brdg_max_rq + no description available + 12 + 4 + read-write + + + 0000 + Feature is disabled + #0000 + + + 0001 + Max request is 1 + #0001 + + + 1111 + Max request are15 + #1111 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + CSI0_SENS_CONF + CSI0 Sensor Configuration Register + 0x30000 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_VSYNC_POL + no description available + 0 + 1 + read-write + + + 0 + IPP_IND_SENSB_VSYNC is not inverted before applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_VSYNC is inverted before applied to internal circuitry. + #1 + + + + + CSI0_HSYNC_POL + no description available + 1 + 1 + read-write + + + 0 + IPP_IND_SENSB_HSYNC is directly applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_HSYNC is inverted before applied to internal circuitry. + #1 + + + + + CSI0_DATA_POL + no description available + 2 + 1 + read-write + + + 0 + data lines are directly applied to internal circuitry. + #0 + + + 1 + data lines are inverted before applied to internal circuitry. + #1 + + + + + CSI0_SENS_PIX_CLK_POL + no description available + 3 + 1 + read-write + + + 0 + pixel clock is directly applied to internal circuitry. + #0 + + + 1 + pixel clock is inverted before applied to internal circuitry. + #1 + + + + + CSI0_SENS_PRTCL + no description available + 4 + 3 + read-write + + + 000 + Gated clock mode + #000 + + + 001 + Non-gated clock mode + #001 + + + 010 + CCIR progressive mode (BT.656) + #010 + + + 011 + CCIR interlaced mode (BT.656) + #011 + + + 100 + CCIR progressive (BT.1120 DDR mode: data arrives on every edge of the clock) + #100 + + + 101 + CCIR progressive (BT.1120 SDR mode: data arrives only on the positive edge of the clock) + #101 + + + 110 + CCIR interlaced mode (BT.1120 DDR mode: data arrives on every edge of the clock) + #110 + + + 111 + CCIR interlaced mode (BT.1120 SDR mode: data arrives only on the positive edge of the clock) + #111 + + + + + CSI0_PACK_TIGHT + no description available + 7 + 1 + read-write + + + 1 + Three 10 bits components are packed into a 32 bit word. Color extension/reduction is performed + #1 + + + 0 + Each component is written as a 16 bit word where the MSB is written to bit #15, color extension is done for the remaining least significant bits. + #0 + + + + + CSI0_SENS_DATA_FORMAT + no description available + 8 + 3 + read-write + + + 000 + full RGB or YUV444 + #000 + + + 001 + YUV422 (YUYV...) + #001 + + + 010 + YUV422 (UYVY...) + #010 + + + 011 + Bayer or Generic data + #011 + + + 100 + RGB565 + #100 + + + 101 + RGB555 + #101 + + + 110 + RGB444 + #110 + + + 111 + JPEG + #111 + + + + + CSI0_DATA_WIDTH + no description available + 11 + 4 + read-write + + + 0000 + 4 bits per color + #0000 + + + 0001 + 8 bits per color + #0001 + + + 0010 + 9 bits per color + #0010 + + + 0011 + 10 bits per color + #0011 + + + 0100 + 11 bits per color + #0100 + + + 0101 + 12 bits per color + #0101 + + + 0110 + 13 bits per color + #0110 + + + 0111 + 14 bits per color + #0111 + + + 1000 + 15 bits per color + #1000 + + + 1001 + 16 bits per color + #1001 + + + + + CSI0_EXT_VSYNC + no description available + 15 + 1 + read-write + + + 0 + Internal VSYNC mode. + #0 + + + 1 + External VSYNC mode. + #1 + + + + + CSI0_DIV_RATIO + no description available + 16 + 8 + read-write + + + CSI0_DATA_DEST + no description available + 24 + 3 + read-write + + + CSI0_JPEG8_EN + no description available + 27 + 1 + read-write + + + 1 + JPEG8 detection is enabled + #1 + + + 0 + JPEG8 is disabled + #0 + + + + + CSI0_JPEG_MODE + no description available + 28 + 1 + read-write + + + 1 + The data is valid as long as HSYNC and VSYNC signals are active; HSYNC is valid for single frame + #1 + + + 0 + The frame starts withe the assertion of VSYNC. The frame ends on the next VSYNC or by setting the CSI0_FORCE_EOF bit. + #0 + + + + + CSI0_FORCE_EOF + no description available + 29 + 1 + read-write + + + 1 + force end of frame + #1 + + + 0 + no action + #0 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + CSI0_DATA_EN_POL + no description available + 31 + 1 + read-write + + + 0 + IPP_IND_SENSB_DATA_EN is directly applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_DATA_EN is inverted before applied to internal circuitry. + #1 + + + + + + + CSI0_SENS_FRM_SIZE + CSI0 Sense Frame Size Register + 0x30004 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_SENS_FRM_WIDTH + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + CSI0_SENS_FRM_HEIGHT + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CSI0_ACT_FRM_SIZE + CSI0 Actual Frame Size Register + 0x30008 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_ACT_FRM_WIDTH + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + CSI0_ACT_FRM_HEIGHT + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CSI0_OUT_FRM_CTRL + CSI0 Output Control Register + 0x3000C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_VSC + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI0_HSC + no description available + 16 + 13 + read-write + + + RESERVED + no description available + 29 + 1 + read-only + + + CSI0_VERT_DWNS + no description available + 30 + 1 + read-write + + + 0 + Downsizing disabled + #0 + + + 1 + Downsizing enabled + #1 + + + + + CSI0_HORZ_DWNS + no description available + 31 + 1 + read-write + + + 0 + Downsizing disabled1 Downsizing enabled + #0 + + + + + + + CSI0_TST_CTRL + CSIO Test Control Register + 0x30010 + 32 + read-write + 0 + 0xFFFFFFFF + + + PG_R_VALUE + no description available + 0 + 8 + read-write + + + PG_G_VALUE + no description available + 8 + 8 + read-write + + + PG_B_VALUE + no description available + 16 + 8 + read-write + + + TEST_GEN_MODE + no description available + 24 + 1 + read-write + + + 0 + Test signal generator is inactive. + #0 + + + 1 + Test signal generator is active. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI0_CCIR_CODE_1 + CSIO CCIR Code Register 1 + 0x30014 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_END_FLD0_BLNK_1ST + no description available + 0 + 3 + read-write + + + CSI0_STRT_FLD0_BLNK_1ST + no description available + 3 + 3 + read-write + + + CSI0_END_FLD0_BLNK_2ND + no description available + 6 + 3 + read-write + + + CSI0_STRT_FLD0_BLNK_2ND + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI0_END_FLD0_ACTV + no description available + 16 + 3 + read-write + + + CSI0_STRT_FLD0_ACTV + no description available + 19 + 3 + read-write + + + RESERVED + no description available + 22 + 2 + read-only + + + CSI0_CCIR_ERR_DET_EN + no description available + 24 + 1 + read-write + + + 0 + Error detection and correction is disabled. + #0 + + + 1 + Error detection and correction is enabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI0_CCIR_CODE_2 + CSIO CCIR Code Register 2 + 0x30018 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_END_FLD1_BLNK_1ST + no description available + 0 + 3 + read-write + + + CSI0_STRT_FLD1_BLNK_1ST + no description available + 3 + 3 + read-write + + + CSI0_END_FLD1_BLNK_2ND + no description available + 6 + 3 + read-write + + + CSI0_STRT_FLD1_BLNK_2ND + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI0_END_FLD1_ACTV + no description available + 16 + 3 + read-write + + + CSI0_STRT_FLD1_ACTV + no description available + 19 + 3 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + CSI0_CCIR_CODE_3 + CSIO CCIR Code Register 3 + 0x3001C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CCIR_PRECOM + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CSI0_DI + CSI0 Data Identifier Register + 0x30020 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CSI0_MIPI_DI0 + no description available + 0 + 8 + read-write + + + CSI0_MIPI_DI1 + no description available + 8 + 8 + read-write + + + CSI0_MIPI_DI2 + no description available + 16 + 8 + read-write + + + CSI0_MIPI_DI3 + no description available + 24 + 8 + read-write + + + + + CSI0_SKIP + CSI0 SKIP Register + 0x30024 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_MAX_RATIO_SKIP_SMFC + no description available + 0 + 3 + read-write + + + CSI0_SKIP_SMFC + no description available + 3 + 5 + read-write + + + CSI0_ID_2_SKIP + no description available + 8 + 2 + read-write + + + 00 + - Skipping mechanism is activated on frames with ID equal to 00 + #00 + + + 01 + - Skipping mechanism is activated on frames with ID equal to 01 + #01 + + + 10 + - Skipping mechanism is activated on frames with ID equal to 10 + #10 + + + 11 + - Skipping mechanism is activated on frames with ID equal to 11 + #11 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + CSIO_CPD_CTRL + CSI0 Compander Control Register + 0x30028 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_GREEN_P_BEGIN + no description available + 0 + 1 + read-write + + + 0 + First component in the frame is blue or red, depending from RED_ROW bit. + #0 + + + 1 + First component in the frame is green + #1 + + + + + CSI0_RED_ROW_BEGIN + no description available + 1 + 1 + read-write + + + 0 + First row in the frame is GBGB. + #0 + + + 1 + First row in the frame is GRGR. + #1 + + + + + CSI0_CPD + no description available + 2 + 3 + read-write + + + RESERVED + no description available + 5 + 27 + read-only + + + + + CSIO_CPD_RC_i + CSI0 Red Component Compander Constants Register <i> + 0x3002C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_RC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI0_CPD_RC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSIO_CPD_RS_i + CSI0 Red Component Compander SLOPE Register <i> + 0x3004C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_RS_4i + no description available + 0 + 8 + read-write + + + CSI0_CPD_RS_4i_1 + no description available + 8 + 8 + read-write + + + CSI0_CPD_RS_4i_2 + no description available + 16 + 8 + read-write + + + CSI0_CPD_RS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSIO_CPD_GRC_i + CSI0 GR Component Compander Constants Register <i> + 0x3005C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_GRC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI0_CPD_GRC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSIO_CPD_GRS_i + CSI0 GR Component Compander SLOPE Register <i> + 0x3007C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_GRS_4i + no description available + 0 + 8 + read-write + + + CSI0_CPD_GRS_4i_1 + no description available + 8 + 8 + read-write + + + CSI0_CPD_GRS_4i_2 + no description available + 16 + 8 + read-write + + + CSI0_CPD_GRS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSIO_CPD_GBC_i + CSI0 GB Component Compander Constants Register <i> + 0x3008C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_GBC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI0_CPD_GBC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSIO_CPD_GBS_i + CSI0 GB Component Compander SLOPE Register <i> + 0x300AC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_GBS_4i + no description available + 0 + 8 + read-write + + + CSI0_CPD_GBS_4i_1 + no description available + 8 + 8 + read-write + + + CSI0_CPD_GBS_4i_2 + no description available + 16 + 8 + read-write + + + CSI0_CPD_GBS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSIO_CPD_BC_i + CSI0 Blue Component Compander Constants Register <i> + 0x300BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_BC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI0_CPD_BC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSIO_CPD_BS_i + CSI0 Blue Component Compander SLOPE Register <i> + 0x300DC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_BS_4i + no description available + 0 + 8 + read-write + + + CSI0_CPD_BS_4i_1 + no description available + 8 + 8 + read-write + + + CSI0_CPD_BS_4i_2 + no description available + 16 + 8 + read-write + + + CSI0_CPD_BS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSI0_CPD_OFFSET1 + CSI0 Compander Offset Register 1 + 0x300EC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_GR_OFFSET + no description available + 0 + 10 + read-write + + + CSI0_GB_OFFSET + no description available + 10 + 10 + read-write + + + CSI0_CPD_B_OFFSET + no description available + 20 + 10 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CSI0_CPD_OFFSET2 + CSI0 Compander Offset Register 2 + 0x300F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI0_CPD_R_OFFSET + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 22 + read-only + + + + + CSI1_SENS_CONF + CSI1 Sensor Configuration Register + 0x38000 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_VSYNC_POL + no description available + 0 + 1 + read-write + + + 0 + IPP_IND_SENSB_VSYNC is not inverted before applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_VSYNC is inverted before applied to internal circuitry. + #1 + + + + + CSI1_HSYNC_POL + no description available + 1 + 1 + read-write + + + 0 + IPP_IND_SENSB_HSYNC is directly applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_HSYNC is inverted before applied to internal circuitry. + #1 + + + + + CSI1_DATA_POL + no description available + 2 + 1 + read-write + + + 0 + data lines are directly applied to internal circuitry. + #0 + + + 1 + data lines are inverted before applied to internal circuitry. + #1 + + + + + CSI1_SENS_PIX_CLK_POL + no description available + 3 + 1 + read-write + + + 0 + pixel clock is directly applied to internal circuitry. + #0 + + + 1 + pixel clock is inverted before applied to internal circuitry. + #1 + + + + + CSI1_SENS_PRTCL + no description available + 4 + 3 + read-write + + + 000 + Gated clock mode + #000 + + + 001 + Non-gated clock mode + #001 + + + 010 + CCIR progressive mode (BT.656) + #010 + + + 011 + CCIR interlaced mode (BT.656) + #011 + + + 100 + CCIR progressive (BT.1120 DDR mode: data arrives on every edge of the clock) + #100 + + + 101 + CCIR progressive (BT.1120 SDR mode: data arrives only on the positive edge of the clock) + #101 + + + 110 + CCIR interlaced mode (BT.1120 DDR mode: data arrives on every edge of the clock) + #110 + + + 111 + CCIR interlaced mode (BT.1120 SDR mode: data arrives only on the positive edge of the clock) + #111 + + + + + CSI1_PACK_TIGHT + no description available + 7 + 1 + read-write + + + 1 + Three 10 bits components are packed into a 32 bit word. Color extension/reduction is performed + #1 + + + 0 + Each component is written as a 16 bit word where the MSB is written to bit #15, color extension is done for the remaining least significant bits. + #0 + + + + + CSI1_SENS_DATA_FORMAT + no description available + 8 + 3 + read-write + + + 000 + full RGB or YUV444 + #000 + + + 001 + YUV422 (YUYV...) + #001 + + + 010 + YUV422 (UYVY...) + #010 + + + 011 + Bayer or Generic data + #011 + + + 100 + RGB565 + #100 + + + 101 + RGB555 + #101 + + + 110 + RGB444 + #110 + + + 111 + JPEG + #111 + + + + + CSI1_DATA_WIDTH + no description available + 11 + 4 + read-write + + + 0000 + 4 bits per color + #0000 + + + 0000 + Reserved + #0000 + + + 0001 + 8 bits per color + #0001 + + + 0010 + 9 bits per color + #0010 + + + 0010 + Reserved + #0010 + + + 0011 + 10 bits per color + #0011 + + + 0100 + 11 bits per color + #0100 + + + 0100 + Reserved + #0100 + + + 0101 + 12 bits per color + #0101 + + + 0101 + Reserved + #0101 + + + 0110 + 13 bits per color + #0110 + + + 0110 + Reserved + #0110 + + + 0111 + 14 bits per color + #0111 + + + 0111 + Reserved + #0111 + + + 1000 + 15 bits per color + #1000 + + + 1000 + Reserved + #1000 + + + 1001 + 16 bits per color + #1001 + + + + + CSI1_EXT_VSYNC + no description available + 15 + 1 + read-write + + + 0 + Internal VSYNC mode. + #0 + + + 1 + External VSYNC mode. + #1 + + + + + CSI1_DIV_RATIO + no description available + 16 + 8 + read-write + + + CSI1_DATA_DEST + no description available + 24 + 3 + read-write + + + CSI1_JPEG8_EN + no description available + 27 + 1 + read-write + + + 1 + JPEG8 detection is enabled + #1 + + + 0 + JPEG8 is disabled + #0 + + + + + CSI1_JPEG_MODE + no description available + 28 + 1 + read-write + + + 1 + The data is valid as long as HSYNC and VSYNC signals are active; HSYNC is valid for single frame + #1 + + + 0 + The frame starts withe the assertion of VSYNC. The frame ends on the next VSYNC or by setting the CSI0_FORCE_EOF bit + #0 + + + + + CSI1_FORCE_EOF + no description available + 29 + 1 + read-write + + + 1 + force end of frame + #1 + + + 0 + no action + #0 + + + + + RESERVED + no description available + 30 + 1 + read-only + + + CSI0_DATA_EN_POL + no description available + 31 + 1 + read-write + + + 0 + IPP_IND_SENSB_DATA_EN is directly applied to internal circuitry. + #0 + + + 1 + IPP_IND_SENSB_DATA_EN is inverted before applied to internal circuitry. + #1 + + + + + + + CSI1_SENS_FRM_SIZE + CSI1 Sense Frame Size Register + 0x38004 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_SENS_FRM_WIDTH + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + CSI1_SENS_FRM_HEIGHT + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CSI1_ACT_FRM_SIZE + CSI1 Actual Frame Size Register + 0x38008 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_ACT_FRM_WIDTH + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + CSI1_ACT_FRM_HEIGHT + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + CSI1_OUT_FRM_CTRL + CSI1 Output Control Register + 0x3800C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_VSC + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI1_HSC + no description available + 16 + 13 + read-write + + + RESERVED + no description available + 29 + 1 + read-only + + + CSI1_VERT_DWNS + no description available + 30 + 1 + read-write + + + 0 + Downsizing disabled + #0 + + + 1 + Downsizing enabled + #1 + + + + + CSI1_HORZ_DWNS + no description available + 31 + 1 + read-write + + + 0 + Downsizing disabled1 Downsizing enabled + #0 + + + + + + + CSI1_TST_CTRL + CSI1 Test Control Register + 0x38010 + 32 + read-write + 0 + 0xFFFFFFFF + + + PG_R_VALUE + no description available + 0 + 8 + read-write + + + PG_G_VALUE + no description available + 8 + 8 + read-write + + + PG_B_VALUE + no description available + 16 + 8 + read-write + + + TEST_GEN_MODE + no description available + 24 + 1 + read-write + + + 0 + Test signal generator is inactive. + #0 + + + 1 + Test signal generator is active. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CCIR_CODE_1 + CSI1 CCIR Code Register 1 + 0x38014 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_END_FLD0_BLNK_1ST + no description available + 0 + 3 + read-write + + + CSI1_STRT_FLD0_BLNK_1ST + no description available + 3 + 3 + read-write + + + CSI1_END_FLD0_BLNK_2ND + no description available + 6 + 3 + read-write + + + CSI1_STRT_FLD0_BLNK_2ND + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI1_END_FLD0_ACTV + no description available + 16 + 3 + read-write + + + CSI1_STRT_FLD0_ACTV + no description available + 19 + 3 + read-write + + + RESERVED + no description available + 22 + 2 + read-only + + + CSI1_CCIR_ERR_DET_EN + no description available + 24 + 1 + read-write + + + 0 + Error detection and correction is disabled. + #0 + + + 1 + Error detection and correction is enabled. + #1 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CCIR_CODE_2 + CSI1 CCIR Code Register 2 + 0x38018 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_END_FLD1_BLNK_1ST + no description available + 0 + 3 + read-write + + + CSI1_STRT_FLD1_BLNK_1ST + no description available + 3 + 3 + read-write + + + CSI1_END_FLD1_BLNK_2ND + no description available + 6 + 3 + read-write + + + CSI1_STRT_FLD1_BLNK_2ND + no description available + 9 + 3 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + CSI1_END_FLD1_ACTV + no description available + 16 + 3 + read-write + + + CSI1_STRT_FLD1_ACTV + no description available + 19 + 3 + read-write + + + RESERVED + no description available + 22 + 10 + read-only + + + + + CSI1_CCIR_CODE_3 + CSI1 CCIR Code Register 3 + 0x3801C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CCIR_PRECOM + no description available + 0 + 30 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CSI1_DI + CSI1 Data Identifier Register + 0x38020 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CSI1_MIPI_DI0 + no description available + 0 + 8 + read-write + + + CSI0_MIPI_DI1 + no description available + 8 + 8 + read-write + + + CSI1_MIPI_DI2 + no description available + 16 + 8 + read-write + + + CSI1_MIPI_DI3 + no description available + 24 + 8 + read-write + + + + + CSI1_SKIP + CSI1 SKIP Register + 0x38024 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_MAX_RATIO_SKIP_SMFC + no description available + 0 + 3 + read-write + + + CSI1_SKIP_SMFC + no description available + 3 + 5 + read-write + + + CSI1_ID_2_SKIP + no description available + 8 + 2 + read-write + + + 00 + - Skipping mechanism is activated on frames with ID equal to 00 + #00 + + + 01 + - Skipping mechanism is activated on frames with ID equal to 01 + #01 + + + 10 + - Skipping mechanism is activated on frames with ID equal to 10 + #10 + + + 11 + - Skipping mechanism is activated on frames with ID equal to 11 + #11 + + + + + RESERVED + no description available + 10 + 22 + read-only + + + + + CSI1_CPD_CTRL + CSI1 Compander Control Register + 0x38028 + 32 + read-only + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + RESERVED + no description available + 1 + 1 + read-only + + + RESERVED + no description available + 2 + 3 + read-only + + + RESERVED + no description available + 5 + 27 + read-only + + + + + CSI1_CPD_RC_i + CSI1 Red Component Compander Constants Register <i> + 0x3802C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_RC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI1_CPD_RC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CPD_RS_i + CSI1 Red Component Compander SLOPE Register <i> + 0x3804C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_RS_4i + no description available + 0 + 8 + read-write + + + CSI1_CPD_RS_4i_1 + no description available + 8 + 8 + read-write + + + CSI1_CPD_RS_4i_2 + no description available + 16 + 8 + read-write + + + CSI1_CPD_RS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSI1_CPD_GRC_i + CSI1 GR Component Compander Constants Register <i> + 0x3805C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_GRC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI1_CPD_GRC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CPD_GRS_i + CSI1 GR Component Compander SLOPE Register <i> + 0x3807C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_GRS_4i + no description available + 0 + 8 + read-write + + + CSI1_CPD_GRS_4i_1 + no description available + 8 + 8 + read-write + + + CSI1_CPD_GRS_4i_2 + no description available + 16 + 8 + read-write + + + CSI1_CPD_GRS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSI1_CPD_GBC_i + CSI1 GB Component Compander Constants Register <i> + 0x3808C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_GBC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI1_CPD_GBC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CPD_GBS_i + CSI1 GB Component Compander SLOPE Register <i> + 0x380AC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_GBS_4i + no description available + 0 + 8 + read-write + + + CSI1_CPD_GBS_4i_1 + no description available + 8 + 8 + read-write + + + CSI1_CPD_GBS_4i_2 + no description available + 16 + 8 + read-write + + + CSI1_CPD_GBS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSI1_CPD_BC_i + CSI1 Blue Component Compander Constants Register <i> + 0x380BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_BC_2i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + CSI1_CPD_BC_2i_1 + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + CSI1_CPD_BS_i + CSI1 Blue Component Compander SLOPE Register <i> + 0x380DC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_BS_4i + no description available + 0 + 8 + read-write + + + CSI1_CPD_BS_4i_1 + no description available + 8 + 8 + read-write + + + CSI1_CPD_BS_4i_2 + no description available + 16 + 8 + read-write + + + CSI1_CPD_BS_4i_3 + no description available + 24 + 8 + read-write + + + + + CSI1_CPD_OFFSET1 + CSI1 Compander Offset Register 1 + 0x380EC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_GR_OFFSET + no description available + 0 + 10 + read-write + + + CSI1_CPD_GB_OFFSET + no description available + 10 + 10 + read-write + + + CSI1_CPD_B_OFFSET + no description available + 20 + 10 + read-write + + + RESERVED + no description available + 30 + 2 + read-only + + + + + CSI1_CPD_OFFSET2 + CSI1 Compander Offset Register 2 + 0x380F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSI1_CPD_R_OFFSET + no description available + 0 + 10 + read-write + + + RESERVED + no description available + 10 + 22 + read-only + + + + + DI0_GENERAL + DI0 General Register + 0x40000 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + di0_polarity_i_1 + no description available + 0 + 8 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + di0_polarity_cs0 + no description available + 8 + 1 + read-write + + + 1 + The CS0 is active high + #1 + + + 0 + The CS0 is active low + #0 + + + + + di0_polarity_cs1 + no description available + 9 + 1 + read-write + + + 1 + The CS1 is active high + #1 + + + 0 + The CS1 is active low + #0 + + + + + di0_erm_vsync_sel + no description available + 10 + 1 + read-write + + + 1 + vsync_post - an internal VSYNC signal asserted 2 lines after the DI's VSYNC + #1 + + + 0 + vsync_pre - an internal VSYNC signal asserted 2 lines before the DI's VSYNC + #0 + + + + + di0_err_treatment + no description available + 11 + 1 + read-write + + + 1 + to wait (stop clock) + #1 + + + 0 + Drive the last component + #0 + + + + + di0_sync_count_sel + no description available + 12 + 4 + read-write + + + RESERVED + no description available + 16 + 1 + read-only + + + di0_polarity_disp_clk + no description available + 17 + 1 + read-write + + + 1 + The output clock is active high + #1 + + + 0 + The output clock is active low + #0 + + + + + DI0_WATCHDOG_MODE + no description available + 18 + 2 + read-write + + + 00 + The timer counts 4 DI cycles + #00 + + + 01 + The timer counts 16 DI cycles + #01 + + + 10 + The timer counts 64 DI cycles + #10 + + + 11 + The timer counts 128 DI cycles + #11 + + + + + di0_clk_ext + no description available + 20 + 1 + read-write + + + 1 + The source of the clock is external to the IPU + #1 + + + 0 + The clock is internally generated by the IPU + #0 + + + + + di0_vsync_ext + no description available + 21 + 1 + read-write + + + 1 + External to the IPU + #1 + + + 0 + Internally generated by the IPU + #0 + + + + + di0_mask_sel + no description available + 22 + 1 + read-write + + + 1 + IPP_PIN_2 is coming from extracted MASK data coming from the memory + #1 + + + 0 + IPP_PIN_2 is coming from counter #2 + #0 + + + + + DI0_DISP_CLOCK_INIT + no description available + 23 + 1 + read-write + + + 1 + The display's clock is running after the next VSYNC (indicating new frame) + #1 + + + 0 + The display's clock is stopped after the next VSYNC (indicating new frame) + #0 + + + + + DI0_CLOCK_STOP_MODE + no description available + 24 + 4 + read-write + + + 0000 + stop at the next edge of the display clock + #0000 + + + 1100 + stop at EOL (end of a line), but if stop request is during blanking interval, stop now + #1100 + + + 1101 + stop at EOF (end of a frame), but if stop request is during blanking interval, stop now + #1101 + + + 1110 + stop at EOL (end of a line), but if stop request is during blanking interval, stop at the end of the next line + #1110 + + + 1111 + stop at EOF (end of a frame), but if stop request is during blanking interval, stop at the end of the next frame + #1111 + + + + + di0_disp_y_sel + no description available + 28 + 3 + read-write + + + 000 + counter #1 is selected + #000 + + + 111 + counter #8 is selected + #111 + + + + + di0_pin8_pin15_sel + no description available + 31 + 1 + read-write + + + 1 + PIN8 is routed to PIN15, PIN8 is also routed to PIN8 + #1 + + + 0 + PIN15 is routed to PIN15, PIN8 is routed to PIN8 + #0 + + + + + + + DI0_BS_CLKGEN0 + DI0 Base Sync Clock Gen 0 Register + 0x40004 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_disp_clk_period + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + di0_disp_clk_offset + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_BS_CLKGEN1 + DI0 Base Sync Clock Gen 1 Register + 0x40008 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_disp_clk_up + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di0_disp_clk_down + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_SW_GEN0_1 + DI0 Sync Wave Gen 1 Register 0 + 0x4000C + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_1 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock + #001 + + + 010 + NA + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_1 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_1 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + NA + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_1 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_2 + DI0 Sync Wave Gen 2 Register 0 + 0x40010 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_2 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSIs according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_2 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_2 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_2 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_3 + DI0 Sync Wave Gen 3 Register 0 + 0x40014 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_3 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_3 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_3 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_3 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_4 + DI0 Sync Wave Gen 4 Register 0 + 0x40018 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_4 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_4 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_4 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_4 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_5 + DI0 Sync Wave Gen 5 Register 0 + 0x4001C + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_5 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + -The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_5 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_5 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_5 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_6 + DI0 Sync Wave Gen 6 Register 0 + 0x40020 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_6 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_6 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_6 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_6 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_7 + DI0 Sync Wave Gen 7 Register 0 + 0x40024 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_1 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_7 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_7 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_7 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_8 + DI0 Sync Wave Gen 8 Register 0 + 0x40028 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_8 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_8 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_8 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_8 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN0_9 + DI0 Sync Wave Gen 9 Register 0 + 0x4002C + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_offset_resolution_9 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_offset_value_9 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_run_resolution_9 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_run_value_m1_9 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_1 + DI0 Sync Wave Gen 1 Register 1 + 0x40030 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_1 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_1 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_1 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_1 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_1 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_1 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_1 field + #0 + + + + + di0_cnt_polarity_gen_en_1 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_2 + DI0 Sync Wave Gen 2 Register 1 + 0x40034 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_2 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_2 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_2 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_2 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_2 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_2 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_2 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_3 + DI0 Sync Wave Gen 3 Register 1 + 0x40038 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_3 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_3 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_3 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_3 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_3 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_3 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_3 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_4 + DI0 Sync Wave Gen 4 Register 1 + 0x4003C + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_4 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_4 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_4 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_4 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_4 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_4 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_4 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_5 + DI0 Sync Wave Gen 5 Register 1 + 0x40040 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_5 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_5 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_5 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_5 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_5 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_5 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_5 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_6 + DI0 Sync Wave Gen 6 Register 1 + 0x40044 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_6 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_6 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Reserved + #111 + + + + + di0_cnt_polarity_trigger_sel_6 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_6 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_6 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_6 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_6 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_7 + DI0 Sync Wave Gen 7 Register 1 + 0x40048 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_7 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_7 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Output is inverted if the output of counter #6 is set + #111 + + + + + di0_cnt_polarity_trigger_sel_7 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_7 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_7 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_7 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_7 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_8 + DI0 Sync Wave Gen 8 Register 1 + 0x4004C + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_8 + no description available + 0 + 9 + read-write + + + di0_cnt_polarity_clr_sel_8 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Output is inverted if the output of counter #6 is set + #111 + + + + + di0_cnt_polarity_trigger_sel_8 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di0_cnt_down_8 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_8 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_8 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_cnt_polarity_gen_en_8 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI0_SW_GEN1_9 + DI0 Sync Wave Gen 9 Register 1 + 0x40050 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_cnt_up_9 + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 6 + read-only + + + di0_tag_sel_9 + no description available + 15 + 1 + read-write + + + 1 + tag source is counter #9 + #1 + + + 0 + Tag's source is the triggering counter. + #0 + + + + + di0_cnt_down_9 + no description available + 16 + 9 + read-write + + + di0_cnt_clr_sel_9 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di0_cnt_auto_reload_9 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di0_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di0_step_repeat_<i> field + #0 + + + + + di0_gentime_sel_9 + no description available + 29 + 3 + read-write + + + 000 + Counter #9's waveform is attached to counter #1's waveform + #000 + + + 001 + Counter #9's waveform is attached to counter #2's waveform + #001 + + + 010 + Counter #9's waveform is attached to counter #3's waveform + #010 + + + 011 + Counter #9's waveform is attached to counter #4's waveform + #011 + + + 100 + Counter #9's waveform is attached to counter #5's waveform + #100 + + + 101 + Counter #9's waveform is attached to counter #6's waveform + #101 + + + 110 + Counter #9's waveform is attached to counter #7's waveform + #110 + + + 111 + Counter #9's waveform is attached to counter #8's waveform + #111 + + + + + + + DI0_SYNC_AS_GEN + DI0 Sync Assistance Gen Register + 0x40054 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_sync_start + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 1 + read-only + + + di0_vsync_sel + no description available + 13 + 3 + read-write + + + 000 + VSYNC is coming from counter #1 + #000 + + + 001 + VSYNC is coming from counter #2 + #001 + + + 111 + VSYNC is coming from counter #8 + #111 + + + + + RESERVED + no description available + 16 + 12 + read-only + + + di0_sync_start_en + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DI0_DW_GEN_i + DI0 Data Wave Gen <i> Register + 0x40058 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_pt_0_i + no description available + 0 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_1_i + no description available + 2 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_2_i + no description available + 4 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_3_i + no description available + 6 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_4_i + no description available + 8 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_5_i + no description available + 10 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_pt_6_i + no description available + 12 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_cst_i + no description available + 14 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI0_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI0_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI0_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI0_DW_SET3_<i> + #11 + + + + + di0_componnent_size_i + no description available + 16 + 8 + read-write + + + di0_access_size_i + no description available + 24 + 8 + read-write + + + + + DI0_DW_SET0_i + DI0 Data Wave Set 0 <i> Register + 0x40088 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_data_cnt_up0_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di0_data_cnt_down0_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_DW_SET1_i + DI0 Data Wave Set 1 <i> Register + 0x400B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_data_cnt_up1_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di0_data_cnt_down1_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_DW_SET2_i + DI0 Data Wave Set 2 <i> Register + 0x400E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_data_cnt_up2_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di0_data_cnt_down2_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_DW_SET3_i + DI0 Data Wave Set 3 <i> Register + 0x40118 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_data_cnt_up3_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di0_data_cnt_down3_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI0_STP_REP_i + DI0 Step Repeat <i> Registers + 0x40148 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_step_repeat_2i_minus_1 + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + di0_step_repeat_2i + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DI0_STP_REP_9 + DI0 Step Repeat 9 Registers + 0x40158 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_step_repeat_9 + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + DI0_SER_CONF + DI0 Serial Display Control Register + 0x4015C + 32 + read-write + 0 + 0xFFFFFFFF + + + DI0_WAIT4SERIAL + no description available + 0 + 1 + read-write + + + 1 + The parallel port should wait to the serial port as the pins are shared + #1 + + + 0 + The parallel port should not wait to the serial port as the pins are not shared + #0 + + + + + DI0_SERIAL_CS_POLARITY + no description available + 1 + 1 + read-write + + + 1 + The CS is inverted + #1 + + + 0 + The CS is not inverted + #0 + + + + + DI0_SERIAL_RS_POLARITY + no description available + 2 + 1 + read-write + + + 1 + The RS is inverted + #1 + + + 0 + The RS is not inverted + #0 + + + + + DI0_SERIAL_DATA_POLARITY + no description available + 3 + 1 + read-write + + + 1 + The data is inverted + #1 + + + 0 + The data is not inverted + #0 + + + + + DI0_SER_CLK_POLARITY + no description available + 4 + 1 + read-write + + + 1 + The clock is inverted + #1 + + + 0 + The clock is not inverted + #0 + + + + + DI0_LLA_SER_ACCESS + no description available + 5 + 1 + read-write + + + 1 + ARM platform access is performed via a direct path to the serial display in LLA mode, in this mode only the ARM platform in LLA mode can access the serial port + #1 + + + 0 + ARM platform access to the serial display port is not done directly, hence other source are allowed to access the serial port. The arbitration is done automatically + #0 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + DI0_SERIAL_LATCH + no description available + 8 + 8 + read-write + + + DI0_SERIAL_LLA_PNTR_RS_W_0 + no description available + 16 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI0_SERIAL_LLA_PNTR_RS_W_1 + no description available + 20 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI0_SERIAL_LLA_PNTR_RS_R_0 + no description available + 24 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI0_SERIAL_LLA_PNTR_RS_R_1 + no description available + 28 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + + + DI0_SSC + DI0 Special Signals Control Register + 0x40160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI0_BYTE_EN_PNTR + no description available + 0 + 3 + read-write + + + 000 + wave form of byte enable as pin_11 + #000 + + + 001 + wave form of byte enable as pin_12 + #001 + + + 111 + wave form of byte enable as suitable CS pin + #111 + + + + + DI0_BYTE_EN_RD_IN + no description available + 3 + 1 + read-write + + + 1 + The write byte enable signals are routed via bits [17:16] of the display's data, The read byte enable signals are routed via bits [19:18 of the display's data + #1 + + + 0 + The byte enable signals are routed via bits [17:16] of the display's data for both read and write + #0 + + + + + RESERVED + no description available + 4 + 1 + read-only + + + DI0_WAIT_ON + no description available + 5 + 1 + read-write + + + 1 + The DC holds the flow as long as WAIT is asserted + #1 + + + 0 + The DC continues the flow regardless the WAIT signal + #0 + + + + + RESERVED + no description available + 6 + 10 + read-only + + + DI0_CS_ERM + no description available + 16 + 1 + read-write + + + 1 + The GLUELOGIC is release in case of a synchronous display error. The release will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the GLUELOGIC following a display error detection + #0 + + + + + DI0_PIN11_ERM + no description available + 17 + 1 + read-write + + + 1 + The PIN11 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN11 pin following a display error detection + #0 + + + + + DI0_PIN12_ERM + no description available + 18 + 1 + read-write + + + 1 + The PIN12 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN12 pin following a display error detection + #0 + + + + + DI0_PIN13_ERM + no description available + 19 + 1 + read-write + + + 1 + The PIN13 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN13 pin following a display error detection + #0 + + + + + DI0_PIN14_ERM + no description available + 20 + 1 + read-write + + + 1 + The PIN14 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN14 pin following a display error detection + #0 + + + + + DI0_PIN15_ERM + no description available + 21 + 1 + read-write + + + 1 + The PIN15 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN15 pin following a display error detection + #0 + + + + + DI0_PIN16_ERM + no description available + 22 + 1 + read-write + + + 1 + The PIN16 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN16 pin following a display error detection + #0 + + + + + DI0_PIN17_ERM + no description available + 23 + 1 + read-write + + + 1 + The PIN17 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC + #1 + + + 0 + Nothing is done to the PIN17 pin following a display error detection + #0 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DI0_POL + DI0 Polarity Register + 0x40164 + 32 + read-write + 0 + 0xFFFFFFFF + + + di0_drdy_polarity + no description available + 0 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI0_DRDY_DATA_POLARITY + no description available + 7 + 1 + read-write + + + di0_cs0_polarity + no description available + 8 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI0_CS0_DATA_POLARITY + no description available + 15 + 1 + read-write + + + di0_cs1_polarity + no description available + 16 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI0_CS1_DATA_POLARITY + no description available + 23 + 1 + read-write + + + DI0_CS0_BYTE_EN_POLARITY + no description available + 24 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + DI0_CS1_BYTE_EN_POLARITY + no description available + 25 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + DI0_WAIT_POLARITY + no description available + 26 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DI0_AW0 + DI0 Active Window 0 Register + 0x40168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI0_AW_HSTART + no description available + 0 + 12 + read-write + + + DI0_AW_HCOUNT_SEL + no description available + 12 + 4 + read-write + + + 0000 + disabled + #0000 + + + 0001 + reserved + #0001 + + + 0010 + The counter is counter #1 + #0010 + + + 0011 + The counter is counter #2 + #0011 + + + 0100 + The counter is counter #3 + #0100 + + + 0101 + The counter is counter #4 + #0101 + + + 0110 + The counter is counter #5 + #0110 + + + 1001 + The counter is counter #8 + #1001 + + + + + DI0_AW_HEND + no description available + 16 + 12 + read-write + + + DI0_AW_TRIG_SEL + no description available + 28 + 4 + read-write + + + 000 + disabled + #000 + + + 001 + The trigger is the same trigger that triggers the displays clock. + #001 + + + 010 + The trigger is counter #1 + #010 + + + 011 + The trigger is counter #2 + #011 + + + 100 + The trigger is counter #3 + #100 + + + 101 + The trigger is counter #4 + #101 + + + 110 + The trigger is counter #5 + #110 + + + 111 + The trigger is always on. + #111 + + + + + + + DI0_AW1 + DI0 Active Window 1 Register + 0x4016C + 32 + read-write + 0 + 0xFFFFFFFF + + + DI0_AW_VSTART + no description available + 0 + 12 + read-write + + + DI0_AW_VCOUNT_SEL + no description available + 12 + 4 + read-write + + + 0000 + disabled + #0000 + + + 0001 + reserved + #0001 + + + 0010 + The counter is counter #1 + #0010 + + + 0011 + The counter is counter #2 + #0011 + + + 0100 + The counter is counter #3 + #0100 + + + 0101 + The counter is counter #4 + #0101 + + + 0110 + The counter is counter #5 + #0110 + + + 1001 + The counter is counter #8 + #1001 + + + + + DI0_AW_VEND + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DI0_SCR_CONF + DI0 Screen Configuration Register + 0x40170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI0_SCREEN_HEIGHT + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + DI0_STAT + DI0 Status Register + 0x40174 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + DI0_READ_FIFO_EMPTY + no description available + 0 + 1 + read-only + + + DI0_READ_FIFO_FULL + no description available + 1 + 1 + read-only + + + DI0_READ_CNTR_EMPTY + no description available + 2 + 1 + read-only + + + DI0_CNTR_FIFO_FULL + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + DI1_GENERAL + DI1General Register + 0x48000 + 32 + read-write + 0x200000 + 0xFFFFFFFF + + + di1_polarity_i_1 + no description available + 0 + 8 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + di1_polarity_cs0 + no description available + 8 + 1 + read-write + + + 1 + The CS0 is active high + #1 + + + 0 + The CS0 is active low + #0 + + + + + di1_polarity_cs1 + no description available + 9 + 1 + read-write + + + 1 + The CS1 is active high + #1 + + + 0 + The CS1 is active low + #0 + + + + + di1_erm_vsync_sel + no description available + 10 + 1 + read-write + + + 1 + vsync_post - an internal VSYNC signal asserted 2 lines after the DI's VSYNC + #1 + + + 0 + vsync_pre - an internal VSYNC signal asserted 2 lines before the DI's VSYNC + #0 + + + + + di1_err_treatment + no description available + 11 + 1 + read-write + + + 1 + to wait (i.e. stop clock) + #1 + + + 0 + Drive the last component + #0 + + + + + di1_sync_count_sel + no description available + 12 + 4 + read-write + + + RESERVED + no description available + 16 + 1 + read-only + + + di1_polarity_disp_clk + no description available + 17 + 1 + read-write + + + 1 + The output clock is active high + #1 + + + 0 + The output clock is active low + #0 + + + + + DI1_WATCHDOG_MODE + no description available + 18 + 2 + read-write + + + 00 + The timer counts 4 DI cycles + #00 + + + 01 + The timer counts 16 DI cycles + #01 + + + 10 + The timer counts 64 DI cycles + #10 + + + 11 + The timer counts 128 DI cycles + #11 + + + + + di1_clk_ext + no description available + 20 + 1 + read-write + + + 1 + The source of the clock is external to the IPU + #1 + + + 0 + The clock is internally generated by the IPU + #0 + + + + + di1_vsync_ext + no description available + 21 + 1 + read-write + + + 1 + External to the IPU + #1 + + + 0 + Internally generated by the IPU + #0 + + + + + di1_mask_sel + no description available + 22 + 1 + read-write + + + 1 + IPP_PIN_2 is coming from extracted MASK data coming from the memory + #1 + + + 0 + IPP_PIN_2 is coming from counter #2 + #0 + + + + + DI1_DISP_CLOCK_INIT + no description available + 23 + 1 + read-write + + + 1 + The display's clock is running after the next VSYNC (indicating new frame) + #1 + + + 0 + The display's clock is stopped after the next VSYNC (indicating new frame) + #0 + + + + + DI1_CLOCK_STOP_MODE + no description available + 24 + 4 + read-write + + + 0000 + stop at the next edge of the display clock + #0000 + + + 1100 + stop at EOL (end of a line), but if stop request is during blanking interval, stop now + #1100 + + + 1101 + stop at EOF (end of a frame), but if stop request is during blanking interval, stop now + #1101 + + + 1110 + stop at EOL (end of a line), but if stop request is during blanking interval, stop at the end of the next line + #1110 + + + 1111 + stop at EOF (end of a frame), but if stop request is during blanking interval, stop at the end of the next frame + #1111 + + + + + di1_disp_y_sel + no description available + 28 + 3 + read-write + + + 000 + counter #1 is selected + #000 + + + 111 + counter #8 is selected + #111 + + + + + di1_pin8_pin15_sel + no description available + 31 + 1 + read-write + + + 1 + PIN8 is routed to PIN15, PIN8 is also routed to PIN8 + #1 + + + 0 + PIN15 is routed to PIN15, PIN8 is routed to PIN8 + #0 + + + + + + + DI1_BS_CLKGEN0 + DI1 Base Sync Clock Gen 0 Register + 0x48004 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_disp_clk_period + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + di1_disp_clk_offset + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI1_BS_CLKGEN1 + DI1 Base Sync Clock Gen 1 Register + 0x48008 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_disp_clk_up + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di1_disp_clk_down + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI1_SW_GEN0_1 + DI1 Sync Wave Gen 1 Register 0 + 0x4800C + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_1 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + NA + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_1 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_1 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + NA + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_1 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_2 + DI1 Sync Wave Gen 2 Register 0 + 0x48010 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_2 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_2 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_2 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + NA + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_2 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_3 + DI1 Sync Wave Gen 3 Register 0 + 0x48014 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_3 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_3 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_3 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + NA + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_3 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_4 + DI1 Sync Wave Gen 4 Register 0 + 0x48018 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_4 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_4 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_4 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_4 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_5 + DI1 Sync Wave Gen 5 Register 0 + 0x4801C + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_5 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + -The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_5 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_5 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_5 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_6 + DI1 Sync Wave Gen 6 Register 0 + 0x48020 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_6 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_6 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_6 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_6 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_7 + DI1 Sync Wave Gen 7 Register 0 + 0x48024 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_1 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_7 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_7 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_7 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_8 + DI1 Sync Wave Gen 8 Register 0 + 0x48028 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_8 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_8 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_8 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_8 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN0_9 + DI1Sync Wave Gen 9 Register 0 + 0x4802C + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_offset_resolution_9 + no description available + 0 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_offset_value_9 + no description available + 3 + 12 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_run_resolution_9 + no description available + 16 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_run_value_m1_9 + no description available + 19 + 12 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_1 + DI1 Sync Wave Gen 1 Register 1 + 0x48030 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_1 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_1 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_1 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_1 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_1 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_1 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_1 field + #0 + + + + + di1_cnt_polarity_gen_en_1 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_2 + DI1 Sync Wave Gen 2 Register 1 + 0x48034 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_2 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_2 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Reserved + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_2 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_2 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_2 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + Reserved + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_2 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_2 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_3 + DI1 Sync Wave Gen 3 Register 1 + 0x48038 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_3 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_3 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Reserved + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_3 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_3 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_3 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + Reserved + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_3 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_3 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_4 + DI1 Sync Wave Gen 4 Register 1 + 0x4803C + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_4 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_4 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_4 + no description available + 12 + 3 + read-write + + + 000 + - Counter is disabled + #000 + + + 001 + - The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + - The Counter is triggered by counter #1 + #010 + + + 011 + - The Counter is triggered by counter #2 + #011 + + + 100 + - The Counter is triggered by counter #3 + #100 + + + 101 + - CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_4 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_4 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + CSI VSYNC. The VSYNC is a trigger coming from one of the CSI's according to the CSI_VSYNC_DEST bit. + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_4 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_4 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_5 + DI1 Sync Wave Gen 5 Register 1 + 0x48040 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_5 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_5 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_5 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_5 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_5 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + External VSYNC + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_5 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_5 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_6 + DI1 Sync Wave Gen 6 Register 1 + 0x48044 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_6 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_6 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Reserved + #111 + + + + + di1_cnt_polarity_trigger_sel_6 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_6 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_6 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_6 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_6 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_7 + DI1Sync Wave Gen 7 Register 1 + 0x48048 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_7 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_7 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Output is inverted if the output of counter #6 is set + #111 + + + + + di1_cnt_polarity_trigger_sel_7 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_7 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_7 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_7 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_cnt_polarity_gen_en_7 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_8 + DI1 Sync Wave Gen 8 Register 1 + 0x4804C + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_8 + no description available + 0 + 9 + read-write + + + di1_cnt_polarity_clr_sel_8 + no description available + 9 + 3 + read-write + + + 000 + Output is always inverted + #000 + + + 001 + Output is kept the same (no inversion) + #001 + + + 010 + Output is inverted if the output of counter #1 is set + #010 + + + 011 + Output is inverted if the output of counter #2 is set + #011 + + + 100 + Output is inverted if the output of counter #3 is set + #100 + + + 101 + Output is inverted if the output of counter #4 is set + #101 + + + 110 + Output is inverted if the output of counter #5 is set + #110 + + + 111 + Output is inverted if the output of counter #6 is set + #111 + + + + + di1_cnt_polarity_trigger_sel_8 + no description available + 12 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + RESERVED + no description available + 15 + 1 + read-only + + + di1_cnt_down_8 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_8 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_8 + no description available + 28 + 1 + read-write + + + di1_cnt_polarity_gen_en_8 + no description available + 29 + 2 + read-write + + + 00 + Dynamic polarity change is disabled + #00 + + + 01 + The counters UP and DOWN value are calculated according to the trigger selected by cnt_polarity_trigger_sel field. When selecting this mode the UP and DOWN values has to be a multiple of 2. + #01 + + + 10 + Dynamic polarity change is enabled + #10 + + + 11 + Outputs polarity is dynamically changed every time the counter reaches its pre defined value + #11 + + + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DI1_SW_GEN1_9 + DI1 Sync Wave Gen 9 Register 1 + 0x48050 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_cnt_up_9 + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 6 + read-only + + + di1_tag_sel_9 + no description available + 15 + 1 + read-write + + + 1 + tag source is counter #9 + #1 + + + 0 + Tag's source is the triggering counter. + #0 + + + + + di1_cnt_down_9 + no description available + 16 + 9 + read-write + + + di1_cnt_clr_sel_9 + no description available + 25 + 3 + read-write + + + 000 + Counter is disabled + #000 + + + 001 + The counter is triggered by the same trigger that triggers the displays clock. + #001 + + + 010 + The Counter is triggered by counter #1 + #010 + + + 011 + The Counter is triggered by counter #2 + #011 + + + 100 + The Counter is triggered by counter #3 + #100 + + + 101 + The Counter is triggered by counter #4 + #101 + + + 110 + The Counter is triggered by counter #5 + #110 + + + 111 + Counter is always on. + #111 + + + + + di1_cnt_auto_reload_9 + no description available + 28 + 1 + read-write + + + 1 + The counter will automatically be reloaded forever, ignoring the value of the di1_step_repeat_<i> field + #1 + + + 0 + The counter will not be automatically reloaded, It will be reloaded for the amount of repeat times defined on the di1_step_repeat_<i> field + #0 + + + + + di1_gentime_sel_9 + no description available + 29 + 3 + read-write + + + 000 + Counter #9's waveform is attached to counter #1's waveform + #000 + + + 001 + Counter #9's waveform is attached to counter #2's waveform + #001 + + + 010 + Counter #9's waveform is attached to counter #3's waveform + #010 + + + 011 + Counter #9's waveform is attached to counter #4's waveform + #011 + + + 100 + Counter #9's waveform is attached to counter #5's waveform + #100 + + + 101 + Counter #9's waveform is attached to counter #6's waveform + #101 + + + 110 + Counter #9's waveform is attached to counter #7's waveform + #110 + + + 111 + Counter #9's waveform is attached to counter #8's waveform + #111 + + + + + + + DI1_SYNC_AS_GEN + DI1 Sync Assistance Gen Register + 0x48054 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_sync_start + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 1 + read-only + + + di1_vsync_sel + no description available + 13 + 3 + read-write + + + 000 + VSYNC is coming from counter #1 + #000 + + + 001 + VSYNC is coming from counter #2 + #001 + + + 111 + VSYNC is coming from counter #8 + #111 + + + + + RESERVED + no description available + 16 + 12 + read-only + + + di1_sync_start_en + no description available + 28 + 1 + read-write + + + RESERVED + no description available + 29 + 3 + read-write + + + + + DI1_DW_GEN_i + DI1 Data Wave Gen <i> Register + 0x48058 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_pt_0_i + no description available + 0 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + - The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_1_i + no description available + 2 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_2_i + no description available + 4 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_3_i + no description available + 6 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_4_i + no description available + 8 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_5_i + no description available + 10 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_pt_6_i + no description available + 12 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_cst_i + no description available + 14 + 2 + read-write + + + 00 + The waveform is defined according to the settings on DI1_DW_SET0_<i> + #00 + + + 01 + The waveform is defined according to the settings on DI1_DW_SET1_<i> + #01 + + + 10 + The waveform is defined according to the settings on DI1_DW_SET2_<i> + #10 + + + 11 + The waveform is defined according to the settings on DI1_DW_SET3_<i> + #11 + + + + + di1_componnent_size_i + no description available + 16 + 8 + read-write + + + di1_access_size_i + no description available + 24 + 8 + read-write + + + + + DI1_DW_SET0_i + DI1 Data Wave Set 0 <i> Register + 0x48088 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_data_cnt_up0_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di1_data_cnt_down0_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI1_DW_SET1_i + DI1 Data Wave Set 1 <i> Register + 0x480B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_data_cnt_up1_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di1_data_cnt_down1_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI1_DW_SET2_i + DI1 Data Wave Set 2 <i> Register + 0x480E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_data_cnt_up2_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di1_data_cnt_down2_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DI1_DW_SET3_i + DI1 Data Wave Set 3 <i> Register + 0x48118 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_data_cnt_up3_i + no description available + 0 + 9 + read-write + + + RESERVED + no description available + 9 + 7 + read-only + + + di1_data_cnt_down3_i + no description available + 16 + 9 + read-write + + + RESERVED + no description available + 25 + 7 + read-only + + + + + D1_STP_REP_i + DI1 Step Repeat <i> Registers + 0x48148 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_step_repeat_2i_minus_1 + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 4 + read-only + + + di1_step_repeat_2i + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DI1_STP_REP_9 + DI1Step Repeat 9 Registers + 0x48158 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_step_repeat_9 + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + DI1_SER_CONF + DI1 Serial Display Control Register + 0x4815C + 32 + read-write + 0 + 0xFFFFFFFF + + + DI1_WAIT4SERIAL + no description available + 0 + 1 + read-write + + + 1 + The parallel port should wait to the serial port as the pins are shared + #1 + + + 0 + The parallel port should not wait to the serial port as the pins are not shared + #0 + + + + + DI1_SERIAL_CS_POLARITY + no description available + 1 + 1 + read-write + + + 1 + The CS is inverted + #1 + + + 0 + The CS is not inverted + #0 + + + + + DI1_SERIAL_RS_POLARITY + no description available + 2 + 1 + read-write + + + 1 + The RS is inverted + #1 + + + 0 + The RS is not inverted + #0 + + + + + DI1_SERIAL_DATA_POLARITY + no description available + 3 + 1 + read-write + + + 1 + The data is inverted + #1 + + + 0 + The data is not inverted + #0 + + + + + DI1_SER_CLK_POLARITY + no description available + 4 + 1 + read-write + + + 1 + The clock is inverted + #1 + + + 0 + The clock is not inverted + #0 + + + + + DI1_LLA_SER_ACCESS + no description available + 5 + 1 + read-write + + + 1 + ARM platform access is performed via a direct path to the serial display in LLA mode, in this mode only the ARM platform in LLA mode can access the serial port + #1 + + + 0 + ARM platform access to the serial display port is not done directly, hence other source are allowed to access the serial port. The arbitration is done automatically + #0 + + + + + RESERVED + no description available + 6 + 2 + read-only + + + DI1_SERIAL_LATCH + no description available + 8 + 8 + read-write + + + DI1_SERIAL_LLA_PNTR_RS_W_0 + no description available + 16 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI1_SERIAL_LLA_PNTR_RS_W_1 + no description available + 20 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI1_SERIAL_LLA_PNTR_RS_R_0 + no description available + 24 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + DI1_SERIAL_LLA_PNTR_RS_R_1 + no description available + 28 + 4 + read-write + + + 0000 + Waveform set #1 + #0000 + + + 0001 + Waveform set #2 + #0001 + + + 1011 + Waveform set #12 + #1011 + + + 1100 + Reserved + #1100 + + + 1101 + Reserved + #1101 + + + 1100 + Reserved + #1100 + + + + + + + DI1_SSC + DI1 Special Signals Control Register + 0x48160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI1_BYTE_EN_PNTR + no description available + 0 + 3 + read-write + + + 000 + wave form of byte enable as pin_11 + #000 + + + 001 + wave form of byte enable as pin_12 + #001 + + + 111 + wave form of byte enable as suitable CS pin + #111 + + + + + DI1_BYTE_EN_RD_IN + no description available + 3 + 1 + read-write + + + 1 + The write byte enable signals are routed via bits [17:16] of the display's data, The read byte enable signals are routed via bits [19:18 of the display's data + #1 + + + 0 + The byte enable signals are routed via bits [17:16] of the display's data for both read and write + #0 + + + + + DI1_BYTE_EN_POLARITY + no description available + 4 + 1 + read-write + + + 1 + active high. + #1 + + + 0 + active low. + #0 + + + + + DI1_WAIT_ON + no description available + 5 + 1 + read-write + + + 1 + The DC holds the flow as long as WAIT is asserted. + #1 + + + 0 + The DC continues the flow regardless the WAIT signal. + #0 + + + + + RESERVED + no description available + 6 + 10 + read-only + + + DI1_CS_ERM + no description available + 16 + 1 + read-write + + + 1 + The GLUELOGIC is release in case of a synchronous display error. The release will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the GLUELOGIC following a display error detection. + #0 + + + + + DI1_PIN11_ERM + no description available + 17 + 1 + read-write + + + 1 + The PIN11 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN11 pin following a display error detection. + #0 + + + + + DI1_PIN12_ERM + no description available + 18 + 1 + read-write + + + 1 + The PIN12 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN12 pin following a display error detection. + #0 + + + + + DI1_PIN13_ERM + no description available + 19 + 1 + read-write + + + 1 + The PIN13 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN13 pin following a display error detection. + #0 + + + + + DI1_PIN14_ERM + no description available + 20 + 1 + read-write + + + 1 + The PIN14 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN14 pin following a display error detection. + #0 + + + + + DI1_PIN15_ERM + no description available + 21 + 1 + read-write + + + 1 + The PIN15 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN15 pin following a display error detection. + #0 + + + + + DI1_PIN16_ERM + no description available + 22 + 1 + read-write + + + 1 + The PIN16 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN16 pin following a display error detection. + #0 + + + + + DI1_PIN17_ERM + no description available + 23 + 1 + read-write + + + 1 + The PIN17 pin is cleared in case of a synchronous display error. The clear will be done on the next VSYNC. + #1 + + + 0 + Nothing is done to the PIN17 pin following a display error detection. + #0 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DI1_POL + DI1 Polarity Register + 0x48164 + 32 + read-write + 0 + 0xFFFFFFFF + + + di1_drdy_polarity + no description available + 0 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI1_DRDY_DATA_POLARITY + no description available + 7 + 1 + read-write + + + di1_cs0_polarity + no description available + 8 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI1_CS0_DATA_POLARITY + no description available + 15 + 1 + read-write + + + di1_cs1_polarity + no description available + 16 + 7 + read-write + + + 1 + The output pin is active high + #1 + + + 0 + The output pin is active low + #0 + + + + + DI1_CS1_DATA_POLARITY + no description available + 23 + 1 + read-write + + + DI1_CS0_BYTE_EN_POLARITY + no description available + 24 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + DI1_CS1_BYTE_EN_POLARITY + no description available + 25 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + DI1_WAIT_POLARITY + no description available + 26 + 1 + read-write + + + 1 + active high + #1 + + + 0 + active low + #0 + + + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DI1_AW0 + DI1Active Window 0 Register + 0x48168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI1_AW_HSTART + no description available + 0 + 12 + read-write + + + DI1_AW_HCOUNT_SEL + no description available + 12 + 4 + read-write + + + 0000 + disabled + #0000 + + + 0001 + reserved + #0001 + + + 0010 + The counter is counter #1 + #0010 + + + 0011 + The counter is counter #2 + #0011 + + + 0100 + The counter is counter #3 + #0100 + + + 0101 + The counter is counter #4 + #0101 + + + 0110 + The counter is counter #5 + #0110 + + + 1001 + The counter is counter #8 + #1001 + + + + + DI1_AW_HEND + no description available + 16 + 12 + read-write + + + DI1_AW_TRIG_SEL + no description available + 28 + 4 + read-write + + + 000 + disabled + #000 + + + 001 + The trigger is the same trigger that triggers the displays clock. + #001 + + + 010 + The trigger is counter #1 + #010 + + + 011 + The trigger is counter #2 + #011 + + + 100 + The trigger is counter #3 + #100 + + + 101 + The trigger is counter #4 + #101 + + + 110 + The trigger is counter #5 + #110 + + + 111 + The trigger is always on. + #111 + + + + + + + DI1_AW1 + DI1 Active Window 1 Register + 0x4816C + 32 + read-write + 0 + 0xFFFFFFFF + + + DI1_AW_VSTART + no description available + 0 + 12 + read-write + + + DI1_AW_VCOUNT_SEL + no description available + 12 + 4 + read-write + + + 0000 + disabled + #0000 + + + 0001 + reserved + #0001 + + + 0010 + The counter is counter #1 + #0010 + + + 0011 + The counter is counter #2 + #0011 + + + 0100 + The counter is counter #3 + #0100 + + + 0101 + The counter is counter #4 + #0101 + + + 0110 + The counter is counter #5 + #0110 + + + 1001 + The counter is counter #8 + #1001 + + + + + DI1_AW_VEND + no description available + 16 + 12 + read-write + + + RESERVED + no description available + 28 + 4 + read-only + + + + + DI1_SCR_CONF + DI1 Screen Configuration Register + 0x48170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI1_SCREEN_HEIGHT + no description available + 0 + 12 + read-write + + + RESERVED + no description available + 12 + 20 + read-only + + + + + DI1_STAT + DI1 Status Register + 0x48174 + 32 + read-only + 0x5 + 0xFFFFFFFF + + + DI1_READ_FIFO_EMPTY + no description available + 0 + 1 + read-only + + + DI1_READ_FIFO_FULL + no description available + 1 + 1 + read-only + + + DI1_CNTR_FIFO_EMPTY + no description available + 2 + 1 + read-only + + + DI1_CNTR_FIFO_FULL + no description available + 3 + 1 + read-only + + + RESERVED + no description available + 4 + 28 + read-only + + + + + SMFC_MAP + SMFC Mapping Register + 0x50000 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAP_CH0 + no description available + 0 + 3 + read-write + + + 000 + CSI0, ID=0 mapped to DMASMFC channel 0. + #000 + + + 001 + CSI0, ID=1 mapped to DMASMFC channel 0. + #001 + + + 010 + CSI0, ID=2 mapped to DMASMFC channel 0. + #010 + + + 011 + CSI0, ID=3 mapped to DMASMFC channel 0. + #011 + + + 100 + CSI1, ID=0 mapped to DMASMFC channel 0. + #100 + + + 101 + CSI1, ID=1 mapped to DMASMFC channel 0. + #101 + + + 110 + CSI1, ID=2 mapped to DMASMFC channel 0. + #110 + + + 111 + CSI1, ID=3 mapped to DMASMFC channel 0. + #111 + + + + + MAP_CH1 + no description available + 3 + 3 + read-write + + + 000 + CSI0, ID=0 mapped to DMASMFC channel 1. + #000 + + + 001 + CSI0, ID=1 mapped to DMASMFC channel 1. + #001 + + + 010 + CSI0, ID=2 mapped to DMASMFC channel 1. + #010 + + + 011 + CSI0, ID=3 mapped to DMASMFC channel 1. + #011 + + + 100 + CSI1, ID=0 mapped to DMASMFC channel 1. + #100 + + + 101 + CSI1, ID=1 mapped to DMASMFC channel 1. + #101 + + + 110 + CSI1, ID=2 mapped to DMASMFC channel 1. + #110 + + + 111 + CSI1, ID=3 mapped to DMASMFC channel 1. + #111 + + + + + MAP_CH2 + no description available + 6 + 3 + read-write + + + 000 + CSI0, ID=0 mapped to DMASMFC channel 2. + #000 + + + 001 + CSI0, ID=1 mapped to DMASMFC channel 2. + #001 + + + 010 + CSI0, ID=2 mapped to DMASMFC channel 2. + #010 + + + 011 + CSI0, ID=3 mapped to DMASMFC channel 2. + #011 + + + 100 + CSI1, ID=0 mapped to DMASMFC channel 2. + #100 + + + 101 + CSI1, ID=1 mapped to DMASMFC channel 2. + #101 + + + 110 + CSI1, ID=2 mapped to DMASMFC channel 2. + #110 + + + 111 + CSI1, ID=3 mapped to DMASMFC channel 2. + #111 + + + + + MAP_CH3 + no description available + 9 + 3 + read-write + + + 000 + CSI0, ID=0 mapped to DMASMFC channel 3. + #000 + + + 001 + CSI0, ID=1 mapped to DMASMFC channel 3. + #001 + + + 010 + CSI0, ID=2 mapped to DMASMFC channel 3. + #010 + + + 011 + CSI0, ID=3 mapped to DMASMFC channel 3. + #011 + + + 100 + CSI1, ID=0 mapped to DMASMFC channel 3. + #100 + + + 101 + CSI1, ID=1 mapped to DMASMFC channel 3. + #101 + + + 110 + CSI1, ID=2 mapped to DMASMFC channel 3. + #110 + + + 111 + CSI1, ID=3 mapped to DMASMFC channel 3. + #111 + + + + + RESERVED + no description available + 12 + 20 + read-only + + + + + SMFC_WMC + SMFC Watermark Control Register + 0x50004 + 32 + read-write + 0x9A6 + 0xFFFFFFFF + + + WM0_SET + no description available + 0 + 3 + read-write + + + 000 + set watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + set watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + set watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + set watermark level when FIFO is full. + #111 + + + + + WM0_CLR + no description available + 3 + 3 + read-write + + + 000 + clear watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + clear watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + clear watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + clear watermark level when FIFO is full. + #111 + + + + + WM1_SET + no description available + 6 + 3 + read-write + + + 000 + set watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + set watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + set watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + set watermark level when FIFO is full. + #111 + + + + + WM1_CLR + no description available + 9 + 3 + read-write + + + 000 + clear watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + clear watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + clear watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + clear watermark level when FIFO is full. + #111 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + WM2_SET + no description available + 16 + 3 + read-write + + + 000 + set watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + set watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + set watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + set watermark level when FIFO is full. + #111 + + + + + WM2_CLR + no description available + 19 + 3 + read-write + + + 000 + clear watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + clear watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + clear watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + clear watermark level when FIFO is full. + #111 + + + + + WM3_SET + no description available + 22 + 3 + read-write + + + 000 + set watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + set watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + set watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + set watermark level when FIFO is full. + #111 + + + + + WM3_CLR + no description available + 25 + 3 + read-write + + + 000 + clear watermark level when FIFO is full on 1/8 of their size. + #000 + + + 001 + clear watermark level when FIFO is full on 2/8 of their size. + #001 + + + 110 + clear watermark level when FIFO is full on 7/8 of their size. + #110 + + + 111 + clear watermark level when FIFO is full. + #111 + + + + + RESERVED + no description available + 28 + 4 + read-only + + + + + SMFC_BS + SMFC Burst Size Register + 0x50008 + 32 + read-write + 0 + 0xFFFFFFFF + + + BURST0_SIZE + no description available + 0 + 4 + read-write + + + BURST1_SIZE + no description available + 4 + 4 + read-write + + + BURST2_SIZE + no description available + 8 + 4 + read-write + + + BURST3_SIZE + no description available + 12 + 4 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_READ_CH_CONF + DC Read Channel Configuration Register + 0x58000 + 32 + read-write + 0xFFFF0000 + 0xFFFFFFFF + + + RD_CHANNEL_EN + no description available + 0 + 1 + read-write + + + 1 + The Read channel is enabled + #1 + + + 0 + The Read channel is disabled + #0 + + + + + PROG_DI_ID_0 + no description available + 1 + 1 + read-write + + + 1 + DI #1 + #1 + + + 0 + DI #0 + #0 + + + + + PROG_DISP_ID_0 + no description available + 2 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + W_SIZE_0 + no description available + 4 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + CHAN_MASK_DEFAULT_0 + no description available + 6 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + CS_ID_0 + no description available + 8 + 1 + read-write + + + 1 + display #0 is connected to CS1 + #1 + + + 0 + display #0 is connected to CS0 + #0 + + + + + CS_ID_1 + no description available + 9 + 1 + read-write + + + 1 + display #1 is connected to CS1 + #1 + + + 0 + display #1 is connected to CS0 + #0 + + + + + CS_ID_2 + no description available + 10 + 1 + read-write + + + 1 + display #2 is connected to CS1 + #1 + + + 0 + display #2 is connected to CS0 + #0 + + + + + CS_ID_3 + no description available + 11 + 1 + read-write + + + 1 + display #3 is connected to CS1 + #1 + + + 0 + display #3 is connected to CS0 + #0 + + + + + RESERVED + no description available + 12 + 4 + read-only + + + TIME_OUT_VALUE + no description available + 16 + 16 + read-write + + + + + DC_READ_SH_ADDR + DC Read Channel Start Address Register + 0x58004 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_0 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL0_CH_0 + DC Routine Link Register 0 Channel 0 + 0x58008 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NF_PRIORITY_CHAN_0 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NF_START_CHAN_0 + no description available + 8 + 8 + read-write + + + COD_NL_PRIORITY_CHAN_0 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NL_START_CHAN_0 + no description available + 24 + 8 + read-write + + + + + DC_RL1_CH_0 + DC Routine Link Register 1 Channel 0 + 0x5800C + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOF_PRIORITY_CHAN_0 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOF_START_CHAN_0 + no description available + 8 + 8 + read-write + + + COD_NFIELD_PRIORITY_CHAN_0 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NFIELD_START_CHAN_0 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_0 + DC Routine Link Register2 Channel 0 + 0x58010 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOL_PRIORITY_CHAN_0 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOL_START_CHAN_0 + no description available + 8 + 8 + read-write + + + COD_EOFIELD_PRIORITY_CHAN_0 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_EOFIELD_START_CHAN_0 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_0 + DC Routine Link Registe3 Channel 0 + 0x58014 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_0 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_0 + no description available + 8 + 8 + read-write + + + COD_NEW_CHAN_PRIORITY_CHAN_0 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_0 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_0 + DC Routine Link Register 4 Channel 0 + 0x58018 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_0 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_WR_CH_CONF_1 + DC Write Channel 1 Configuration Register + 0x5801C + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_1 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + PROG_DI_ID_1 + no description available + 2 + 1 + read-write + + + 1 + DI #1 + #1 + + + 0 + DI #0 + #0 + + + + + PROG_DISP_ID_1 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + PROG_CHAN_TYP_1 + no description available + 5 + 3 + read-write + + + 000 + Disable + #000 + + + 001 + Reserved + #001 + + + 010 + Reserved + #010 + + + 100 + Normal mode without anti-tearing. For sync display this is the only mode allowed + #100 + + + 101 + Normal mode with anti-tearing + #101 + + + 110 + Reserved + #110 + + + 111 + Additional command channel is added to the flow handled by DC channel #1 + #111 + + + + + CHAN_MASK_DEFAULT_1 + no description available + 8 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + FIELD_MODE_1 + no description available + 9 + 1 + read-write + + + 1 + Field mode + #1 + + + 0 + Frame mode + #0 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + PROG_START_TIME_1 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DC_WR_CH_ADDR_1 + DC Write Channel 1 Address Configuration Register + 0x58020 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_1 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL0_CH_1 + DC Routine Link Register 0 Channel 1 + 0x58024 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NF_PRIORITY_CHAN_1 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NF_START_CHAN_1 + no description available + 8 + 8 + read-write + + + COD_NL_PRIORITY_CHAN_1 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NL_START_CHAN_1 + no description available + 24 + 8 + read-write + + + + + DC_RL1_CH_1 + DC Routine Link Register 1 Channel 1 + 0x58028 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOF_PRIORITY_CHAN_1 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOF_START_CHAN_1 + no description available + 8 + 8 + read-write + + + COD_NFIELD_PRIORITY_CHAN_1 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NFIELD_START_CHAN_1 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_1 + DC Routine Link Register 2 Channel 1 + 0x58030 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOL_PRIORITY_CHAN_1 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOL_START_CHAN_1 + no description available + 8 + 8 + read-write + + + COD_EOFIELD_PRIORITY_CHAN_1 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_EOFIELD_START_CHAN_1 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_1 + DC Routine Link Register 3 Channel 1 + 0x58032 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_1 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_1 + no description available + 8 + 8 + read-write + + + COD_NEW_CHAN_PRIORITY_CHAN_1 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_1 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_1 + DC Routine Link Register 4 Channel 1 + 0x58034 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_1 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_1 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_WR_CH_CONF_2 + DC Write Channel 2 Configuration Register + 0x58038 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_2 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + PROG_DI_ID_2 + no description available + 2 + 1 + read-write + + + 1 + DI #1 + #1 + + + 0 + DI #0 + #0 + + + + + PROG_DISP_ID_2 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + PROG_CHAN_TYP_2 + no description available + 5 + 3 + read-write + + + 000 + Disable + #000 + + + 001 + Reserved + #001 + + + 010 + Reserved + #010 + + + 100 + Normal mode without anti-tearing. For sync display this is the only mode allowed + #100 + + + 101 + Normal mode with anti-tearing + #101 + + + 110 + Reserved + #110 + + + 111 + Additional command channel is added to the flow handled by DC channel #2 + #111 + + + + + CHAN_MASK_DEFAULT_2 + no description available + 8 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + PROG_START_TIME_2 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DC_WR_CH_ADDR_2 + DC Write Channel 2 Address Configuration Register + 0x5803C + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_2 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL0_CH_2 + DC Routine Link Register 0 Channel 2 + 0x58040 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NF_PRIORITY_CHAN_2 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NF_START_CHAN_2 + no description available + 8 + 8 + read-write + + + COD_NL_PRIORITY_CHAN_2 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NL_START_CHAN_2 + no description available + 24 + 8 + read-write + + + + + DC_RL1_CH_2 + DC Routine Link Register 1 Channel 2 + 0x58044 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOF_PRIORITY_CHAN_2 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOF_START_CHAN_2 + no description available + 8 + 8 + read-write + + + COD_NFIELD_PRIORITY_CHAN_2 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NFIELD_START_CHAN_2 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_2 + DC Routine Link Register 2 Channel 2 + 0x58048 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOL_PRIORITY_CHAN_2 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOL_START_CHAN_2 + no description available + 8 + 8 + read-write + + + COD_EOFIELD_PRIORITY_CHAN_2 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_EOFIELD_START_CHAN_2 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_2 + DC Routine Link Register 3 Channel 2 + 0x5804C + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_2 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_2 + no description available + 8 + 8 + read-write + + + COD_NEW_CHAN_PRIORITY_CHAN_2 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_2 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_2 + DC Routine Link Register 4 Channel 2 + 0x58050 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_2 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_2 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_CMD_CH_CONF_3 + DC Command Channel 3 Configuration Register + 0x58054 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_3 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + COD_CMND_START_CHAN_RS0_3 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_CMND_START_CHAN_RS1_3 + no description available + 24 + 8 + read-write + + + + + DC_CMD_CH_CONF_4 + DC Command Channel 4 Configuration Register + 0x58058 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_4 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + RESERVED + no description available + 2 + 6 + read-only + + + COD_CMND_START_CHAN_RS0_4 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_CMND_START_CHAN_RS1_4 + no description available + 24 + 8 + read-write + + + + + DC_WR_CH_CONF_5 + DC Write Channel 5Configuration Register + 0x5805C + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_5 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + PROG_DI_ID_5 + no description available + 2 + 1 + read-write + + + 1 + DI #1 + #1 + + + 0 + DI #0 + #0 + + + + + PROG_DISP_ID_5 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + PROG_CHAN_TYP_5 + no description available + 5 + 3 + read-write + + + 000 + Disable + #000 + + + 001 + Reserved + #001 + + + 010 + Reserved + #010 + + + 100 + Normal mode without anti-tearing. For sync display this is the only mode allowed + #100 + + + 101 + Normal mode with anti-tearing + #101 + + + 110 + Reserved + #110 + + + 111 + Additional command channel is added to the flow handled by DC channel #5 + #111 + + + + + CHAN_MASK_DEFAULT_5 + no description available + 8 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + FIELD_MODE_5 + no description available + 9 + 1 + read-write + + + 1 + Field mode + #1 + + + 0 + Frame mode + #0 + + + + + RESERVED + no description available + 10 + 6 + read-only + + + PROG_START_TIME_5 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DC_WR_CH_ADDR_5 + DC Write Channel 5Address Configuration Register + 0x58060 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_5 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL0_CH_5 + DC Routine Link Register 0 Channel 5 + 0x58064 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NF_PRIORITY_CHAN_5 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NF_START_CHAN_5 + no description available + 8 + 8 + read-write + + + COD_NL_PRIORITY_CHAN_5 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NL_START_CHAN_5 + no description available + 24 + 8 + read-write + + + + + DC_RL1_CH_5 + DC Routine Link Register 1 Channel 5 + 0x58068 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOF_PRIORITY_CHAN_5 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOF_START_CHAN_5 + no description available + 8 + 8 + read-write + + + COD_NFIELD_PRIORITY_CHAN_5 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NFIELD_START_CHAN_5 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_5 + DC Routine Link Register 2 Channel 5 + 0x5806C + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOL_PRIORITY_CHAN_5 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOL_START_CHAN_5 + no description available + 8 + 8 + read-write + + + COD_EOFIELD_PRIORITY_CHAN_5 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_EOFIELD_START_CHAN_5 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_5 + DC Routine Link Register3 Channel 5 + 0x58070 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_5 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_5 + no description available + 8 + 8 + read-write + + + COD_NEW_CHAN_PRIORITY_CHAN_5 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_5 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_5 + DC Routine Link Register 4 Channel 5 + 0x58074 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_5 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_5 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_WR_CH_CONF_6 + DC Write Channel 6 Configuration Register + 0x58078 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_6 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + PROG_DI_ID_6 + no description available + 2 + 1 + read-write + + + 1 + DI #1 + #1 + + + 0 + DI #0 + #0 + + + + + PROG_DISP_ID_6 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + PROG_CHAN_TYP_6 + no description available + 5 + 3 + read-write + + + 000 + Disable + #000 + + + 001 + Reserved + #001 + + + 010 + Reserved + #010 + + + 100 + Normal mode without anti-tearing. For sync display this is the only mode allowed + #100 + + + 101 + Normal mode with anti-tearing + #101 + + + 110 + Reserved + #110 + + + 111 + Additional command channel is added to the flow handled by DC channel #6 + #111 + + + + + CHAN_MASK_DEFAULT_6 + no description available + 8 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + PROG_START_TIME_6 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + DC_WR_CH_ADDR_6 + DC Write Channel 6 Address Configuration Register + 0x5807C + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_6 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL0_CH_6 + DC Routine Link Register 0Channel 6 + 0x58080 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NF_PRIORITY_CHAN_6 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NF_START_CHAN_6 + no description available + 8 + 8 + read-write + + + COD_NL_PRIORITY_CHAN_6 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NL_START_CHAN_6 + no description available + 24 + 8 + read-write + + + + + DC_RL1_CH_6 + DC Routine Link Register 1 Channel 6 + 0x58084 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOF_PRIORITY_CHAN_6 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOF_START_CHAN_6 + no description available + 8 + 8 + read-write + + + COD_NFIELD_PRIORITY_CHAN_6 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NFIELD_START_CHAN_6 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_6 + DC Routine Link Register 2 Channel 6 + 0x58088 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_EOL_PRIORITY_CHAN_6 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_EOL_START_CHAN_6 + no description available + 8 + 8 + read-write + + + COD_EOFIELD_PRIORITY_CHAN_6 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_EOFIELD_START_CHAN_6 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_6 + DC Routine Link Register 3 Channel 6 + 0x5808C + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_6 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_6 + no description available + 8 + 8 + read-write + + + COD_NEW_CHAN_PRIORITY_CHAN_6 + no description available + 16 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 20 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_6 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_6 + DC Routine Link Register 4 Channel 6 + 0x58090 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_6 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_6 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DC_WR_CH_CONF1_8 + DC Write Channel 8 Configuration 1Register + 0x58094 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_8 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + CHAN_MASK_DEFAULT_8 + no description available + 2 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + MCU_DISP_ID_8 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + DC_WR_CH_CONF2_8 + DC Write Channel 8 Configuration 2 Register + 0x58098 + 32 + read-write + 0 + 0xFFFFFFFF + + + NEW_ADDR_SPACE_SA_8 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL1_CH_8 + DC Routine Link Register 1 Channel 8 + 0x5809C + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_8 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_W_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_W_8_1 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_8 + DC Routine Link Register 2 Channel 8 + 0x580A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_CHAN_PRIORITY_CHAN_8 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_W_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_W_8_1 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_8 + DC Routine Link Register 3 Channel 8 + 0x580A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_8 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_W_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_W_8_1 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_8 + DC Routine Link Register 4 Channel 8 + 0x580A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_R_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_R_8_1 + no description available + 24 + 8 + read-write + + + + + DC_RL5_CH_8 + DC Routine Link Register 5 Channel 8 + 0x580AC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_R_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_R_8_1 + no description available + 24 + 8 + read-write + + + + + DC_RL6_CH_8 + DC Routine Link Register 6 Channel 8 + 0x580B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_R_8_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_R_8_1 + no description available + 24 + 8 + read-write + + + + + DC_WR_CH_CONF1_9 + DC Write Channel 9 Configuration 1Register + 0x580B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + W_SIZE_9 + no description available + 0 + 2 + read-write + + + 00 + 8 bits are used - a 32 bit words includes 4X8bit valid words. + #00 + + + 01 + 16 LSB bits - a 32 bit words includes 2 X16bit valid words. + #01 + + + 10 + 24 MSB bits are used (RGB) - 8 LSB bits are ignored by the DC + #10 + + + 11 + 32 bits are used + #11 + + + + + CHAN_MASK_DEFAULT_9 + no description available + 2 + 1 + read-write + + + 1 + All the events are used - no mask + #1 + + + 0 + Only the highest priority event is used, the rest are masked + #0 + + + + + MCU_DISP_ID_9 + no description available + 3 + 2 + read-write + + + 00 + display #0 + #00 + + + 01 + display #1 + #01 + + + 10 + display #2 + #10 + + + 11 + display #3 + #11 + + + + + RESERVED + no description available + 5 + 27 + read-only + + + + + DC_WR_CH_CONF2_9 + DC Write Channel 9Configuration 2Register + 0x580B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + NEW_ADDR_SPACE_SA_9 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_RL1_CH_9 + DC Routine Link Register 1 Channel 9 + 0x580BC + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_ADDR_PRIORITY_CHAN_9 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_ADDR_START_CHAN_W_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_W_9_1 + no description available + 24 + 8 + read-write + + + + + DC_RL2_CH_9 + DC Routine Link Register 2 Channel 9 + 0x580C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_CHAN_PRIORITY_CHAN_9 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_CHAN_START_CHAN_W_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_W_9_1 + no description available + 24 + 8 + read-write + + + + + DC_RL3_CH_9 + DC Routine Link Register 3Channel 9 + 0x580C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + COD_NEW_DATA_PRIORITY_CHAN_9 + no description available + 0 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 4 + 4 + read-only + + + COD_NEW_DATA_START_CHAN_W_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_W_9_1 + no description available + 24 + 8 + read-write + + + + + DC_RL4_CH_9 + DC Routine Link Register 4 Channel 9 + 0x580C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_R_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_ADDR_START_CHAN_R_9_1 + no description available + 24 + 8 + read-write + + + + + DC_RL5_CH_9 + DC Routine Link Register 5 Channel 9 + 0x580CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_R_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_CHAN_START_CHAN_R_9_1 + no description available + 24 + 8 + read-write + + + + + DC_RL6_CH_9 + DC Routine Link Register 6 Channel 9 + 0x580D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_R_9_0 + no description available + 8 + 8 + read-write + + + RESERVED + no description available + 16 + 8 + read-only + + + COD_NEW_DATA_START_CHAN_R_9_1 + no description available + 24 + 8 + read-write + + + + + DC_GEN + DC General Register + 0x580D4 + 32 + read-write + 0x60 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + SYNC_1_6 + no description available + 1 + 2 + read-write + + + 00 + Channel 1 of the DC handles async flow + #00 + + + 01 + Illegal + #01 + + + 10 + Channel 1 of the DC handles sync flow + #10 + + + 11 + illegal + #11 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + MASK_EN + no description available + 4 + 1 + read-write + + + 1 + mask channel is enabled + #1 + + + 0 + mask channel is disabled + #0 + + + + + MASK4CHAN_5 + no description available + 5 + 1 + read-write + + + 1 + mask channel is associated to the sync flow via DP + #1 + + + 0 + mask channel is associated to the sync flow via DC (without DP) + #0 + + + + + SYNC_PRIORITY_5 + no description available + 6 + 1 + read-write + + + 1 + high priority + #1 + + + 0 + low Priority + #0 + + + + + SYNC_PRIORITY_1 + no description available + 7 + 1 + read-write + + + 1 + high Priority + #1 + + + 0 + low Priority + #0 + + + + + DC_CH5_TYPE + no description available + 8 + 1 + read-write + + + 1 + Enable the asynchronous interface via channel 5 + #1 + + + 0 + normal mode, synchronous flow via channel 5 + #0 + + + + + RESERVED + no description available + 9 + 7 + read-only + + + DC_BKDIV + no description available + 16 + 8 + read-write + + + DC_BK_EN + no description available + 24 + 1 + read-write + + + 1 + blinking is enabled + #1 + + + 0 + blinking is disabled + #0 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DC_DISP_CONF1_0 + DC Display Configuration 1 Register 0 + 0x580D8 + 32 + read-write + 0x42 + 0xFFFFFFFF + + + DISP_TYP_0 + no description available + 0 + 2 + read-write + + + 00 + Serial accesses display + #00 + + + 01 + Reserved + #01 + + + 10 + parallel display, without byte_enable support + #10 + + + 11 + parallel display, with byte_enable support + #11 + + + + + ADDR_INCREMENT_0 + no description available + 2 + 2 + read-write + + + 00 + Increment the address by 1 + #00 + + + 01 + Increment the address by 2 + #01 + + + 10 + Increment the address by 3 + #10 + + + 11 + Increment the address by 4 + #11 + + + + + ADDR_BE_L_INC_0 + no description available + 4 + 2 + read-write + + + 00 + No increment + #00 + + + 01 + Increment by 1 + #01 + + + 10 + Increment by 2 + #10 + + + 11 + Increment by 3 + #11 + + + + + MCU_ACC_LB_MASK_0 + no description available + 6 + 1 + read-write + + + 1 + The 2 addresses are fully compared + #1 + + + 0 + The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored + #0 + + + + + DISP_RD_VALUE_PTR_0 + no description available + 7 + 1 + read-write + + + 1 + DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 0 + #1 + + + 0 + DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 0 + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DC_DISP_CONF1_1 + DC Display Configuration 1 Register 1 + 0x580DC + 32 + read-write + 0x42 + 0xFFFFFFFF + + + DISP_TYP_1 + no description available + 0 + 2 + read-write + + + 00 + Serial accesses display + #00 + + + 01 + Reserved + #01 + + + 10 + parallel display, without byte_enable support + #10 + + + 11 + parallel display, with byte_enable support + #11 + + + + + ADDR_INCREMENT_1 + no description available + 2 + 2 + read-write + + + 00 + Increment the address by 1 + #00 + + + 01 + Increment the address by 2 + #01 + + + 10 + Increment the address by 3 + #10 + + + 11 + Increment the address by 4 + #11 + + + + + ADDR_BE_L_INC_1 + no description available + 4 + 2 + read-write + + + 00 + No increment + #00 + + + 01 + Increment by 1 + #01 + + + 10 + Increment by 2 + #10 + + + 11 + Increment by 3 + #11 + + + + + MCU_ACC_LB_MASK_1 + no description available + 6 + 1 + read-write + + + 1 + The 2 addresses are fully compared + #1 + + + 0 + The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored + #0 + + + + + DISP_RD_VALUE_PTR_1 + no description available + 7 + 1 + read-write + + + 1 + DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 1 + #1 + + + 0 + DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 1 + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DC_DISP_CONF1_2 + DC Display Configuration 1 Register 2 + 0x580E0 + 32 + read-write + 0x42 + 0xFFFFFFFF + + + DISP_TYP_2 + no description available + 0 + 2 + read-write + + + 00 + Serial accesses display + #00 + + + 01 + Reserved + #01 + + + 10 + parallel display, without byte_enable support + #10 + + + 11 + parallel display, with byte_enable support + #11 + + + + + ADDR_INCREMENT_2 + no description available + 2 + 2 + read-write + + + 00 + Increment the address by 1 + #00 + + + 01 + Increment the address by 2 + #01 + + + 10 + Increment the address by 3 + #10 + + + 11 + Increment the address by 4 + #11 + + + + + ADDR_BE_L_INC_2 + no description available + 4 + 2 + read-write + + + 00 + No increment + #00 + + + 01 + Increment by 1 + #01 + + + 10 + Increment by 2 + #10 + + + 11 + Increment by 3 + #11 + + + + + MCU_ACC_LB_MASK_2 + no description available + 6 + 1 + read-write + + + 1 + The 2 addresses are fully compared + #1 + + + 0 + The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored + #0 + + + + + DISP_RD_VALUE_PTR_2 + no description available + 7 + 1 + read-write + + + 1 + DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 2 + #1 + + + 0 + DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 2 + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DC_DISP_CONF1_3 + DC Display Configuration 1 Register 3 + 0x580E4 + 32 + read-write + 0x42 + 0xFFFFFFFF + + + DISP_TYP_3 + no description available + 0 + 2 + read-write + + + 00 + Serial accesses display + #00 + + + 01 + Reserved + #01 + + + 10 + parallel display, without byte_enable support + #10 + + + 11 + parallel display, with byte_enable support + #11 + + + + + ADDR_INCREMENT_3 + no description available + 2 + 2 + read-write + + + 00 + Increment the address by 1 + #00 + + + 01 + Increment the address by 2 + #01 + + + 10 + Increment the address by 3 + #10 + + + 11 + Increment the address by 4 + #11 + + + + + ADDR_BE_L_INC_3 + no description available + 4 + 2 + read-write + + + 00 + No increment + #00 + + + 01 + Increment by 1 + #01 + + + 10 + Increment by 2 + #10 + + + 11 + Increment by 3 + #11 + + + + + MCU_ACC_LB_MASK_3 + no description available + 6 + 1 + read-write + + + 1 + The 2 addresses are fully compared + #1 + + + 0 + The 2 addresses are compared, but the ADDR[0] bit of the new address is ignored + #0 + + + + + DISP_RD_VALUE_PTR_3 + no description available + 7 + 1 + read-write + + + 1 + DI_READ_DATA_ACK_VALUE_1 & DI_READ_DATA_MASK_1 are used for display 3 + #1 + + + 0 + DI_READ_DATA_ACK_VALUE_0 & DI_READ_DATA_MASK_0 are used for display 3 + #0 + + + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DC_DISP_CONF2_0 + DC Display Configuration 2 Register 0 + 0x580E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SL_0 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_DISP_CONF2_1 + DC Display Configuration 2 Register 1 + 0x580EC + 32 + read-write + 0 + 0xFFFFFFFF + + + SL_1 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_DISP_CONF2_2 + DC Display Configuration 2 Register 2 + 0x580F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SL_2 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_DISP_CONF2_3 + DC Display Configuration 2 Register 3 + 0x580F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SL_3 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_DI0_CONF_1 + DC DI0Configuration Register 1 + 0x580F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI_READ_DATA_MASK_0 + no description available + 0 + 32 + read-write + + + + + DC_DI0_CONF_2 + DC DI0Configuration Register 2 + 0x580FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DI_READ_DATA_ACK_VALUE_0 + no description available + 0 + 32 + read-write + + + + + DC_DI1_CONF_1 + DC DI1Configuration Register 1 + 0x58100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI_READ_DATA_MASK_1 + no description available + 0 + 32 + read-write + + + + + DC_DI1_CONF_2 + DC DI1Configuration Register 2 + 0x58104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DI_READ_DATA_ACK_VALUE_1 + no description available + 0 + 32 + read-write + + + + + DC_MAP_CONF_0 + DC Mapping Configuration Register 0 + 0x58108 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_0 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_0 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_0 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_1 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_1 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_1 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_1 + DC Mapping Configuration Register 1 + 0x5810C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_2 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_2 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_2 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_3 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_3 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_3 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_2 + DC Mapping Configuration Register 2 + 0x58110 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_4 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_4 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_4 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_5 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_5 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_5 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_3 + DC Mapping Configuration Register 3 + 0x58114 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_6 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_6 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_6 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_7 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_7 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_7 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_4 + DC Mapping Configuration Register 4 + 0x58118 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_8 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_8 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_8 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_9 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_1 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_9 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_5 + DC Mapping Configuration Register 5 + 0x5811C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_10 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_10 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_10 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_11 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_11 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_11 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_6 + DC Mapping Configuration Register 6 + 0x58120 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_12 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_12 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_12 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_13 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_13 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_13 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_7 + DC Mapping Configuration Register 7 + 0x58124 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_14 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_14 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_14 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_15 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_15 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_15 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_8 + DC Mapping Configuration Register 8 + 0x58128 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_16 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_16 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_16 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_17 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_17 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_17 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_9 + DC Mapping Configuration Register 9 + 0x5812C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_18 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_18 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_18 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_19 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_19 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_19 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_10 + DC Mapping Configuration Register 10 + 0x58130 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_20 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_20 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_20 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_21 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_21 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_21 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_11 + DC Mapping Configuration Register 11 + 0x58134 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_22 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_22 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_22 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_23 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_23 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_23 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_12 + DC Mapping Configuration Register 12 + 0x58138 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_24 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_24 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_24 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_25 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_25 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_25 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_13 + DC Mapping Configuration Register 13 + 0x5813C + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE0_26 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_26 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_26 + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_27 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_27 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_27 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_14 + DC Mapping Configuration Register 14 + 0x58140 + 32 + read-write + 0 + 0xFFFFFFFF + + + MAPPING_PNTR_BYTE2_28 + no description available + 0 + 5 + read-write + + + MAPPING_PNTR_BYTE1_28 + no description available + 5 + 5 + read-write + + + MAPPING_PNTR_BYTE2_28f + no description available + 10 + 5 + read-write + + + RESERVED + no description available + 15 + 1 + read-only + + + MAPPING_PNTR_BYTE0_29 + no description available + 16 + 5 + read-write + + + MAPPING_PNTR_BYTE1_29 + no description available + 21 + 5 + read-write + + + MAPPING_PNTR_BYTE2_29 + no description available + 26 + 5 + read-write + + + RESERVED + no description available + 31 + 1 + read-only + + + + + DC_MAP_CONF_15 + DC Mapping Configuration Register 15 + 0x58144 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_0 + no description available + 0 + 8 + read-write + + + MD_OFFSET_0 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_1 + no description available + 16 + 8 + read-write + + + MD_OFFSET_1 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_16 + DC Mapping Configuration Register 16 + 0x58148 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_0 + no description available + 0 + 8 + read-write + + + MD_OFFSET_2 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_3 + no description available + 16 + 8 + read-write + + + MD_OFFSET_3 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_17 + DC Mapping Configuration Register 17 + 0x5814C + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_4 + no description available + 0 + 8 + read-write + + + MD_OFFSET_4 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_5 + no description available + 16 + 8 + read-write + + + MD_OFFSET_5 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_18 + DC Mapping Configuration Register 18 + 0x58150 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_6 + no description available + 0 + 8 + read-write + + + MD_OFFSET_6 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_7 + no description available + 16 + 8 + read-write + + + MD_OFFSET_7 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_19 + DC Mapping Configuration Register 19 + 0x58154 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_8 + no description available + 0 + 8 + read-write + + + MD_OFFSET_8 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_9 + no description available + 16 + 8 + read-write + + + MD_OFFSET_9 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_20 + DC Mapping Configuration Register 20 + 0x58158 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_10 + no description available + 0 + 8 + read-write + + + MD_OFFSET_10 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_11 + no description available + 16 + 8 + read-write + + + MD_OFFSET_11 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_21 + DC Mapping Configuration Register 21 + 0x5815C + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_12 + no description available + 0 + 8 + read-write + + + MD_OFFSET_12 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_13 + no description available + 16 + 8 + read-write + + + MD_OFFSET_13 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_22 + DC Mapping Configuration Register 22 + 0x58160 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_14 + no description available + 0 + 8 + read-write + + + MD_OFFSET_14 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_15 + no description available + 16 + 8 + read-write + + + MD_OFFSET_15 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_23 + DC Mapping Configuration Register 23 + 0x58164 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_16 + no description available + 0 + 8 + read-write + + + MD_OFFSET_16 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_17 + no description available + 16 + 8 + read-write + + + MD_OFFSET_17 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_24 + DC Mapping Configuration Register 24 + 0x58168 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_18 + no description available + 0 + 8 + read-write + + + MD_OFFSET_18 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_19 + no description available + 16 + 8 + read-write + + + MD_OFFSET_19 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_25 + DC Mapping Configuration Register 25 + 0x5816C + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_20 + no description available + 0 + 8 + read-write + + + MD_OFFSET_20 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_21 + no description available + 16 + 8 + read-write + + + MD_OFFSET_21 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_MAP_CONF_26 + DC Mapping Configuration Register 26 + 0x58170 + 32 + read-write + 0 + 0xFFFFFFFF + + + MD_MASK_22 + no description available + 0 + 8 + read-write + + + MD_OFFSET_22 + no description available + 8 + 5 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + MD_MASK_23 + no description available + 16 + 8 + read-write + + + MD_OFFSET_23 + no description available + 24 + 5 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE0_0 + DC User General Data Event 0 Register 0 + 0x58174 + 32 + read-write + 0 + 0xFFFFFFFF + + + ID_CODED_0 + no description available + 0 + 3 + read-write + + + 000 + DC channel_0 + #000 + + + 001 + DC channel_1 + #001 + + + 010 + DC channel_2 + #010 + + + 011 + DC channel_5 (DP_SYNC) + #011 + + + 100 + DC channel_6 (DP ASYNC) + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved. + #110 + + + 111 + Reserved. + #111 + + + + + COD_EV_PRIORITY_0 + no description available + 3 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + COD_EV_START_0 + no description available + 8 + 8 + read-write + + + COD_ODD_START_0 + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + ODD_EN_0 + no description available + 25 + 1 + read-write + + + 1 + ODD_MODE is enabled + #1 + + + 0 + ODD_MODE is disabled + #0 + + + + + AUTORESTART_0 + no description available + 26 + 1 + read-write + + + 0 + disable + #0 + + + 1 + User's general event #0's counter is automatically restarted. + #1 + + + + + NF_NL_0 + no description available + 27 + 2 + read-write + + + 00 + New Line + #00 + + + 01 + New Frame + #01 + + + 10 + New Field + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE0_1 + DC User General Data Event 0 Register 1 + 0x58178 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_0 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE0_2 + DC User General Data Event 0 Register2 + 0x5817C + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET_DT_0 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE0_3 + DC User General Data Event 0 Register 3 + 0x58180 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_REPEAT_0 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE1_0 + DC User General Data Event 1Register0 + 0x58184 + 32 + read-write + 0 + 0xFFFFFFFF + + + ID_CODED_1 + no description available + 0 + 3 + read-write + + + 000 + DC channel_0 + #000 + + + 001 + DC channel_1 + #001 + + + 010 + DC channel_2 + #010 + + + 011 + DC channel_5 (DP_SYNC) + #011 + + + 100 + DC channel_6 (DP ASYNC) + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + COD_EV_PRIORITY_1 + no description available + 3 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + COD_EV_START_1 + no description available + 8 + 8 + read-write + + + COD_ODD_START_1 + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + ODD_EN_1 + no description available + 25 + 1 + read-write + + + 1 + ODD_MODE is enabled + #1 + + + 0 + ODD_MODE is disabled + #0 + + + + + AUTORESTART_1 + no description available + 26 + 1 + read-write + + + 0 + disable + #0 + + + 1 + User's general event #1's counter is automatically restarted. + #1 + + + + + NF_NL_1 + no description available + 27 + 2 + read-write + + + 00 + New Line + #00 + + + 01 + New Frame + #01 + + + 10 + New Field + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE1_1 + DC User General Data Event 1 Register 1 + 0x58188 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_1 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE1_2 + DC User General Data Event 1Register 2 + 0x5818C + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET_DT_1 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE1_3 + DC User General Data Event 1Register 3 + 0x58190 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_REPEAT_1 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE2_0 + DC User General Data Event 2 Register 0 + 0x58194 + 32 + read-write + 0 + 0xFFFFFFFF + + + ID_CODED_2 + no description available + 0 + 3 + read-write + + + 000 + DC channel_0 + #000 + + + 001 + DC channel_1 + #001 + + + 010 + DC channel_2 + #010 + + + 011 + DC channel_5 (DP_SYNC) + #011 + + + 100 + DC channel_6 (DP ASYNC) + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved + #111 + + + + + COD_EV_PRIORITY_2 + no description available + 3 + 4 + read-write + + + 0000 + disable + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + COD_EV_START_2 + no description available + 8 + 8 + read-write + + + COD_ODD_START_2 + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + ODD_EN_2 + no description available + 25 + 1 + read-write + + + 1 + ODD_MODE is enabled + #1 + + + 0 + ODD_MODE is disabled + #0 + + + + + AUTORESTART_2 + no description available + 26 + 1 + read-write + + + 0 + disable + #0 + + + 1 + User's general event #2's counter is automatically restarted. + #1 + + + + + NF_NL_2 + no description available + 27 + 2 + read-write + + + 00 + New Line + #00 + + + 01 + New Frame + #01 + + + 10 + New Field + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE2_1 + DC User General Data Event 2 Register 1 + 0x58198 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_2 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE2_2 + DC User General Data Event 2Register 2 + 0x5819C + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET_DT_2 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE2_3 + DC User General Data Event 2Register 3 + 0x581A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_REPEAT_2 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE3_0 + DC User General Data Event 3Register 0 + 0x581A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ID_CODED_3 + no description available + 0 + 3 + read-write + + + 000 + DC channel_0 + #000 + + + 001 + DC channel_1 + #001 + + + 010 + DC channel_2 + #010 + + + 011 + DC channel_5 (DP_SYNC) + #011 + + + 100 + DC channel_6 (DP ASYNC) + #100 + + + 101 + Reserved + #101 + + + 110 + Reserved + #110 + + + 111 + Reserved. + #111 + + + + + COD_EV_PRIORITY_3 + no description available + 3 + 4 + read-write + + + 0000 + disableThe priority between the events should be set to a unique value. i.e. two events must not have the same priority (except 0000 - disable) + #0000 + + + 0001 + Priority #1 (lowest) + #0001 + + + 0010 + Priority #2 + #0010 + + + 1101 + Priority #13 (highest) + #1101 + + + 1110 + Reserved + #1110 + + + 1111 + Reserved + #1111 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + COD_EV_START_3 + no description available + 8 + 8 + read-write + + + COD_ODD_START_3 + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + ODD_EN_3 + no description available + 25 + 1 + read-write + + + 1 + ODD_MODE is enabled + #1 + + + 0 + ODD_MODE is disabled + #0 + + + + + AUTORESTART_3 + no description available + 26 + 1 + read-write + + + 0 + disable + #0 + + + 1 + User's general event #3's counter is automatically restarted. + #1 + + + + + NF_NL_3 + no description available + 27 + 2 + read-write + + + 00 + New Line + #00 + + + 01 + New Frame + #01 + + + 10 + New Field + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE3_1 + DC User General Data Event 3Register 1 + 0x581A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_3 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE3_2 + DC User General Data Event 3Register 2 + 0x581AC + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET_DT_3 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_UGDE3_3 + DC User General Data Event 3Register 2 + 0x581B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP_REPEAT_3 + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_LLA0 + DC Low Level Access Control Register 0 + 0x581B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCU_RS_0_0 + no description available + 0 + 8 + read-write + + + MCU_RS_1_0 + no description available + 8 + 8 + read-write + + + MCU_RS_2_0 + no description available + 16 + 8 + read-write + + + MCU_RS_3_0 + no description available + 24 + 8 + read-write + + + + + DC_LLA1 + DC Low Level Access Control Register 1 + 0x581B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCU_RS_0_1 + no description available + 0 + 8 + read-write + + + MCU_RS_1_1 + no description available + 8 + 8 + read-write + + + MCU_RS_2_1 + no description available + 16 + 8 + read-write + + + MCU_RS_3_1 + no description available + 24 + 8 + read-write + + + + + DC_R_LLA0 + DC Read Low Level Read Access Control Register 0 + 0x581BC + 32 + read-write + 0 + 0xFFFFFFFF + + + MCU_RS_R_0_0 + no description available + 0 + 8 + read-write + + + MCU_RS_R_1_0 + no description available + 8 + 8 + read-write + + + MCU_RS_2_0 + no description available + 16 + 8 + read-write + + + MCU_RS_3_0 + no description available + 24 + 8 + read-write + + + + + DC_R_LLA1 + DC Read Low Level Read Access Control Register1 + 0x581C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MCU_RS_R_0_1 + no description available + 0 + 8 + read-write + + + MCU_RS_R_1_1 + no description available + 8 + 8 + read-write + + + MCU_RS_R_2_1 + no description available + 16 + 8 + read-write + + + MCU_RS_R_3_1 + no description available + 24 + 8 + read-write + + + + + DC_WR_CH_ADDR_5_ALT + DC Write Channel 5 Configuration Register + 0x581C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ST_ADDR_5_ALT + no description available + 0 + 29 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DC_STAT + DC Status Register + 0x581C8 + 32 + read-only + 0xAA + 0xFFFFFFFF + + + DC_TRIPLE_BUF_CNT_FULL_0 + no description available + 0 + 1 + read-only + + + DC_TRIPLE_BUF_CNT_EMPTY_0 + no description available + 1 + 1 + read-only + + + DC_TRIPLE_BUF_DATA_FULL_0 + no description available + 2 + 1 + read-only + + + DC_TRIPLE_BUF_DATA_EMPTY_0 + no description available + 3 + 1 + read-only + + + DC_TRIPLE_BUF_CNT_FULL_1 + no description available + 4 + 1 + read-only + + + DC_TRIPLE_BUF_CNT_EMPTY_1 + no description available + 5 + 1 + read-only + + + DC_TRIPLE_BUF_DATA_FULL_1 + no description available + 6 + 1 + read-only + + + DC_TRIPLE_BUF_DATA_EMPTY_1 + no description available + 7 + 1 + read-only + + + RESERVED + no description available + 8 + 24 + read-only + + + + + DMFC_RD_CHAN + DMFC Read Channel Register + 0x60000 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 6 + read-only + + + dmfc_burst_size_0 + no description available + 6 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, going to the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + RESERVED + no description available + 8 + 9 + read-only + + + dmfc_wm_en_0 + no description available + 17 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_0 + no description available + 18 + 3 + read-write + + + dmfc_wm_clr_0 + no description available + 21 + 3 + read-write + + + dmfc_ppw_c + no description available + 24 + 2 + read-write + + + 00 + 8 bit per pixel + #00 + + + 01 + 16 bit per pixel + #01 + + + 10 + 24 (rgb) bit per pixel or 32 bit per pixel + #10 + + + 11 + Reserved + #11 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + DMFC_WR_CHAN + DMFC Write Channel Register + 0x60004 + 32 + read-write + 0 + 0xFFFFFFFF + + + dmfc_st_addr_1 + no description available + 0 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_1 + no description available + 3 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_1 + no description available + 6 + 2 + read-write + + + 00 + 32 words of 1hbit + #00 + + + + + dmfc_st_addr_2 + no description available + 8 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_2 + no description available + 11 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_2 + no description available + 14 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_1c + no description available + 16 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_1c + no description available + 19 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_1c + no description available + 22 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_2c + no description available + 24 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_2c + no description available + 27 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_2c + no description available + 30 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + + + DMFC_WR_CHAN_DEF + DMFC Write Channel Definition Register + 0x60008 + 32 + read-write + 0x20202020 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + dmfc_wm_en_1 + no description available + 1 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_1 + no description available + 2 + 3 + read-write + + + dmfc_wm_clr_1 + no description available + 5 + 3 + read-write + + + RESERVED + no description available + 8 + 1 + read-only + + + dmfc_wm_en_2 + no description available + 9 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_2 + no description available + 10 + 3 + read-write + + + dmfc_wm_clr_2 + no description available + 13 + 3 + read-write + + + RESERVED + no description available + 16 + 1 + read-only + + + dmfc_wm_en_1c + no description available + 17 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_1c + no description available + 18 + 3 + read-write + + + dmfc_wm_clr_1c + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + dmfc_wm_en_2c + no description available + 25 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_2c + no description available + 26 + 3 + read-write + + + dmfc_wm_clr_2c + no description available + 29 + 3 + read-write + + + + + DMFC_DP_CHAN + DMFC Display Processor Channel Register + 0x6000C + 32 + read-write + 0 + 0xFFFFFFFF + + + dmfc_st_addr_5b + no description available + 0 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_5b + no description available + 3 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_5b + no description available + 6 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_5f + no description available + 8 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_5f + no description available + 11 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_5f + no description available + 14 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_6b + no description available + 16 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_6b + no description available + 19 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_6b + no description available + 22 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_6f + no description available + 24 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_6f + no description available + 27 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_6f + no description available + 30 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + + + DMFC_DP_CHAN_DEF + DMFC Display Processor Channel Definition Register + 0x60010 + 32 + read-write + 0x20202020 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + dmfc_wm_en_5b + no description available + 1 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_5b + no description available + 2 + 3 + read-write + + + dmfc_wm_clr_5b + no description available + 5 + 3 + read-write + + + RESERVED + no description available + 8 + 1 + read-only + + + dmfc_wm_en_5f + no description available + 9 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_5f + no description available + 10 + 3 + read-write + + + dmfc_wm_clr_5f + no description available + 13 + 3 + read-write + + + RESERVED + no description available + 16 + 1 + read-only + + + dmfc_wm_en_6b + no description available + 17 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_6b + no description available + 18 + 3 + read-write + + + dmfc_wm_clr_6b + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + dmfc_wm_en_6f + no description available + 25 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_6f + no description available + 26 + 3 + read-write + + + dmfc_wm_clr_6f + no description available + 29 + 3 + read-write + + + + + DMFC_GENERAL_1 + DMFC General 1 Register + 0x60014 + 32 + read-write + 0x3 + 0xFFFFFFFF + + + dmfc_dcdp_sync_pr + no description available + 0 + 2 + read-write + + + 00 + Forbidden - should not be used. + #00 + + + 01 + DC has higher priority over DP + #01 + + + 10 + DP has higher priority over DC + #10 + + + 11 + Round Robin + #11 + + + + + RESERVED + no description available + 2 + 3 + read-only + + + dmfc_burst_size_9 + no description available + 5 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + RESERVED + no description available + 7 + 1 + read-only + + + RESERVED + no description available + 8 + 1 + read-only + + + dmfc_wm_en_9 + no description available + 9 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_9 + no description available + 10 + 3 + read-write + + + dmfc_wm_clr_9 + no description available + 13 + 3 + read-write + + + WAIT4EOT_1 + no description available + 16 + 1 + read-write + + + 1 + FIFO #1 is in wait4eot mode + #1 + + + 0 + FIFO #1 is in normal mode + #0 + + + + + WAIT4EOT_2 + no description available + 17 + 1 + read-write + + + 1 + FIFO #2 is in wait4eot mode + #1 + + + 0 + FIFO #2 is in normal mode + #0 + + + + + WAIT4EOT_3 + no description available + 18 + 1 + read-write + + + 1 + FIFO #3 is in wait4eot mode + #1 + + + 0 + FIFO #3 is in normal mode + #0 + + + + + WAIT4EOT_4 + no description available + 19 + 1 + read-write + + + 1 + FIFO #4 is in wait4eot mode + #1 + + + 0 + FIFO #4 is in normal mode + #0 + + + + + WAIT4EOT_5B + no description available + 20 + 1 + read-write + + + 1 + FIFO #5B is in wait4eot mode + #1 + + + 0 + FIFO #5B is in normal mode + #0 + + + + + WAIT4EOT_5F + no description available + 21 + 1 + read-write + + + 1 + FIFO #5F is in wait4eot mode + #1 + + + 0 + FIFO #5F is in normal mode + #0 + + + + + WAIT4EOT_6B + no description available + 22 + 1 + read-write + + + 1 + FIFO #6B is in wait4eot mode + #1 + + + 0 + FIFO #6B is in normal mode + #0 + + + + + WAIT4EOT_6F + no description available + 23 + 1 + read-write + + + 1 + FIFO #6F is in wait4eot mode + #1 + + + 0 + FIFO #6F is in normal mode + #0 + + + + + WAIT4EOT_9 + no description available + 24 + 1 + read-write + + + 1 + FIFO #9 is in wait4eot mode + #1 + + + 0 + FIFO #9 is in normal mode + #0 + + + + + RESERVED + no description available + 25 + 7 + read-only + + + + + DMFC_GENERAL_2 + DMFC General 2 Register + 0x60018 + 32 + read-write + 0 + 0xFFFFFFFF + + + dmfc_frame_width_rd + no description available + 0 + 13 + read-write + + + RESERVED + no description available + 13 + 3 + read-only + + + dmfc_frame_height_rd + no description available + 16 + 13 + read-write + + + RESERVED + no description available + 29 + 3 + read-only + + + + + DMFC_IC_CTRL + DMFC IC Interface Control Register + 0x6001C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + dmfc_ic_in_port + no description available + 0 + 3 + read-write + + + 000 + CH28 + #000 + + + 001 + CH41 + #001 + + + 010 + Reserved, IC channel is disabled + #010 + + + 011 + Reserved, IC channel is disabled + #011 + + + 100 + CH23 + #100 + + + 101 + CH27 + #101 + + + 110 + CH24 + #110 + + + 111 + CH29 + #111 + + + + + RESERVED + no description available + 3 + 1 + read-only + + + dmfc_ic_ppw_c + no description available + 4 + 2 + read-write + + + 00 + 8 bit per pixel + #00 + + + 01 + 16 bit per pixel + #01 + + + 10 + 24 bit per pixel + #10 + + + 11 + Reserved + #11 + + + + + dmfc_ic_frame_width_rd + no description available + 6 + 13 + read-write + + + dmfc_ic_frame_height_rd + no description available + 19 + 13 + read-write + + + + + DMFC_WR_CHAN_ALT + DMFC Write Channel Alternate Register + 0x60020 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 8 + read-only + + + dmfc_st_addr_2_alt + no description available + 8 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_2_alt + no description available + 11 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_2_alt + no description available + 14 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DMFC_WR_CHAN_DEF_ALT + DMFC Write Channel Definition Alternate Register + 0x60024 + 32 + read-write + 0x2000 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 9 + read-only + + + dmfc_wm_en_2_alt + no description available + 9 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_2_alt + no description available + 10 + 3 + read-write + + + dmfc_wm_clr_2_alt + no description available + 13 + 3 + read-write + + + RESERVED + no description available + 16 + 16 + read-only + + + + + DMFC_DP_CHAN_ALT + DMFC MFC Display Processor Channel Alternate Register + 0x60028 + 32 + read-write + 0 + 0xFFFFFFFF + + + dmfc_st_addr_5b_alt + no description available + 0 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_5b_alt + no description available + 3 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_5b_alt + no description available + 6 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + RESERVED + no description available + 8 + 8 + read-only + + + dmfc_st_addr_6b_alt + no description available + 16 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_6b_alt + no description available + 19 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_6b_alt + no description available + 22 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + dmfc_st_addr_6f_alt + no description available + 24 + 3 + read-write + + + 000 + Segment 0 + #000 + + + 001 + Segment 1 + #001 + + + 111 + Segment 7 + #111 + + + + + dmfc_fifo_size_6f_alt + no description available + 27 + 3 + read-write + + + 000 + All (512X128 words) the DMFC's FIFO is allocated to this channel + #000 + + + 001 + 256X128 words are allocated to this channel + #001 + + + 010 + 128X128 words are allocated to this channel + #010 + + + 011 + 64X128 words are allocated to this channel + #011 + + + 100 + 32X128 words are allocated to this channel + #100 + + + 101 + 16X128 words are allocated to this channel + #101 + + + 110 + 8X128 words are allocated to this channel + #110 + + + 111 + 4X128 words are allocated to this channel + #111 + + + + + dmfc_burst_size_6f_alt + no description available + 30 + 2 + read-write + + + 00 + 32 words of 128 bit (4 pixels of 32 bit each, coming from the IDMAC) + #00 + + + 01 + 16 words of 128 bit + #01 + + + 10 + 8 words of 128 bit + #10 + + + 11 + 4 words of 128 bit + #11 + + + + + + + DMFC_DP_CHAN_DEF_ALT + DMFC Display Channel Definition Alternate Register + 0x6002C + 32 + read-write + 0x20200020 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + dmfc_wm_en_5b_alt + no description available + 1 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_5b_alt + no description available + 2 + 3 + read-write + + + dmfc_wm_clr_5b_alt + no description available + 5 + 3 + read-write + + + RESERVED + no description available + 8 + 9 + read-only + + + dmfc_wm_en_6b_alt + no description available + 17 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_6b_alt + no description available + 18 + 3 + read-write + + + dmfc_wm_clr_6b_alt + no description available + 21 + 3 + read-write + + + RESERVED + no description available + 24 + 1 + read-only + + + dmfc_wm_en_6f_alt + no description available + 25 + 1 + read-write + + + 1 + WM feature is enabled + #1 + + + 0 + WM feature is disabled + #0 + + + + + dmfc_wm_set_6f_alt + no description available + 26 + 3 + read-write + + + dmfc_wm_clr_6f_alt + no description available + 29 + 3 + read-write + + + + + DMFC_GENERAL1_ALT + DMFC General 1 Alternate Register + 0x60030 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 17 + read-only + + + WAIT4EOT_2_ALT + no description available + 17 + 1 + read-write + + + 1 + FIFO #2 is in wait4eot mode (for alternate flow) + #1 + + + 0 + FIFO #2 is in normal mode (for alternate flow) + #0 + + + + + RESERVED + no description available + 18 + 2 + read-only + + + WAIT4EOT_5B_ALT + no description available + 20 + 1 + read-write + + + 1 + FIFO #5B is in wait4eot mode (for alternate flow) + #1 + + + 0 + FIFO #5B is in normal mode (for alternate flow) + #0 + + + + + RESERVED + no description available + 21 + 1 + read-only + + + WAIT4EOT_6B_ALT + no description available + 22 + 1 + read-write + + + 1 + FIFO #6B is in wait4eot mode (for alternate flow) + #1 + + + 0 + FIFO #6B is in normal mode (for alternate flow) + #0 + + + + + WAIT4EOT_6F_ALT + no description available + 23 + 1 + read-write + + + 1 + FIFO #6F is in wait4eot mode (for alternate flow) + #1 + + + 0 + FIFO #6F is in normal mode (for alternate flow) + #0 + + + + + RESERVED + no description available + 24 + 8 + read-only + + + + + DMFC_STAT + DMFC Status Register + 0x60034 + 32 + read-only + 0x2FFF000 + 0xFFFFFFFF + + + DMFC_FIFO_FULL_i + no description available + 0 + 12 + read-only + + + 0 + FIFO #<i> is not full + #0 + + + 1 + FIFO #<i> is full + #1 + + + + + DMFC_FIFO_EMPTY_i + no description available + 12 + 12 + read-only + + + 0 + FIFO #<i> is not empty + #0 + + + 1 + FIFO #<i> is empty + #1 + + + + + DMFC_IC_BUFFER_FULL + no description available + 24 + 1 + read-only + + + 0 + IC FIFO not full + #0 + + + 1 + IC FIFO is full + #1 + + + + + DMFC_IC_BUFFER_EMPTY + no description available + 25 + 1 + read-only + + + 0 + IC FIFO not empty + #0 + + + 1 + IC FIFO is empty + #1 + + + + + RESERVED + no description available + 26 + 6 + read-only + + + + + VDI_FSIZE + VDI Field Size Register + 0x68000 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_FWIDTH + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + VDI_FHEIGHT + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDI_C + VDI Control Register + 0x68004 + 32 + read-write + 0 + 0xFFFFFFFF + + + RESERVED + no description available + 0 + 1 + read-only + + + VDI_CH_422 + no description available + 1 + 1 + read-write + + + 0 + Chroma format is 420. + #0 + + + 1 + Chroma format is 422. + #1 + + + + + VDI_MOT_SEL + no description available + 2 + 2 + read-write + + + 0 + Motion determined by ROM "1" (shared toward medium/high motion). + #0 + + + 1 + Motion determined by ROM "2" (This option will not work well for high motion). + #1 + + + + + VDI_BURST_SIZE1 + no description available + 4 + 4 + read-write + + + 0 + Burst size is 1 access. + #0 + + + 1 + Burst size is 2 accesses. + #1 + + + + + VDI_BURST_SIZE2 + no description available + 8 + 4 + read-write + + + 0 + Burst size is 1 access. + #0 + + + 1 + Burst size is 2 accesses. + #1 + + + + + VDI_BURST_SIZE3 + no description available + 12 + 4 + read-write + + + 0 + Burst size is 1 access. + #0 + + + 1 + Burst size is 2 accesses. + #1 + + + + + VDI_VWM1_SET + no description available + 16 + 3 + read-write + + + 0 + set watermark level when FIFO1 is full on 1/8 of their size. + #0 + + + 1 + set watermark level when FIFO1 is full on 2/8 of their size. + #1 + + + + + VDI_VWM1_CLR + no description available + 19 + 3 + read-write + + + 0 + clear watermark level when FIFO1 is full on 1/8 of their size. + #0 + + + 1 + clear watermark level when FIFO1 is full on 2/8 of their size. + #1 + + + + + VDI_VWM3_SET + no description available + 22 + 3 + read-write + + + 0 + set watermark level when FIFO3 is full on 1/8 of their size. + #0 + + + 1 + set watermark level when FIFO3 is full on 2/8 of their size. + #1 + + + + + VDI_VWM3_CLR + no description available + 25 + 3 + read-write + + + 0 + clear watermark level when FIFO3 is full on 1/8 of their size. + #0 + + + 1 + clear watermark level when FIFO3 is full on 2/8 of their size. + #1 + + + + + RESERVED + no description available + 28 + 2 + read-only + + + RESERVED + no description available + 30 + 1 + read-write + + + 0 + top field is field 0 + #0 + + + 1 + top field is field 1 + #1 + + + + + RESERVED + no description available + 31 + 1 + read-write + + + 0 + top field is field 0 + #0 + + + 1 + top field is field 1 + #1 + + + + + + + VDI_C2_ + VDI Control Register 2 + 0x68008 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_CMB_EN + no description available + 0 + 1 + read-write + + + 0 + Combining disabled. The VDIC works in de-interlacing mode + #0 + + + 1 + Combining enabled. The de-interlacing mode is not functional + #1 + + + + + VDI_KEY_COLOR_EN + no description available + 1 + 1 + read-write + + + 0 + Key Color disabled. + #0 + + + 1 + Key color enabled + #1 + + + + + VDI_GLB_A_EN + no description available + 2 + 1 + read-write + + + 0 + Alpha is local + #0 + + + 1 + Alpha is global + #1 + + + + + VDI_PLANE_1_EN + no description available + 3 + 1 + read-write + + + 0 + plane #1 is disabled + #0 + + + 1 + plane #1 is enabled + #1 + + + + + RESERVED + no description available + 4 + 28 + read-only + + + + + VDI_CMDP_1 + VDI Combining Parameters Register 1 + 0x6800C + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_KEY_COLOR_B + no description available + 0 + 8 + read-write + + + VDI_KEY_COLOR_G + no description available + 8 + 8 + read-write + + + VDI_KEY_COLOR_R + no description available + 16 + 8 + read-write + + + VDI_ALPHA + no description available + 24 + 8 + read-write + + + + + VDI_CMDP_2 + VDI Combining Parameters Register 2 + 0x68010 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_KEY_COLOR_B + no description available + 0 + 8 + read-write + + + VDI_KEY_COLOR_G + no description available + 8 + 8 + read-write + + + VDI_KEY_COLOR_R + no description available + 16 + 8 + read-write + + + RESERVED + no description available + 24 + 8 + read-only + + + + + VDI_PS_1 + VDI Plane Size Register 1 + 0x68014 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_FWIDTH1 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + VDI_FHEIGHT1 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDI_PS_2 + VDI Plane Size Register 2 + 0x68018 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_OFFSET_HOR1 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + VDI_OFFSET_VER1 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDI_PS_3 + VDI Plane Size Register 3 + 0x6801C + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_FWIDTH3 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + VDI_FHEIGHT3 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + VDI_PS_4 + VDI Plane Size Register 4 + 0x68020 + 32 + read-write + 0 + 0xFFFFFFFF + + + VDI_OFFSET_HOR3 + no description available + 0 + 11 + read-write + + + RESERVED + no description available + 11 + 5 + read-only + + + VDI_OFFSET_VER3 + no description available + 16 + 11 + read-write + + + RESERVED + no description available + 27 + 5 + read-only + + + + + + + diff --git a/tbot_contrib/register/register.py b/tbot_contrib/register/register.py new file mode 100644 index 00000000..764a8969 --- /dev/null +++ b/tbot_contrib/register/register.py @@ -0,0 +1,210 @@ +import tbot +import typing +import pickle +import os +from tbot.machine.shell import Shell +from tbot.machine import Machine, linux, board +import register + + +class Register: + def __init__(self, name: str, address: int, width: int) -> None: + self.name = name + self.address = address + assert width in [8, 16, 32, 64], f"Unsupported register width: {width!r}" + self.width = width + + +class CPU: + def __init__( + self, host: Shell, processor_name: str = "", cpu_bits: int = 0 + ) -> None: + self.set_host(host) + if processor_name != "": + THIS_FOLDER = os.path.dirname(os.path.abspath(__file__)) + file_name = os.path.join(THIS_FOLDER, f"{processor_name}.pkl") + with open(file_name, "rb") as f: + self._cpu_bits, self._groups_dict, self._registers_dict = pickle.load(f) + + elif cpu_bits > 0: + assert cpu_bits in [32, 64], f"Unsupported register width: {cpu_bits!r}" + self._cpu_bits = cpu_bits + self._groups_dict = {} + self._registers_dict = {} + + else: + raise Exception(f"Wrong arguments") + + def __validate_host(self, host: Shell) -> None: + self._host = host + if isinstance(host, board.UBootShell): + self._host_name = "uboot" + + elif isinstance(host, linux.LinuxShell): + self._host_name = "linux" + else: + raise Exception( + f"You are not in an allowed context (linux machine or uboot machine)" + ) + + def set_host(self, host: Shell) -> None: + self.__validate_host(host) + self._host = host + + def add_register_to_group(self, group_name: str, register: Register) -> None: + if group_name in self._groups_dict: + self._groups_dict[group_name].append(register.name) + self._registers_dict[register.name] = register + + else: + self._groups_dict[group_name] = [] + self._groups_dict[group_name].append(register.name) + self._registers_dict[register.name] = register + + def remove_register_from_group( + self, group_name: str, register_name: str + ) -> Register: + if not (group_name in self._groups_dict): + raise Exception(f"There is not a group with the name: {group_name}") + + if not (register_name in self._groups_dict[group_name]): + raise Exception( + f"There is not a register with the name: {register_name} in the group: {group_name}" + ) + + self._groups_dict[group_name].remove(register_name) + return self._registers_dict[register_name] + + def get_register_from_group(self, group_name: str, register_name: str) -> Register: + if not (group_name in self._groups_dict): + raise Exception(f"There is not a group with the name: {group_name}") + + if not (register_name in self._groups_dict[group_name]): + raise Exception( + f"There is not a register with the name: {register_name} in the group: {group_name}" + ) + + return self._registers_dict[register_name] + + def get_all_registers_from_group(self, group_name: str) -> typing.List[Register]: + if not (group_name in self._groups_dict): + raise Exception(f"There is not a group with the name: {group_name}") + return list(self._groups_dict[group_name].values()) + + def __bit_parser_kernel(self, width: int) -> str: + if width > self._cpu_bits: + raise Exception(f"Maximun register width is: {self._cpu_bits}") + + if width == 8: + return "b" + elif width == self._cpu_bits: + return "w" + elif width == (self._cpu_bits / 2): + return "h" + else: + raise Exception(f"Not a valid width") + + def __bit_parser_uboot(self, width: int) -> typing.Tuple[str, int]: + if width > self._cpu_bits: + raise Exception(f"Maximun register width is: {self._cpu_bits}") + + if width == 8: + return ".b", 1 + elif width == 16: + return ".w", 1 + elif width == 32: + return ".l", 1 + elif width > 32: + i = width / 32 + return ".l", int(i) + + def __validate_register_address_alignment(self, register: Register) -> bool: + address = str(hex(register.address)) + multiple_word = self._cpu_bits / 8 + multiple_halfword = multiple_word / 2 + if register.width == 8: + return True + elif register.width == self._cpu_bits: + if (int(address[-1], 16) % multiple_word) == 0: + return True + elif register.width == (self._cpu_bits / 2): + if (int(address[-1], 16) % multiple_halfword) == 0: + return True + return False + + def read_register(self, register_name: str) -> None: + if not (register_name in self._registers_dict): + raise Exception(f"There is not a register with the name: {register_name}") + + if self.__validate_register_address_alignment( + self._registers_dict[register_name] + ): + if self._host_name == "linux": + self._host.exec( + "devmem2", + str(hex(self._registers_dict[register_name].address)), + self.__bit_parser_kernel(self._registers_dict[register_name].width), + ) + elif self._host_name == "uboot": + l, m = self.__bit_parser_uboot( + self._registers_dict[register_name].width + ) + command = "md" + l + for i in range(0, m): + if i == 0: + self._host.exec( + command, + str(hex(self._registers_dict[register_name].address)), + "1", + ) + else: + # it needs work. + self._host.exec(command) + else: + tbot.log.message( + f"The register: {self._registers_dict[register_name].name} has an unaligned address: {hex(self._registers_dict[register_name].address)} with width: {self._registers_dict[register_name].width}" + ) + + def read_all_registers_from_group(self, group_name: str) -> None: + if not (group_name in self._groups_dict): + raise Exception(f"There is not a group with the name: {group_name}") + if self._groups_dict[group_name] == []: + raise Exception(f"The group: {group_name} is empty") + + for register_name in self._groups_dict[group_name]: + self.read_register(register_name) + + def write_register(self, register_name: str, value: int) -> None: + if not (register_name in self._registers_dict): + raise Exception(f"There is not a register with the name: {register_name}") + + if self.__validate_register_address_alignment( + self._registers_dict[register_name] + ): + if self._host_name == "linux": + self._host.exec( + "devmem2", + hex(self._registers_dict[register_name].address), + self.__bit_parser_kernel(self._registers_dict[register_name].width), + hex(value), + ) + elif self._host_name == "uboot": + l, m = self.__bit_parser_uboot( + self._registers_dict[register_name].width + ) + command = "mw" + l + for i in range(0, m): + if i == 0: + self._host.exec( + command, + hex(self._registers_dict[register_name].address), + hex(value), + "1", + ) + else: + # it needs work. + self._host.exec(command) + else: + tbot.log.message( + f"The register: {self._registers_dict[register_name].name} has an unaligned address: {hex(self._registers_dict[register_name].address)} with width: {self._registers_dict[register_name].width}" + )