diff --git a/.gitignore b/.gitignore index cca5331..95131b9 100644 --- a/.gitignore +++ b/.gitignore @@ -23,4 +23,5 @@ Cargo.lock .DS_Store *~ - +# Vim temporary files +*.swp diff --git a/Makefile b/Makefile index 7bc63e8..a775b9d 100644 --- a/Makefile +++ b/Makefile @@ -15,6 +15,13 @@ build-mgmt: flash-mgmt: cd mgmt && cargo flash --release --chip STM32F072CBTx +# XXX(RLB) This line has a bunch of special cases for my laptop that probably +# won't work elsewhere +flasher-mgmt: + cd mgmt && cargo objcopy --release --target=thumbv6m-none-eabi -- -O binary target/mgmt.bin + python3 ../hactar/software/flasher/main.py --baud=115200 --chip="mgmt" --port=/dev/tty.usbserial-10 \ + -bin=mgmt/target/mgmt.bin + run-mgmt: echo run "openocd -f mgmt/openocd.cfg" in background echo run something like "screen /dev/tty.usbserial-120 115200" in another window diff --git a/mgmt/mem072.x b/mgmt/mem072.x index bd5ed8d..97493c2 100644 --- a/mgmt/mem072.x +++ b/mgmt/mem072.x @@ -33,12 +33,12 @@ SECTIONS *(.rodata .rodata.*); } > FLASH - .data : ALIGN(4) /* AT(ADDR(.rodata) + SIZEOF(.rodata)) */ + .data : ALIGN(4) { _sdata = .; *(.data .data.*); _edata = .; - } > RAM AT > FLASH + } > RAM AT > FLASH _sidata = LOADADDR(.data); @@ -49,16 +49,10 @@ SECTIONS _ebss = .; } > RAM - .heap_start : - { - _heap_start = .; - . = ALIGN(4); - . = . + _Heap_Size; - _stack_reserve_start = .; - . = . + _Stack_Size; - _stack_reserve_end = .; - . = ALIGN(4); - } > RAM + /* Heap and stack symbols defined without creating sections */ + _heap_start = .; + _stack_reserve_start = _heap_start + _Heap_Size; + _stack_reserve_end = _stack_reserve_start + _Stack_Size; .stack_sizes (INFO) : { diff --git a/neo/mgmt-cots/.cargo/config.toml b/neo/mgmt-cots/.cargo/config.toml new file mode 100644 index 0000000..c1fd4a2 --- /dev/null +++ b/neo/mgmt-cots/.cargo/config.toml @@ -0,0 +1,8 @@ +[target.thumbv6m-none-eabi] +rustflags = [ + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=--nmagic", +] + +[build] +target = "thumbv6m-none-eabi" diff --git a/neo/mgmt-cots/.claude/settings.local.json b/neo/mgmt-cots/.claude/settings.local.json new file mode 100644 index 0000000..7b8b289 --- /dev/null +++ b/neo/mgmt-cots/.claude/settings.local.json @@ -0,0 +1,8 @@ +{ + "permissions": { + "allow": [ + "Bash(cargo:*)" + ], + "deny": [] + } +} \ No newline at end of file diff --git a/neo/mgmt-cots/Cargo.toml b/neo/mgmt-cots/Cargo.toml new file mode 100644 index 0000000..6b27847 --- /dev/null +++ b/neo/mgmt-cots/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "mgmt-cots" +version = "0.1.0" +edition = "2024" + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = "0.7" +panic-halt = "0.2" +stm32f0xx-hal = { version = "0.18", features = ["stm32f072", "rt"] } +embedded-dma = "0.2" +nb = "1" +heapless = { version = "0.8", features = ["portable-atomic-unsafe-assume-single-core"] } diff --git a/neo/mgmt-cots/Makefile b/neo/mgmt-cots/Makefile new file mode 100644 index 0000000..98b5c36 --- /dev/null +++ b/neo/mgmt-cots/Makefile @@ -0,0 +1,8 @@ +FLASHER=../../../hactar/software/flasher/main.py +PORT=/dev/tty.usbserial-10 + +.PHONY: flash + +flash: + cargo objcopy --release --target=thumbv6m-none-eabi -- -O binary target/mgmt.bin + python3 ${FLASHER} --baud=115200 --chip=mgmt --port=${PORT} --bin=target/mgmt.bin diff --git a/neo/mgmt-cots/README.md b/neo/mgmt-cots/README.md new file mode 100644 index 0000000..0aa0edf --- /dev/null +++ b/neo/mgmt-cots/README.md @@ -0,0 +1,75 @@ +MGMT with [COTS] parts +====================== + +In the interest of getting the firmware design moving quickly, this crate is an +effort to get the management chip running using an [off-the-shelf HAL] as much as +possible. With the idea that we can strip it down to something more minimal +later, once we have things working. + +## Architecture + +In brief: + +* The `board` module defines how the hardware board is put together. +* The `app` module defines the application logic and the traits of the board + that it depends on. +* The `main` file instantiates the board and the app, and organizes the + execution in the main function and ISRs. + +``` ++-----------+ +-----------+ +-----------+ +| | | | | | +| |-------Events------>| |-------Events------>| | +| Board | | Main | | App | +| |<------------------------------------Capabilities----| | +| | | | | | ++-----------+ +-----------+ +-----------+ + ^ + | + | + Events + | + | + +-----------+ + | | + | | + | ISRs | + | | + | | + +-----------+ +``` + +The main logic of the application is in the function `App::handle(event, +capbilities...)`. +The application takes in events that reflect inputs from the hardware, and acts +on them using the capabilities. The capabilities are defined using traits, +which are defined in the `app` module and implemented in the `board` module. + +In `main.rs`, the board and app are instantiated, as well as a queue of events. +ISRs asynchronously add events to the queue, and the main loop polls for +synchronous events and triggers the app to process events from the queue. + +The idea is that ultimately, the app could be pulled out into a separate crate, +and instantiated on different hardware. The app crate would define +hardware-independent interfaces and logic. The device-specific crate would +have the app crate as a dependency. It would implement the required interfaces +(as the `board` module does here) and instantiate the app with inputs from the +board (as the `main` module does here). + +## What it actually does + +Right now, the firmware does two things, blink and echo. + +The blinking LED demonstrates asynchronous events. A 1Hz timer is set, which +causes the TIM7 interrupt to fire. That ISR adds a `Timer1Hz` event to the +queue. When the app processes that event shortly thereafter, an reference to +the LED is passed as a capability, which the app uses to toggle the LED. + +The echo functionality echos text from the UART1 back to UART, with "hello: " +prepended. This illustrates synchronous events, since the UART receiver has to +be polled. It also illustrates how the app can use internal state, as it +maintains an internal buffer for characters received from UART. The send/Tx +side of the UART channel is passed to the app as a capability. + +[COTS]: https://en.wikipedia.org/wiki/Commercial_off-the-shelf +[off-the-shelf HAL]: https://docs.rs/stm32f0xx-hal diff --git a/neo/mgmt-cots/memory.x b/neo/mgmt-cots/memory.x new file mode 100644 index 0000000..c4ef437 --- /dev/null +++ b/neo/mgmt-cots/memory.x @@ -0,0 +1,11 @@ +MEMORY +{ + /* NOTE K = KiBi = 1024 bytes */ + FLASH : ORIGIN = 0x08000000, LENGTH = 128K + RAM : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/neo/mgmt-cots/src/app.rs b/neo/mgmt-cots/src/app.rs new file mode 100644 index 0000000..c500018 --- /dev/null +++ b/neo/mgmt-cots/src/app.rs @@ -0,0 +1,43 @@ +use core::fmt::Write; + +pub enum Event { + ConsoleRx(u8), + Timer1Hz, +} + +pub trait Toggle { + fn toggle(&mut self); +} + +#[derive(Default)] +pub struct App { + line: heapless::String<128>, +} + +impl App { + pub fn timer_1hz(&mut self, led: &mut dyn Toggle) { + led.toggle(); + } + + pub fn handle_byte(&mut self, byte: u8, tx: &mut dyn Write) { + // Still building string + if byte != b'\r' && self.line.len() < self.line.capacity() { + self.line.push(byte as char).ok(); + return; + } + + // End-of-line => send response + tx.write_str("hello: ").ok(); + tx.write_str(self.line.as_str()).ok(); + tx.write_str("\r\n").ok(); + + self.line.clear(); + } + + pub fn handle(&mut self, event: Event, tx: &mut dyn Write, led_a: &mut dyn Toggle) { + match event { + Event::ConsoleRx(b) => self.handle_byte(b, tx), + Event::Timer1Hz => self.timer_1hz(led_a), + } + } +} diff --git a/neo/mgmt-cots/src/board/led.rs b/neo/mgmt-cots/src/board/led.rs new file mode 100644 index 0000000..0ae823e --- /dev/null +++ b/neo/mgmt-cots/src/board/led.rs @@ -0,0 +1,98 @@ +use crate::app::Toggle; +use stm32f0xx_hal::prelude::_embedded_hal_gpio_OutputPin as OutputPin; + +#[allow(dead_code)] // Don't warn if we don't use every color +#[derive(Copy, Clone)] +pub enum Color { + Black, + White, + Red, + Green, + Blue, + Teal, + Yellow, + Purple, +} + +impl Color { + fn rgb(&self) -> (bool, bool, bool) { + match self { + Self::Black => (false, false, false), + Self::Red => (true, false, false), + Self::Green => (false, true, false), + Self::Blue => (false, false, true), + Self::Teal => (false, true, true), + Self::Purple => (true, false, true), + Self::Yellow => (true, true, false), + Self::White => (true, true, true), + } + } +} + +trait Set { + fn set(&mut self, high: bool); +} + +impl Set for T { + fn set(&mut self, high: bool) { + let _ = if high { + self.set_high() + } else { + self.set_low() + }; + } +} + +pub struct Led { + on: bool, + color: Color, + r: R, + g: G, + b: B, +} + +impl Led +where + R: OutputPin, + G: OutputPin, + B: OutputPin, +{ + pub fn new(r: R, g: G, b: B) -> Self { + Self { + on: false, + color: Color::Black, + r, + g, + b, + } + } + + fn raw_set(&mut self, c: Color) { + let (r, g, b) = c.rgb(); + self.r.set(r ^ INVERT); + self.g.set(g ^ INVERT); + self.b.set(b ^ INVERT); + } + + pub fn set(&mut self, c: Color) { + self.on = true; + self.color = c; + self.raw_set(c); + } +} + +impl Toggle for Led +where + R: OutputPin, + G: OutputPin, + B: OutputPin, +{ + fn toggle(&mut self) { + self.on = !self.on; + if self.on { + self.raw_set(self.color); + } else { + self.raw_set(Color::Black); + } + } +} diff --git a/neo/mgmt-cots/src/board/mod.rs b/neo/mgmt-cots/src/board/mod.rs new file mode 100644 index 0000000..ceb3528 --- /dev/null +++ b/neo/mgmt-cots/src/board/mod.rs @@ -0,0 +1,114 @@ +pub mod led; + +use led::Led; +use stm32f0xx_hal::{ + pac::{self, Interrupt}, + prelude::*, + serial::Serial, + timers::{Event, Timer}, +}; + +mod led_a { + use stm32f0xx_hal::gpio::{gpioa, Output, PushPull}; + pub type RedPin = gpioa::PA4>; + pub type GreenPin = gpioa::PA6>; + pub type BluePin = gpioa::PA7>; +} + +mod led_b { + use stm32f0xx_hal::gpio::{gpiob, Output, PushPull}; + pub type RedPin = gpiob::PB0>; + pub type GreenPin = gpiob::PB14>; + pub type BluePin = gpiob::PB15>; +} + +mod console { + use stm32f0xx_hal::{ + gpio::{gpioa, Alternate, AF1}, + pac, + }; + pub type Tx = gpioa::PA9>; + pub type Rx = gpioa::PA10>; + pub type Usart = pac::USART1; + pub const BAUD_RATE: u32 = 115_200; +} + +mod timer { + use stm32f0xx_hal::pac; + pub type Timer = pac::TIM7; +} + +pub type LedA = Led; +pub type LedB = Led; +pub type Console = Serial; +pub type Timer1Hz = Timer; + +pub struct Board { + pub led_a: LedA, + pub led_b: LedB, + pub console: Console, + pub timer: Timer1Hz, +} + +impl Board { + pub fn new() -> Self { + let cp = cortex_m::peripheral::Peripherals::take().unwrap(); + let mut dp = pac::Peripherals::take().unwrap(); + let mut rcc = dp + .RCC + .configure() + .hsi48() + .enable_crs(dp.CRS) + .sysclk(48.mhz()) + .pclk(24.mhz()) + .freeze(&mut dp.FLASH); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpiob = dp.GPIOB.split(&mut rcc); + + // Configure GPIO pins + let (led_a_r, led_a_g, led_a_b, led_b_r, led_b_g, led_b_b, tx_pin, rx_pin) = + cortex_m::interrupt::free(|cs| { + let led_a_r = gpioa.pa4.into_push_pull_output(cs); + let led_a_g = gpioa.pa6.into_push_pull_output(cs); + let led_a_b = gpioa.pa7.into_push_pull_output(cs); + let led_b_r = gpiob.pb0.into_push_pull_output(cs); + let led_b_g = gpiob.pb14.into_push_pull_output(cs); + let led_b_b = gpiob.pb15.into_push_pull_output(cs); + let tx_pin = gpioa.pa9.into_alternate_af1(cs); + let rx_pin = gpioa.pa10.into_alternate_af1(cs); + ( + led_a_r, led_a_g, led_a_b, led_b_r, led_b_g, led_b_b, tx_pin, rx_pin, + ) + }); + + // Configure LEDs + let led_a = Led::new(led_a_r, led_a_g, led_a_b); + let led_b = Led::new(led_b_r, led_b_g, led_b_b); + + // Configure the console UART + let console = Serial::usart1( + dp.USART1, + (tx_pin, rx_pin), + console::BAUD_RATE.bps(), + &mut rcc, + ); + + // Configure the 1s timer + let mut timer = Timer::tim7(dp.TIM7, 1.hz(), &mut rcc); + timer.listen(Event::TimeOut); + + let mut nvic = cp.NVIC; + unsafe { + nvic.set_priority(Interrupt::TIM7, 1); + cortex_m::peripheral::NVIC::unmask(Interrupt::TIM7); + } + cortex_m::peripheral::NVIC::unpend(Interrupt::TIM7); + + Self { + led_a, + led_b, + console, + timer, + } + } +} diff --git a/neo/mgmt-cots/src/main.rs b/neo/mgmt-cots/src/main.rs new file mode 100644 index 0000000..7b9376a --- /dev/null +++ b/neo/mgmt-cots/src/main.rs @@ -0,0 +1,68 @@ +#![no_std] +#![no_main] + +mod app; +mod board; + +use cortex_m_rt::entry; +use panic_halt as _; +use stm32f0xx_hal::prelude::*; + +use app::{App, Event}; +use board::led::Color; +use board::{Board, Timer1Hz}; + +use core::cell::RefCell; +use cortex_m::interrupt::Mutex; +use heapless::mpmc::Q64; +use stm32f0xx_hal::pac::interrupt; + +static GINT: Mutex>> = Mutex::new(RefCell::new(None)); +static EVENT_QUEUE: Q64 = Q64::new(); + +#[interrupt] +fn TIM7() { + static mut INT: Option = None; + + let int = INT.get_or_insert_with(|| { + cortex_m::interrupt::free(|cs| GINT.borrow(cs).replace(None).unwrap()) + }); + + // XXX(RLB) Silently drops events + let _ = EVENT_QUEUE.enqueue(Event::Timer1Hz); + int.wait().ok(); +} + +#[entry] +fn main() -> ! { + // Instantiate the board + let mut board = Board::new(); + + // Instantiate the app + let mut app = App::default(); + + // Configure the LEDs + board.led_a.set(Color::Blue); + board.led_b.set(Color::Red); + + // Make shared resources available to interrupts + cortex_m::interrupt::free(move |cs| { + *GINT.borrow(cs).borrow_mut() = Some(board.timer); + }); + + // Working buffer for the line we are building + let (mut tx, mut rx) = board.console.split(); + + loop { + // Poll inputs that don't come in asynchronously + if let Ok(byte) = rx.read() { + // XXX(RLB) Silently drops events + let _ = EVENT_QUEUE.enqueue(Event::ConsoleRx(byte)); + } + + // Process the next event + if let Some(event) = EVENT_QUEUE.dequeue() { + app.handle(event, &mut tx, &mut board.led_a); + } + } +} diff --git a/neo/mgmt-stm32/.cargo/config.toml b/neo/mgmt-stm32/.cargo/config.toml new file mode 100644 index 0000000..3235722 --- /dev/null +++ b/neo/mgmt-stm32/.cargo/config.toml @@ -0,0 +1,9 @@ + +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +runner = "arm-none-eabi-gdb -q -x openocd.gdb" +rustflags = [ + "-Clink-arg=-Tmem072.x", +] + +[build] +target = "thumbv6m-none-eabi" \ No newline at end of file diff --git a/neo/mgmt-stm32/Cargo.toml b/neo/mgmt-stm32/Cargo.toml new file mode 100644 index 0000000..9a15947 --- /dev/null +++ b/neo/mgmt-stm32/Cargo.toml @@ -0,0 +1,10 @@ +[package] +name = "mgmt-stm32" +version = "0.1.0" +edition = "2024" + +[build-dependencies] +svdgen = { path = "../svdgen" } + +[dependencies] +paste = "1.0.15" diff --git a/neo/mgmt-stm32/Makefile b/neo/mgmt-stm32/Makefile new file mode 100644 index 0000000..98b5c36 --- /dev/null +++ b/neo/mgmt-stm32/Makefile @@ -0,0 +1,8 @@ +FLASHER=../../../hactar/software/flasher/main.py +PORT=/dev/tty.usbserial-10 + +.PHONY: flash + +flash: + cargo objcopy --release --target=thumbv6m-none-eabi -- -O binary target/mgmt.bin + python3 ${FLASHER} --baud=115200 --chip=mgmt --port=${PORT} --bin=target/mgmt.bin diff --git a/neo/mgmt-stm32/STM32F0x2.svd b/neo/mgmt-stm32/STM32F0x2.svd new file mode 100644 index 0000000..5a2adb2 --- /dev/null +++ b/neo/mgmt-stm32/STM32F0x2.svd @@ -0,0 +1,42946 @@ + + + + CM0 + r1p1 + little + false + false + true + 2 + false + + STM32F0x2 + 1.0 + STM32F072 + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + CRC + cyclic redundancy check calculation + unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + 0 + 4294967295 + + + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register + bits + 0 + 8 + + + 0 + 255 + + + + + + + CR + CR + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RESET + reset bit + 0 + 1 + + RESET + write + + Reset + Resets the CRC calculation unit + 1 + + + + + POLYSIZE + Polynomial size + 3 + 2 + + SIZE + read-write + + 32bits + 32 bit polynomial. + 0 + + + 16bits + 16 bit polynomial. + 1 + + + 8bits + 8 bit polynomial. + 2 + + + 7bits + 7 bit polynomial. + 3 + + + + + REV_IN + Reverse input data + 5 + 2 + + INPUTREVERSE + read-write + + NoReverse + Bit order not affected. + 0 + + + Byte + Bit reversal done by byte. + 1 + + + HalfWord + Bit reversal done by half-word. + 2 + + + 7bits + Bit reversal done by word. + 3 + + + + + REV_OUT + Reverse output data + 7 + 1 + + OUTPUTREVERSE + + NoReverse + Bit order not affected. + 0 + + + Reverse + Bit-reversed output format. + 1 + + + + + + + INIT + INIT + Initial CRC value + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC + value + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + GPIOF + General-purpose I/Os + GPIO + 0x48001400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + MODE + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bit + 15 + 15 + 1 + + OUTPUTTYPE + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + OT14 + Port x configuration bit + 14 + 14 + 1 + + + + + OT13 + Port x configuration bit + 13 + 13 + 1 + + + + + OT12 + Port x configuration bit + 12 + 12 + 1 + + + + + OT11 + Port x configuration bit + 11 + 11 + 1 + + + + + OT10 + Port x configuration bit + 10 + 10 + 1 + + + + + OT9 + Port x configuration bit 9 + 9 + 1 + + + + + OT8 + Port x configuration bit 8 + 8 + 1 + + + + + OT7 + Port x configuration bit 7 + 7 + 1 + + + + + OT6 + Port x configuration bit 6 + 6 + 1 + + + + + OT5 + Port x configuration bit 5 + 5 + 1 + + + + + OT4 + Port x configuration bit 4 + 4 + 1 + + + + + OT3 + Port x configuration bit 3 + 3 + 1 + + + + + OT2 + Port x configuration bit 2 + 2 + 1 + + + + + OT1 + Port x configuration bit 1 + 1 + 1 + + + + + OT0 + Port x configuration bit 0 + 0 + 1 + + + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + OUTPUTSPEED + + LowSpeed + Low Speed + 0 + + + MediumSpeed + Medium Speed + 1 + + + HighSpeed + High Speed + 3 + + + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + PULLCONFIG + + NoPull + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + Reserved + Reserved + 3 + + + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + OUTPUTVALUE + + Reset + Reset output value + 0 + + + Set + Set output value + 1 + + + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + RESET + write + + Reset + Resets the corresponding ODRx bit + 1 + + + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + SET + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y + 16 + 1 + + LOCKON + + Inactive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + LOCK + + Unlock + Port configuration not locked + 0 + + + Lock + Port configuration locked + 1 + + + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + ALTFUNCTION + + AF0 + Alternate Function 0 + 0 + + + AF1 + Alternate Function 1 + 1 + + + AF2 + Alternate Function 2 + 2 + + + AF3 + Alternate Function 3 + 3 + + + AF4 + Alternate Function 4 + 4 + + + AF5 + Alternate Function 5 + 5 + + + AF6 + Alternate Function 6 + 6 + + + AF7 + Alternate Function 7 + 7 + + + RESERVED + RESERVED + 8 + + + RESERVED + RESERVED + 9 + + + RESERVED + RESERVED + 10 + + + RESERVED + RESERVED + 11 + + + RESERVED + RESERVED + 12 + + + RESERVED + RESERVED + 13 + + + RESERVED + RESERVED + 14 + + + RESERVED + RESERVED + 15 + + + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + ALTFUNCTION + + AF0 + Alternate Function 0 + 0 + + + AF1 + Alternate Function 1 + 1 + + + AF2 + Alternate Function 2 + 2 + + + AF3 + Alternate Function 3 + 3 + + + AF4 + Alternate Function 4 + 4 + + + AF5 + Alternate Function 5 + 5 + + + AF6 + Alternate Function 6 + 6 + + + AF7 + Alternate Function 7 + 7 + + + RESERVED + RESERVED + 8 + + + RESERVED + RESERVED + 9 + + + RESERVED + RESERVED + 10 + + + RESERVED + RESERVED + 11 + + + RESERVED + RESERVED + 12 + + + RESERVED + RESERVED + 13 + + + RESERVED + RESERVED + 14 + + + RESERVED + RESERVED + 15 + + + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + BRR + BRR + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port x Reset bit y + 0 + 1 + + RESET + write + + Reset + Resets the corresponding ODx bit + 1 + + + + + BR1 + Port x Reset bit y + 1 + 1 + + + + + BR2 + Port x Reset bit y + 2 + 1 + + + + + BR3 + Port x Reset bit y + 3 + 1 + + + + + BR4 + Port x Reset bit y + 4 + 1 + + + + + BR5 + Port x Reset bit y + 5 + 1 + + + + + BR6 + Port x Reset bit y + 6 + 1 + + + + + BR7 + Port x Reset bit y + 7 + 1 + + + + + BR8 + Port x Reset bit y + 8 + 1 + + + + + BR9 + Port x Reset bit y + 9 + 1 + + + + + BR10 + Port x Reset bit y + 10 + 1 + + + + + BR11 + Port x Reset bit y + 11 + 1 + + + + + BR12 + Port x Reset bit y + 12 + 1 + + + + + BR13 + Port x Reset bit y + 13 + 1 + + + + + BR14 + Port x Reset bit y + 14 + 1 + + + + + BR15 + Port x Reset bit y + 15 + 1 + + + + + + + + + GPIOD + 0x48000C00 + + + GPIOC + 0x48000800 + + + GPIOB + 0x48000400 + + + GPIOE + 0x48001000 + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x28000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + MODE + + Input + Input mode (reset state) + 0 + + + Output + General purpose output mode + 1 + + + Alternate + Alternate function mode + 2 + + + Analog + Analog mode + 3 + + + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + OUTPUTTYPE + + PushPull + Output push-pull (reset state) + 0 + + + OpenDrain + Output open-drain + 1 + + + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + OUTPUTSPEED + + LowSpeed + Low Speed + 0 + + + MediumSpeed + Medium Speed + 1 + + + HighSpeed + High Speed + 3 + + + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + PULLCONFIG + + NoPull + No pull-up, pull-down + 0 + + + PullUp + Pull-up + 1 + + + PullDown + Pull-down + 2 + + + Reserved + Reserved + 3 + + + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + OUTPUTVALUE + + Reset + Reset output value + 0 + + + Set + Set output value + 1 + + + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + RESET + write + + Reset + Resets the corresponding ODx bit + 1 + + + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + SET + write + + Set + Sets the corresponding ODRx bit + 1 + + + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + LOCKON + + Inactive + Port configuration lock key not active + 0 + + + Active + Port configuration lock key active + 1 + + + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + LOCK + + Unlock + Port configuration not locked + 0 + + + Lock + Port configuration locked + 1 + + + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + ALTFUNCTION + + AF0 + Alternate Function 0 + 0 + + + AF1 + Alternate Function 1 + 1 + + + AF2 + Alternate Function 2 + 2 + + + AF3 + Alternate Function 3 + 3 + + + AF4 + Alternate Function 4 + 4 + + + AF5 + Alternate Function 5 + 5 + + + AF6 + Alternate Function 6 + 6 + + + AF7 + Alternate Function 7 + 7 + + + RESERVED + RESERVED + 8 + + + RESERVED + RESERVED + 9 + + + RESERVED + RESERVED + 10 + + + RESERVED + RESERVED + 11 + + + RESERVED + RESERVED + 12 + + + RESERVED + RESERVED + 13 + + + RESERVED + RESERVED + 14 + + + RESERVED + RESERVED + 15 + + + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + ALTFUNCTION + + AF0 + Alternate Function 0 + 0 + + + AF1 + Alternate Function 1 + 1 + + + AF2 + Alternate Function 2 + 2 + + + AF3 + Alternate Function 3 + 3 + + + AF4 + Alternate Function 4 + 4 + + + AF5 + Alternate Function 5 + 5 + + + AF6 + Alternate Function 6 + 6 + + + AF7 + Alternate Function 7 + 7 + + + RESERVED + RESERVED + 8 + + + RESERVED + RESERVED + 9 + + + RESERVED + RESERVED + 10 + + + RESERVED + RESERVED + 11 + + + RESERVED + RESERVED + 12 + + + RESERVED + RESERVED + 13 + + + RESERVED + RESERVED + 14 + + + RESERVED + RESERVED + 15 + + + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + BRR + BRR + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port x Reset bit y + 0 + 1 + + RESET + write + + Reset + Resets the corresponding ODx bit + 1 + + + + + BR1 + Port x Reset bit y + 1 + 1 + + + + + BR2 + Port x Reset bit y + 2 + 1 + + + + + BR3 + Port x Reset bit y + 3 + 1 + + + + + BR4 + Port x Reset bit y + 4 + 1 + + + + + BR5 + Port x Reset bit y + 5 + 1 + + + + + BR6 + Port x Reset bit y + 6 + 1 + + + + + BR7 + Port x Reset bit y + 7 + 1 + + + + + BR8 + Port x Reset bit y + 8 + 1 + + + + + BR9 + Port x Reset bit y + 9 + 1 + + + + + BR10 + Port x Reset bit y + 10 + 1 + + + + + BR11 + Port x Reset bit y + 11 + 1 + + + + + BR12 + Port x Reset bit y + 12 + 1 + + + + + BR13 + Port x Reset bit y + 13 + 1 + + + + + BR14 + Port x Reset bit y + 14 + 1 + + + + + BR15 + Port x Reset bit y + 15 + 1 + + + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1_global_interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + 2line + 2-line unidirectional data mode selected + 0 + + + 1line + 1-line bidirectional data mode selected + 1 + + + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + disable + Output disabled (receive-only mode) + 0 + + + enable + Output enabled (transmit-only mode) + 1 + + + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + disable + CRC calculation disabled + 0 + + + enable + CRC calculation Enabled + 1 + + + + + CRCNEXT + CRC transfer next + 12 + 1 + + + Tx + Next transmit value is from Tx buffer + 0 + + + TxCRC + Next transmit value is from Tx CRC register + 1 + + + + + DFF + Data frame format + 11 + 1 + + + 8bits + 8-bit CRC length + 0 + + + 16bits + 16-bit CRC length + 1 + + + + + RXONLY + Receive only + 10 + 1 + + + FullDuplex + Full-duplex (Transmit and receive) + 0 + + + ReceiveOnly + Output disabled (Receive-only mode) + 1 + + + + + SSM + Software slave management + 9 + 1 + + + Disabled + Software slave management disabled + 0 + + + Enabled + Software slave management enabled + 1 + + + + + SSI + Internal slave select + 8 + 1 + + + NSSDisable + NSS = 1 + 0 + + + NSSEnable + NSS = 0 + 1 + + + + + LSBFIRST + Frame format + 7 + 1 + + + MSBFirst + data is transmitted / received with the MSB first + 0 + + + LSBFirst + data is transmitted / received with the LSB first + 1 + + + + + SPE + SPI enable + 6 + 1 + + + Disabled + Peripheral disabled + 0 + + + Enabled + Peripheral enabled + 1 + + + + + BR + Baud rate control + 3 + 3 + + + div2 + fPCLK/2 + 0 + + + div4 + fPCLK/4 + 1 + + + div8 + fPCLK/8 + 2 + + + div16 + fPCLK/16 + 3 + + + div32 + fPCLK/32 + 4 + + + div64 + fPCLK/64 + 5 + + + div128 + fPCLK/128 + 6 + + + div256 + fPCLK/256 + 7 + + + + + MSTR + Master selection + 2 + 1 + + + Slave + Slave Configuration + 0 + + + Master + Master Configuration + 1 + + + + + CPOL + Clock polarity + 1 + 1 + + + IdleLow + CK to 0 when idle + 0 + + + IdleHigh + CK to 1 when idle + 1 + + + + + CPHA + Clock phase + 0 + 1 + + + FirstEdge + The first clock transition is the first data capture edge + 0 + + + SecondEdge + The second clock transition is the first data capture edge + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + Disabled + Rx buffer DMA disabled + 0 + + + Enabled + Rx buffer DMA enabled + 1 + + + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + Disabled + Tx buffer DMA disabled + 0 + + + Enabled + Rx buffer DMA enabled + 1 + + + + + SSOE + SS output enable + 2 + 1 + + + Disabled + SS output is disabled in master mode and the SPI interface can work in multimaster +configuration + 0 + + + Enabled + SS output is enabled in master mode and when the SPI interface is enabled. The SPI +interface cannot work in a multimaster environment + 1 + + + + + NSSP + NSS pulse management + 3 + 1 + + + NoPulse + No NSS pulse + 0 + + + Pulse + NSS pulse generated + 1 + + + + + FRF + Frame format + 4 + 1 + + + SPI_Moto + SPI Motorola mode + 0 + + + SPI_TI + SPI TI mode + 1 + + + + + ERRIE + Error interrupt enable + 5 + 1 + + + Disabled + Error interrupt is masked + 0 + + + Enabled + Error interrupt is enabled + 1 + + + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + Disabled + RXNE interrupt masked + 0 + + + Enabled + RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 1 + + + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + Disabled + TXE interrupt masked + 0 + + + Enabled + TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 1 + + + + + DS + Data size + 8 + 4 + + + 4bits + 4-bits + 3 + + + 5bits + 5-bits + 4 + + + 6bits + 6-bits + 5 + + + 7bits + 7-bits + 6 + + + 8bits + 8-bits + 7 + + + 9bits + 9-bits + 8 + + + 10bits + 10-bits + 9 + + + 11bits + 11-bits + 10 + + + 12bits + 12-bits + 11 + + + 13bits + 13-bits + 12 + + + 14bits + 14-bits + 13 + + + 15bits + 15-bits + 14 + + + 16bits + 16-bits + 15 + + + + + FRXTH + FIFO reception threshold + 12 + 1 + + + 16bits + RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + 0 + + + 8bits + RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 1 + + + + + LDMA_RX + Last DMA transfer for + reception + 13 + 1 + + + Even + Number of data to receive is even + 0 + + + Odd + Number of data to receive is odd + 1 + + + + + LDMA_TX + Last DMA transfer for + transmission + 14 + 1 + + + Even + Number of data to transfer is even + 0 + + + Odd + Number of data to transfer is odd + 1 + + + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + UDR + Underrun flag + 3 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + Clear + Flag cleared + 0 + + + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + 0 + 65535 + + + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + 0 + 65535 + + + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + 0 + 65535 + + + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + SPI + SPI mode is selected + 0 + + + I2S + I2S mode is selected + 1 + + + + + I2SE + I2S Enable + 10 + 1 + + + DISABLE + I2S peripheral is disabled + 0 + + + ENABLE + I2S peripheral is enabled + 1 + + + + + I2SCFG + I2S configuration mode + 8 + 2 + + + Slave_transmit + Slave - transmit + 0 + + + Slave_receive + Slave - receive + 1 + + + Master_transmit + Master - transmit + 2 + + + Master_receive + Master - receive + 3 + + + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + Short + Short frame synchronization + 0 + + + Long + Long frame synchronization + 1 + + + + + I2SSTD + I2S standard selection + 4 + 2 + + + I2S + I2S Philips standard. + 0 + + + MSB + MSB justified standard (left justified) + 1 + + + LSB + LSB justified standard (right justified) + 2 + + + PCM + PCM standard + 3 + + + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + IdleLow + I2S clock inactive state is low level + 0 + + + IdleHigh + I2S clock inactive state is high level + 1 + + + + + DATLEN + Data length to be + transferred + 1 + 2 + + + 16bits + 16-bit data length + 0 + + + 24bits + 24-bit data length + 1 + + + 32bits + 32-bit data length + 2 + + + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + 16bits + 16-bit wide + 0 + + + 32bits + 32-bit wide + 1 + + + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 0x00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + Disabled + Master clock output is disabled + 0 + + + Enabled + Master clock output is enabled + 1 + + + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + Even + Real divider value is = I2SDIV *2 + 0 + + + Odd + Real divider value is = (I2SDIV * 2)+1 + 1 + + + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + 1 + 254 + + + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt and DAC underrun + interrupt + 17 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + Disabled + DAC channel1 disabled + 0 + + + Enabled + DAC channel1 enabled + 1 + + + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + Disabled + DAC channel1 output buffer enabled + 0 + + + Enabled + DAC channel1 output buffer disabled + 1 + + + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + Disabled + DAC channel1 trigger disabled and data written into the DAC_DHRx register are +transferred one APB clock cycle later to the DAC_DOR1 register + 0 + + + Enabled + DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB clock cycles later to the DAC_DOR1 register + 1 + + + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + EVENTTRIG + + Timer6Trig + Timer 6 TRGO event + 0 + + + Timer3Trig + Timer 3 TRGO event + 1 + + + Timer7Trig + Timer 7 TRGO event + 2 + + + Timer15Trig + Timer 15 TRGO event + 3 + + + Timer2Trig + Timer 2 TRGO event + 4 + + + Reserved + Reserved + 5 + + + EXTI9_Trig + EXTI line9 + 6 + + + Soft + Software trigger + 7 + + + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right-aligned data + holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left-aligned data + holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DHR12RD + DHR12RD + DHR12RD + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + Dual DAC 12-bit left-aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + Dual DAC 8-bit right-aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + 0 + 255 + + + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + 0 + 255 + + + + + + + DOR2 + DOR2 + DAC channel2 data output + register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + PLS + PVD level selection + 5 + 3 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + LPDS + Low-power deep sleep + 0 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + VREFINTRDY + VREFINT reference voltage + ready + 3 + 1 + read-only + + + EWUP1 + Enable WKUP pin 1 + 8 + 1 + read-write + + + EWUP2 + Enable WKUP pin 2 + 9 + 1 + read-write + + + EWUP3 + Enable WKUP pin 3 + 10 + 1 + read-write + + + EWUP4 + Enable WKUP pin 4 + 11 + 1 + read-write + + + EWUP5 + Enable WKUP pin 5 + 12 + 1 + read-write + + + EWUP6 + Enable WKUP pin 6 + 13 + 1 + read-write + + + EWUP7 + Enable WKUP pin 7 + 14 + 1 + read-write + + + EWUP8 + Enable WKUP pin 8 + 15 + 1 + read-write + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + read-write + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + read-write + + + ERRIE + Error interrupts enable + 7 + 1 + read-write + + + DNF + Digital noise filter + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF + 12 + 1 + read-write + + + SWRST + Software reset + 13 + 1 + write-only + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + + RXDMAEN + + Disabled + Rx buffer DMA disabled + 0 + + + Enabled + Rx buffer DMA enabled + 1 + + + read-write + + + SBC + Slave byte control + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable + 17 + 1 + read-write + + + WUPEN + Wakeup from STOP enable + 18 + 1 + read-write + + + GCEN + General call enable + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + read-write + + + ALERTEN + SMBUS alert enable + 22 + 1 + read-write + + + PECEN + PEC enable + 23 + 1 + read-write + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + 0 + 255 + + + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD8 + Slave address bit 9:8 (master + mode) + 8 + 2 + + + SADD1 + Slave address bit 7:1 (master + mode) + 1 + 7 + + + SADD0 + Slave address bit 0 (master + mode) + 0 + 1 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1_0 + Interface address + 0 + 1 + + + OA1_1 + Interface address + 1 + 7 + + + OA1_8 + Interface address + 8 + 2 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + 0 + 255 + + + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + 0 + 255 + + + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + 0 + 255 + + + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + 0 + 255 + + + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + 0 + 255 + + + + + + + + + I2C2 + 0x40005800 + + I2C2 + I2C2 global interrupt + 24 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + 0 + 65535 + + + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB + Timer base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 break, update, trigger and commutation + interrupt + 13 + + + TIM1_CC + TIM1 Capture Compare interrupt + 14 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Division ratio between the timer clock (CK_INT) frequency and sampling clock + 8 + 2 + + CKD + + Div1 + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + + EdgeAlign + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0 + + + CenterAlignMode1 + Center-aligned mode 1. + 1 + + + CenterAlignMode2 + Center-aligned mode 2. + 2 + + + CenterAlignMode3 + Center-aligned mode 3. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + Reset + OC4=0 when MOE=0 + 0 + + + Set + OC4=1 when MOE=0 + 1 + + + + + OIS3N + Output Idle state 3 + 13 + 1 + + + Reset + OC3N=0 after a dead-time when MOE=0 + 0 + + + Set + OC3N=1 after a dead-time when MOE=0 + 1 + + + + + OIS3 + Output Idle state 3 + 12 + 1 + + + Reset + OC3=0 when MOE=0 + 0 + + + Set + OC3=1 when MOE=0 + 1 + + + + + OIS2N + Output Idle state 2 + 11 + 1 + + + Reset + OC2N=0 after a dead-time when MOE=0 + 0 + + + Set + OC2N=1 after a dead-time when MOE=0 + 1 + + + + + OIS2 + Output Idle state 2 + 10 + 1 + + + Reset + OC2=0 when MOE=0 + 0 + + + Set + OC2=1 when MOE=0 + 1 + + + + + OIS1N + Output Idle state 1 + 9 + 1 + + + Reset + OC1N=0 after a dead-time when MOE=0 + 0 + + + Set + OC1N=1 after a dead-time when MOE=0 + 1 + + + + + OIS1 + Output Idle state 1 + 8 + 1 + + + Reset + OC1=0 when MOE=0 + 0 + + + Set + OC1=1 when MOE=0 + 1 + + + + + TI1S + TI1 selection + 7 + 1 + + + TI1Input + The TIMx CH1 pin is connected to TI1 input + 0 + + + AllTI1Input + The TIMx CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 1 + + + + + MMS + Master mode selection + 4 + 3 + + + Reset + the UG bit from the TIMx_EGR register is used as trigger output (TRGO). + 0 + + + Enable + the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 1 + + + Update + The update event is selected as trigger output (TRGO). + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag is to be set. + 3 + + + CompareOC1REF + OC1REF signal is used as trigger output (TRGO) + 4 + + + CompareOC2REF + OC2REF signal is used as trigger output (TRGO) + 5 + + + CompareOC3REF + OC3REF signal is used as trigger output (TRGO) + 6 + + + CompareOC4REF + OC4REF signal is used as trigger output (TRGO) + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCxEvent + CCx DMA request sent when CCx event occurs + 0 + + + Update + CCx DMA requests sent when update event occurs + 1 + + + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + COMGBitOnly + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0 + + + COMGBit_Edge + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 1 + + + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + NotPreloaded + CCxE, CCxNE and OCxM bits are not preloaded + 0 + + + Preloaded + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a communication event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + NonInverted + ETR is non-inverted, active at high level or rising edge. + 0 + + + Inverted + ETR is inverted, active at low level or falling edge. + 1 + + + + + ECE + External clock enable + 14 + 1 + + + Disabled + External clock mode 2 disabled. + 0 + + + Enabled + External clock mode 2 enabled.. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + + Off + Prescaler OFF. + 0 + + + ETRPdiv2 + ETRP frequency divided by 2. + 1 + + + ETRPdiv4 + ETRP frequency divided by 4. + 2 + + + ETRPdiv8 + ETRP frequency divided by 8. + 3 + + + + + ETF + External trigger filter + 8 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + + NoAction + No action + 0 + + + Synchronization + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + ITR3 + Internal Trigger 3 (ITR3) + 3 + + + TI1F_ED + TI1 Edge Detector + 4 + + + TI1FP1 + Filtered Timer Input 1 + 5 + + + TI2FP2 + Filtered Timer Input 2 + 6 + + + (ETRF) + External Trigger input + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + + Disabled + Counter disabled + 0 + + + EncoderTI2 + Encoder mode, count up/down on TI2FP1 + 1 + + + EncoderTI1 + Encoder mode, count up/down on TI1FP2 + 2 + + + EncoderTI1TI2 + Encoder mode, count up/down on both TI1FP1 and TI2FP2 + 3 + + + Reset + Rising edge of the selected trigger input (TRGI) reinitializes the counter + 4 + + + Gated + The counter clock is enabled when the trigger input (TRGI) is high + 5 + + + Trigger + The counter starts at a rising edge of the trigger TRGI + 6 + + + External + Rising edges of the selected trigger (TRGI) clock the counter + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + DISABLED + Trigger DMA request disabled. + 0 + + + ENABLED + Trigger DMA request enabled. + 1 + + + + + COMDE + COM DMA request enable + 13 + 1 + + + DISABLED + COM DMA request disabled. + 0 + + + ENABLED + COM DMA request enabled. + 1 + + + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + DISABLED + CC4 DMA request disabled. + 0 + + + ENABLED + CC4 DMA request enabled. + 1 + + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + DISABLED + CC3 DMA request disabled. + 0 + + + ENABLED + CC3 DMA request enabled. + 1 + + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + DISABLED + CC2 DMA request disabled. + 0 + + + ENABLED + CC2 DMA request enabled. + 1 + + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + DISABLED + CC1 DMA request disabled. + 0 + + + ENABLED + CC1 DMA request enabled. + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + + DISABLED + Update DMA request disabled. + 0 + + + ENABLED + Update DMA request enabled. + 1 + + + + + BIE + Break interrupt enable + 7 + 1 + + + DISABLED + Break interrupt disabled. + 0 + + + ENABLED + Break interrupt enabled. + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + + DISABLED + Trigger interrupt disabled. + 0 + + + ENABLED + Trigger interrupt enabled. + 1 + + + + + COMIE + COM interrupt enable + 5 + 1 + + + DISABLED + COM interrupt disabled. + 0 + + + ENABLED + COM interrupt enabled. + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + DISABLED + CC4 interrupt disabled. + 0 + + + ENABLED + CC4 interrupt enabled. + 1 + + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + DISABLED + CC3 interrupt disabled. + 0 + + + ENABLED + CC3 interrupt enabled. + 1 + + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + DISABLED + CC2 interrupt disabled. + 0 + + + ENABLED + CC2 interrupt enabled. + 1 + + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + DISABLED + CC1 interrupt disabled. + 0 + + + ENABLED + CC1 interrupt enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + BIF + Break interrupt flag + 7 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + COMIF + COM interrupt flag + 5 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + NoAction + No action. + 0 + + + BreakEvent + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + TG + Trigger generation + 6 + 1 + + + TIFset + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CCupdate + When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits. + 1 + + + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + Generated + generate an event. + 1 + + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + Generated + generate an event. + 1 + + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + Generated + generate an event. + 1 + + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + Generated + generate an event. + 1 + + + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + DISABLED + OC2Ref is not affected by the ETRF Input. + 0 + + + ENABLED + OC2Ref is cleared as soon as a High level is detected on ETRF input. + 1 + + + + + OC2M + Output Compare 2 mode + 12 + 3 + + + Frozen + Frozen + 0 + + + CH2ActiveOnMatch + Set channel 2 to active level on match. OC2REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2). + 1 + + + CH2InactiveOnMatch + Set channel 2 to inactive level on match. + 2 + + + Toggle + Toggle - OC2REF toggles when TIMx_CNT=TIMx_CCR2. + 3 + + + ForcedLow + Force inactive level - OC2REF is forced low. + 4 + + + ForcedHigh + Force active level - OC2REF is forced high. + 5 + + + PWMMode1 + PWM Mode 1 + 6 + + + PWMMode2 + PWM Mode 2 + 7 + + + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + Disabled + Preload register on TIMx_CCR2 disabled. TIMx_CCR2 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR2 enabled. Read/Write operations access the preload register. TIMx_CCR2 preload value is loaded in the active register at each update event. + 1 + + + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + Disabled + CC2 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC2 output when an edge occurs on the trigger input is 5 clock cycles + 0 + + + Enabled + An active edge on the trigger input acts like a compare match on CC2 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC2 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + DISABLED + OC1Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC1Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs( + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWMMode1 + In upcounting, channel 1 is active. + 6 + + + PWMMode2 + In upcounting, channel y is inactive. + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 1 + + + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + DISABLED + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + 1Event + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2Events + capture is done once every 2 events + 1 + + + 4Events + capture is done once every 4 events + 2 + + + 8Events + capture is done once every 8 events + 3 + + + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC1PCS + Input capture 1 prescaler + 2 + 2 + + + 1Event + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2Events + capture is done once every 2 events + 1 + + + 4Events + capture is done once every 4 events + 2 + + + 8Events + capture is done once every 8 events + 3 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + DISABLED + OC4Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC4Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC4M + Output compare 4 mode + 12 + 3 + + + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + Disabled + Preload register on TIMx_CCR4 disabled. TIMx_CCR4 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR4 enabled. Read/Write operations access the preload register. TIMx_CCR4 preload value is loaded in the active register at each update event. + 1 + + + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + DISABLED + CC4 behaves normally depending on counter and CCR4 values even when the trigger is ON. The minimum delay to activate CC4 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC4 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC3 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + CC4output + CC4 channel is configured as output + 0 + + + IC4mappedTI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + IC4mappedTI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + IC4mappedTRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + DISABLED + OC3Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC3Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC3M + Output compare 3 mode + 4 + 3 + + + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR3 disabled. TIMx_CCR3 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR3 enabled. Read/Write operations access the preload register. TIMx_CCR3 preload value is loaded in the active register at each update event. + 1 + + + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + DISABLED + CC3 behaves normally depending on counter and CCR3 values even when the trigger is ON. The minimum delay to activate CC3 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC3 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC3 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + CC3output + CC3 channel is configured as output + 0 + + + IC3mappedTI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + IC3mappedTI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + IC3mappedTRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + CC4output + CC4 channel is configured as output + 0 + + + IC4mappedTI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + IC4mappedTI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + IC4mappedTRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + CC3output + CC3 channel is configured as output + 0 + + + IC3mappedTI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + IC3mappedTI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + IC3mappedTRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + DISABLED + Off + 0 + + + ENABLED + On + 1 + + + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + DISABLED + Off + 0 + + + ENABLED + On + 1 + + + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + DISABLED + Off + 0 + + + ENABLED + On + 1 + + + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + 0 + 255 + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare 3 value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare 3 value + 0 + 16 + + + 0 + 65535 + + + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + DISABLED + OC and OCN outputs are disabled or forced to idle state + 0 + + + ENABLED + OC and OCN outputs are enabled if their respective enable bits are set + 1 + + + + + AOE + Automatic output enable + 14 + 1 + + + DISABLED + MOE can be set only by software + 0 + + + ENABLED + MOE can be set by software or automatically at the next update event + 1 + + + + + BKP + Break polarity + 13 + 1 + + + ActiveLow + Break input BRK is active low + 0 + + + ActiveHigh + Break input BRK is active high + 1 + + + + + BKE + Break enable + 12 + 1 + + + Disabled + Break inputs (BRK and CCS clock failure event) disabled + 0 + + + Enabled + Break inputs (BRK and CCS clock failure event) enabled + 1 + + + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are enabled + 1 + + + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1 + 1 + + + + + LOCK + Lock configuration + 8 + 2 + + + LockOff + LOCK OFF - No bit is write protected. + 0 + + + LockLvl1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 1 + + + LockLvl2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 2 + + + LockLvl3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 3 + + + + + DTG + Dead-time generator setup + 0 + 8 + + + 0 + 255 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + 1transfert + 1 transfert. + 0 + + + 2transferts + 2 transferts. + 1 + + + 3transferts + 3 transferts. + 2 + + + 4transferts + 4 transferts. + 3 + + + 5transferts + 5 transferts. + 4 + + + 6transferts + 6 transferts. + 5 + + + 7transferts + 7 transferts. + 6 + + + 8transferts + 8 transferts. + 7 + + + 9transferts + 9 transferts. + 8 + + + 10transferts + 10 transferts. + 9 + + + 11transferts + 11 transferts. + 10 + + + 12transferts + 12 transferts. + 11 + + + 13transferts + 13 transferts. + 12 + + + 14transferts + 14 transferts. + 13 + + + 15transferts + 15 transferts. + 14 + + + 16transferts + 16 transferts. + 15 + + + 17transferts + 17 transferts. + 16 + + + 18transferts + 18 transferts. + 17 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 15 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Division ratio between the timer clock (CK_INT) frequency and sampling clock + 8 + 2 + + CKD + + Div1 + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + CMS + Center-aligned mode + selection + 5 + 2 + + + EdgeAlign + Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). + 0 + + + CenterAlignMode1 + Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. + 1 + + + CenterAlignMode2 + Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. + 2 + + + CenterAlignMode3 + Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. + 3 + + + + + DIR + Direction + 4 + 1 + + DIR + + Up + Counter used as upcounter + 0 + + + Down + Counter used as downcounter + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow/underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + TI1Input + The TIMx_CH1 pin is connected to TI1 input + 0 + + + AllTI1Input + The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 1 + + + + + MMS + Master mode selection + 4 + 3 + + + Reset + the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0 + + + Enable + the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 1 + + + Update + The update event is selected as trigger output (TRGO). + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.(TRGO). + 3 + + + CompareOC1REF + OC1REF signal is used as trigger output (TRGO) + 4 + + + CompareOC2REF + OC2REF signal is used as trigger output (TRGO) + 5 + + + CompareOC3REF + OC3REF signal is used as trigger output (TRGO) + 6 + + + CompareOC4REF + OC4REF signal is used as trigger output (TRGO) + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCxEvent + CCx DMA request sent when CCx event occurs + 0 + + + Update + CCx DMA requests sent when update event occurs + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + NonInverted + ETR is non-inverted, active at high level or rising edge. + 0 + + + Inverted + ETR is inverted, active at low level or falling edge. + 1 + + + + + ECE + External clock enable + 14 + 1 + + + Disabled + External clock mode 2 disabled. + 0 + + + Enabled + External clock mode 2 enabled.. + 1 + + + + + ETPS + External trigger prescaler + 12 + 2 + + + Off + Prescaler OFF. + 0 + + + ETRPdiv2 + ETRP frequency divided by 2. + 1 + + + ETRPdiv4 + ETRP frequency divided by 4. + 2 + + + ETRPdiv8 + ETRP frequency divided by 8. + 3 + + + + + ETF + External trigger filter + 8 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + MSM + Master/Slave mode + 7 + 1 + + + NoAction + No action + 0 + + + Synchronization + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + ITR3 + Internal Trigger 3 (ITR3) + 3 + + + TI1F_ED + TI1 Edge Detector + 4 + + + TI1FP1 + Filtered Timer Input 1 + 5 + + + TI2FP2 + Filtered Timer Input 2 + 6 + + + (ETRF) + External Trigger input + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + + Disabled + Counter disabled + 0 + + + EncoderTI2 + Encoder mode, count up/down on TI2FP1 + 1 + + + EncoderTI1 + Encoder mode, count up/down on TI1FP2 + 2 + + + EncoderTI1TI2 + Encoder mode, count up/down on both TI1FP1 and TI2FP2 + 3 + + + Reset + Rising edge of the selected trigger input (TRGI) reinitializes the counter + 4 + + + Gated + The counter clock is enabled when the trigger input (TRGI) is high + 5 + + + Trigger + The counter starts at a rising edge of the trigger TRGI + 6 + + + External + Rising edges of the selected trigger (TRGI) clock the counter + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + DISABLED + Trigger DMA request disabled. + 0 + + + ENABLED + Trigger DMA request enabled. + 1 + + + + + COMDE + COM DMA request enable + 13 + 1 + + + DISABLED + COM DMA request disabled. + 0 + + + ENABLED + COM DMA request enabled. + 1 + + + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + DISABLED + CC4 DMA request disabled. + 0 + + + ENABLED + CC4 DMA request enabled. + 1 + + + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + DISABLED + CC3 DMA request disabled. + 0 + + + ENABLED + CC3 DMA request enabled. + 1 + + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + DISABLED + CC2 DMA request disabled. + 0 + + + ENABLED + CC2 DMA request enabled. + 1 + + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + DISABLED + CC1 DMA request disabled. + 0 + + + ENABLED + CC1 DMA request enabled. + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + + DISABLED + Update DMA request disabled. + 0 + + + ENABLED + Update DMA request enabled. + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + + DISABLED + Trigger interrupt disabled. + 0 + + + ENABLED + Trigger interrupt enabled. + 1 + + + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + DISABLED + CC4 interrupt disabled. + 0 + + + ENABLED + CC4 interrupt enabled. + 1 + + + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + DISABLED + CC3 interrupt disabled. + 0 + + + ENABLED + CC3 interrupt enabled. + 1 + + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + DISABLED + CC2 interrupt disabled. + 0 + + + ENABLED + CC2 interrupt enabled. + 1 + + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + DISABLED + CC1 interrupt disabled. + 0 + + + ENABLED + CC1 interrupt enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + TIFset + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + Generated + generate an event. + 1 + + + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + Generated + generate an event. + 1 + + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + Generated + generate an event. + 1 + + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + Generated + generate an event. + 1 + + + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + DISABLED + OC2Ref is not affected by the ETRF Input. + 0 + + + ENABLED + OC2Ref is cleared as soon as a High level is detected on ETRF input. + 1 + + + + + OC2M + Output compare 2 mode + 12 + 3 + + + Frozen + Frozen + 0 + + + CH2ActiveOnMatch + Set channel 2 to active level on match. OC2REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2). + 1 + + + CH2InactiveOnMatch + Set channel 2 to inactive level on match. + 2 + + + Toggle + Toggle - OC2REF toggles when TIMx_CNT=TIMx_CCR2. + 3 + + + ForcedLow + Force inactive level - OC2REF is forced low. + 4 + + + ForcedHigh + Force active level - OC2REF is forced high. + 5 + + + PWMMode1 + PWM Mode 1 + 6 + + + PWMMode2 + PWM Mode 2 + 7 + + + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + Disabled + Preload register on TIMx_CCR2 disabled. TIMx_CCR2 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR2 enabled. Read/Write operations access the preload register. TIMx_CCR2 preload value is loaded in the active register at each update event. + 1 + + + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + Disabled + CC2 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC2 output when an edge occurs on the trigger input is 5 clock cycles + 0 + + + Enabled + An active edge on the trigger input acts like a compare match on CC2 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC2 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + DISABLED + OC1Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC1Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC1M + Output compare 1 mode + 4 + 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs( + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWMMode1 + In upcounting, channel 1 is active. + 6 + + + PWMMode2 + In upcounting, channel y is inactive. + 7 + + + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 1 + + + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + DISABLED + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + DISABLED + OC4Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC4Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC4M + Output compare 4 mode + 12 + 3 + + + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + Disabled + Preload register on TIMx_CCR4 disabled. TIMx_CCR4 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR4 enabled. Read/Write operations access the preload register. TIMx_CCR4 preload value is loaded in the active register at each update event. + 1 + + + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + DISABLED + CC4 behaves normally depending on counter and CCR4 values even when the trigger is ON. The minimum delay to activate CC4 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC4 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC3 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + CC4output + CC4 channel is configured as output + 0 + + + IC4mappedTI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + IC4mappedTI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + IC4mappedTRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + DISABLED + OC3Ref is not affected by the ETRF Input + 0 + + + ENABLED + OC3Ref is cleared as soon as a High level is detected on ETRF input + 1 + + + + + OC3M + Output compare 3 mode + 4 + 3 + + + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR3 disabled. TIMx_CCR3 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR3 enabled. Read/Write operations access the preload register. TIMx_CCR3 preload value is loaded in the active register at each update event. + 1 + + + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + DISABLED + CC3 behaves normally depending on counter and CCR3 values even when the trigger is ON. The minimum delay to activate CC3 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC3 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC3 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + CC3output + CC3 channel is configured as output + 0 + + + IC3mappedTI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + IC3mappedTI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + IC3mappedTRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + CC4output + CC4 channel is configured as output + 0 + + + IC4mappedTI4 + CC4 channel is configured as input, IC4 is mapped on TI4 + 1 + + + IC4mappedTI3 + CC4 channel is configured as input, IC4 is mapped on TI3 + 2 + + + IC4mappedTRC + CC4 channel is configured as input, IC4 is mapped on TRC + 3 + + + + + IC3F + Input capture 3 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + CC3output + CC3 channel is configured as output + 0 + + + IC3mappedTI3 + CC3 channel is configured as input, IC3 is mapped on TI3 + 1 + + + IC3mappedTI4 + CC3 channel is configured as input, IC3 is mapped on TI4 + 2 + + + IC3mappedTRC + CC3 channel is configured as input, IC3 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + CNT_L + Low counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + ARR_L + Low Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + 0 + 65535 + + + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + 0 + 65535 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + 1transfert + 1 transfert. + 0 + + + 2transferts + 2 transferts. + 1 + + + 3transferts + 3 transferts. + 2 + + + 4transferts + 4 transferts. + 3 + + + 5transferts + 5 transferts. + 4 + + + 6transferts + 6 transferts. + 5 + + + 7transferts + 7 transferts. + 6 + + + 8transferts + 8 transferts. + 7 + + + 9transferts + 9 transferts. + 8 + + + 10transferts + 10 transferts. + 9 + + + 11transferts + 11 transferts. + 10 + + + 12transferts + 12 transferts. + 11 + + + 13transferts + 13 transferts. + 12 + + + 14transferts + 14 transferts. + 13 + + + 15transferts + 15 transferts. + 14 + + + 16transferts + 16 transferts. + 15 + + + 17transferts + 17 transferts. + 16 + + + 18transferts + 18 transferts. + 17 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAR + DMA register for burst + accesses + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 16 + + + + TIM14 + General-purpose-timers + TIM + 0x40002000 + + 0x0 + 0x400 + registers + + + TIM14 + TIM14 global interrupt + 19 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Division ratio between the timer clock (CK_INT) frequency and sampling clock + 8 + 2 + + CKD + + Div1 + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow/underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + DISABLED + CC1 interrupt disabled. + 0 + + + ENABLED + CC1 interrupt enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + Generated + generate an event. + 1 + + + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + DISABLED + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 1 + + + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs( + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWMMode1 + In upcounting, channel 1 is active. + 6 + + + PWMMode2 + In upcounting, channel y is inactive. + 7 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + 0 + 65535 + + + + + + + OR + OR + option register + 0x50 + 0x20 + read-write + 0x00000000 + + + RMP + Timer input 1 remap + 0 + 2 + + + + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow/underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + Reset + the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0 + + + Enable + the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 1 + + + Update + The update event is selected as trigger output (TRGO). + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.(TRGO). + 3 + + + CompareOC1REF + OC1REF signal is used as trigger output (TRGO) + 4 + + + CompareOC2REF + OC2REF signal is used as trigger output (TRGO) + 5 + + + CompareOC3REF + OC3REF signal is used as trigger output (TRGO) + 6 + + + CompareOC4REF + OC4REF signal is used as trigger output (TRGO) + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + DISABLED + Update DMA request disabled. + 0 + + + ENABLED + Update DMA request enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 18 + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD + PVD and VDDIO2 supply comparator + interrupt + 1 + + + EXTI0_1 + EXTI Line[1:0] interrupts + 5 + + + EXTI2_3 + EXTI Line[3:2] interrupts + 6 + + + EXTI4_15 + EXTI Line15 and EXTI4 interrupts + 7 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x0F940000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + MR23 + Interrupt Mask on line 23 + 23 + 1 + + + MR24 + Interrupt Mask on line 24 + 24 + 1 + + + MR25 + Interrupt Mask on line 25 + 25 + 1 + + + MR26 + Interrupt Mask on line 26 + 26 + 1 + + + MR27 + Interrupt Mask on line 27 + 27 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + MR23 + Event Mask on line 23 + 23 + 1 + + + MR24 + Event Mask on line 24 + 24 + 1 + + + MR25 + Event Mask on line 25 + 25 + 1 + + + MR26 + Event Mask on line 26 + 26 + 1 + + + MR27 + Event Mask on line 27 + 27 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF31 + Pending interrupt flag on line + 31 + 31 + 1 + + + PIF22 + Pending interrupt flag on line + 22 + 22 + 1 + + + PIF21 + Pending interrupt flag on line + 21 + 21 + 1 + + + PIF20 + Pending interrupt flag on line + 20 + 20 + 1 + + + PIF19 + Pending interrupt flag on line + 19 + 19 + 1 + + + PIF17 + Pending interrupt flag on line + 17 + 17 + 1 + + + PIF16 + Pending interrupt flag on line + 16 + 16 + 1 + + + PIF15 + Pending interrupt flag on line + 15 + 15 + 1 + + + PIF14 + Pending interrupt flag on line + 14 + 14 + 1 + + + PIF13 + Pending interrupt flag on line + 13 + 13 + 1 + + + PIF12 + Pending interrupt flag on line + 12 + 12 + 1 + + + PIF11 + Pending interrupt flag on line + 11 + 11 + 1 + + + PIF10 + Pending interrupt flag on line + 10 + 10 + 1 + + + PIF9 + Pending interrupt flag on line + 9 + 9 + 1 + + + PIF8 + Pending interrupt flag on line + 8 + 8 + 1 + + + PIF7 + Pending interrupt flag on line + 7 + 7 + 1 + + + PIF6 + Pending interrupt flag on line + 6 + 6 + 1 + + + PIF5 + Pending interrupt flag on line + 5 + 5 + 1 + + + PIF4 + Pending interrupt flag on line + 4 + 4 + 1 + + + PIF3 + Pending interrupt flag on line + 3 + 3 + 1 + + + PIF2 + Pending interrupt flag on line + 2 + 2 + 1 + + + PIF1 + Pending interrupt flag on line + 1 + 1 + 1 + + + PIF0 + Pending interrupt flag on line + 0 + 0 + 1 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x33D + registers + + + + ISER + ISER + Interrupt Set Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + 0 + 4294967295 + + + + + + + ICER + ICER + Interrupt Clear Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + 0 + 4294967295 + + + + + + + ISPR + ISPR + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + 0 + 4294967295 + + + + + + + ICPR + ICPR + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + 0 + 4294967295 + + + + + + + IPR0 + IPR0 + Interrupt Priority Register 0 + 0x300 + 0x20 + read-write + 0x00000000 + + + PRI_00 + PRI_00 + 6 + 2 + + + PRI_01 + PRI_01 + 14 + 2 + + + PRI_02 + PRI_02 + 22 + 2 + + + PRI_03 + PRI_03 + 30 + 2 + + + + + IPR1 + IPR1 + Interrupt Priority Register 1 + 0x304 + 0x20 + read-write + 0x00000000 + + + PRI_40 + PRI_40 + 6 + 2 + + + PRI_41 + PRI_41 + 14 + 2 + + + PRI_42 + PRI_42 + 22 + 2 + + + PRI_43 + PRI_43 + 30 + 2 + + + + + IPR2 + IPR2 + Interrupt Priority Register 2 + 0x308 + 0x20 + read-write + 0x00000000 + + + PRI_80 + PRI_80 + 6 + 2 + + + PRI_81 + PRI_81 + 14 + 2 + + + PRI_82 + PRI_82 + 22 + 2 + + + PRI_83 + PRI_83 + 30 + 2 + + + + + IPR3 + IPR3 + Interrupt Priority Register 3 + 0x30C + 0x20 + read-write + 0x00000000 + + + PRI_120 + PRI_120 + 6 + 2 + + + PRI_121 + PRI_121 + 14 + 2 + + + PRI_122 + PRI_122 + 22 + 2 + + + PRI_123 + PRI_123 + 30 + 2 + + + + + IPR4 + IPR4 + Interrupt Priority Register 4 + 0x310 + 0x20 + read-write + 0x00000000 + + + PRI_160 + PRI_160 + 6 + 2 + + + PRI_161 + PRI_161 + 14 + 2 + + + PRI_162 + PRI_162 + 22 + 2 + + + PRI_163 + PRI_163 + 30 + 2 + + + + + IPR5 + IPR5 + Interrupt Priority Register 5 + 0x314 + 0x20 + read-write + 0x00000000 + + + PRI_200 + PRI_200 + 6 + 2 + + + PRI_201 + PRI_201 + 14 + 2 + + + PRI_202 + PRI_202 + 22 + 2 + + + PRI_203 + PRI_203 + 30 + 2 + + + + + IPR6 + IPR6 + Interrupt Priority Register 6 + 0x318 + 0x20 + read-write + 0x00000000 + + + PRI_240 + PRI_240 + 6 + 2 + + + PRI_241 + PRI_241 + 14 + 2 + + + PRI_242 + PRI_242 + 22 + 2 + + + PRI_243 + PRI_243 + 30 + 2 + + + + + IPR7 + IPR7 + Interrupt Priority Register 7 + 0x31C + 0x20 + read-write + 0x00000000 + + + PRI_280 + PRI_280 + 6 + 2 + + + PRI_281 + PRI_281 + 14 + 2 + + + PRI_282 + PRI_282 + 22 + 2 + + + PRI_283 + PRI_283 + 30 + 2 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 9 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR4 + CCR4 + DMA channel configuration register + (DMA_CCR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR4 + CPAR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR4 + CMAR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR5 + CCR5 + DMA channel configuration register + (DMA_CCR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR5 + CPAR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR5 + CMAR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR6 + CCR6 + DMA channel configuration register + (DMA_CCR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR6 + CPAR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR6 + CMAR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CCR7 + CCR7 + DMA channel configuration register + (DMA_CCR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + 0 + 65535 + + + + + + + CPAR7 + CPAR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + 0 + 4294967295 + + + + + + + CMAR7 + CMAR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC_CRS + RCC and CRS global interrupts + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + Disabled + HSI oscillator OFF + 0 + + + Enabled + HSI oscillator ON + 1 + + + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + 0 + 31 + + + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + Disabled + HSE oscillator OFF + 0 + + + Enabled + HSE oscillator ON + 1 + + + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + NotBypassed + HSE crystal oscillator not bypassed + 0 + + + Bypassed + HSE crystal oscillator bypassed with external clock + 1 + + + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + Disabled + Clock security system disabled (clock detector OFF). + 0 + + + Enabled + Clock security system enabled (clock detector ON if the HSE is ready, OFF if not). + 1 + + + + + PLLON + PLL enable + 24 + 1 + read-write + + + Disabled + PLL Off. + 0 + + + Enabled + PLL On. + 1 + + + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + + + CFGR + CFGR + Clock configuration register + (RCC_CFGR) + 0x4 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + HSI + HSI selected as system clock + 0 + + + HSE + HSE selected as system clock + 1 + + + PLL + PLL selected as system clock + 2 + + + HSI48 + HSI48 selected as system clock (when available) + 3 + + + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + Div1 + SYSCLK not divided + 0 + + + Div2 + SYSCLK divided by 2 + 8 + + + Div4 + SYSCLK divided by 4 + 9 + + + Div8 + SYSCLK divided by 8 + 10 + + + Div16 + SYSCLK divided by 16 + 11 + + + Div64 + SYSCLK divided by 64 + 12 + + + Div128 + SYSCLK divided by 128 + 13 + + + Div256 + SYSCLK divided by 256 + 14 + + + Div512 + SYSCLK divided by 512 + 15 + + + + + PPRE + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + Div1 + HCLK not divided + 0 + + + Div2 + HCLK divided by 2 + 4 + + + Div4 + HCLK divided by 4 + 5 + + + Div8 + HCLK divided by 8 + 6 + + + Div16 + HCLK divided by 16 + 7 + + + + + ADCPRE + ADC prescaler + 14 + 1 + read-write + + + PLLSRC + PLL input clock source + 15 + 2 + read-write + + + HSIDiv2 + HSI/2 selected as PLL input clock (PREDIV forced to divide by 2 on STM32F04x, STM32F07x and STM32F09x devices) + 0 + + + HSI + HSI/PREDIV selected as PLL input clock + 1 + + + HSE + HSE/PREDIV selected as PLL input clock + 2 + + + HSI48 + HSI48/PREDIV selected as PLL input clock + 3 + + + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + Div1 + HSE not divided + 0 + + + Div2 + HSE divided by 2 + 8 + + + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + Mul2 + PLL input clock x 2 + 0 + + + Mul3 + PLL input clock x 3 + 1 + + + Mul4 + PLL input clock x 4 + 2 + + + Mul5 + PLL input clock x 5 + 3 + + + Mul6 + PLL input clock x 6 + 4 + + + Mul7 + PLL input clock x 7 + 5 + + + Mul8 + PLL input clock x 8 + 6 + + + Mul9 + PLL input clock x 9 + 7 + + + Mul10 + PLL input clock x 10 + 8 + + + Mul11 + PLL input clock x 11 + 9 + + + Mul12 + PLL input clock x 12 + 10 + + + Mul13 + PLL input clock x 13 + 11 + + + Mul14 + PLL input clock x 14 + 12 + + + Mul15 + PLL input clock x 15 + 13 + + + Mul16 + PLL input clock x 16 + 14 + + + + + MCO + Microcontroller clock + output + 24 + 3 + read-write + + + NoClock + MCO output disabled, no clock on MCO + 0 + + + InternalRC + Internal RC 14 MHz (HSI14) oscillator clock selected + 1 + + + InternalLSI + Internal low speed (LSI) oscillator clock selected + 2 + + + LSE + External low speed (LSE) oscillator clock selected + 3 + + + System + System clock select + 4 + + + InternalHSI + Internal RC 8 MHz (HSI) oscillator clock selected + 5 + + + ExternalHSE + External 4-32 MHz (HSE) oscillator clock selected + 6 + + + PLL + PLL clock selected (divided by 1 or 2, depending on PLLNODIV) + 7 + + + HSI48 + Internal RC 48 MHz (HSI48) oscillator clock selected + 8 + + + + + MCOPRE + Microcontroller Clock Output + Prescaler + 28 + 3 + read-write + + + div1 + MCO is divided by 1 + 0 + + + div2 + MCO is divided by 2 + 1 + + + div4 + MCO is divided by 4 + 2 + + + div8 + MCO is divided by 8 + 3 + + + div16 + MCO is divided by 16 + 4 + + + div32 + MCO is divided by 32 + 5 + + + div64 + MCO is divided by 64 + 6 + + + div128 + MCO is divided by 128 + 7 + + + + + PLLNODIV + PLL clock not divided for + MCO + 31 + 1 + read-write + + + div2 + PLL is divided by 2 for MCO + 0 + + + NoDiv + PLL is not divided for MCO + 1 + + + + + + + CIR + CIR + Clock interrupt register + (RCC_CIR) + 0x8 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + HSI14RDYF + HSI14 ready interrupt flag + 5 + 1 + read-only + + + HSI48RDYF + HSI48 ready interrupt flag + 6 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + Disabled + LSI ready interrupt disabled. + 0 + + + Enabled + LSI ready interrupt enabled. + 1 + + + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + Disabled + LSE ready interrupt disabled. + 0 + + + Enabled + LSE ready interrupt enabled. + 1 + + + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + Disabled + HSI ready interrupt disabled. + 0 + + + Enabled + HSI ready interrupt enabled. + 1 + + + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + Disabled + HSE ready interrupt disabled. + 0 + + + Enabled + HSE ready interrupt enabled. + 1 + + + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + Disabled + PLL lock interrupt disabled. + 0 + + + Enabled + PLL lock interrupt enabled. + 1 + + + + + HSI14RDYE + HSI14 ready interrupt + enable + 13 + 1 + read-write + + + Disabled + HSI14 ready interrupt disabled. + 0 + + + Enabled + HSI14 ready interrupt enabled. + 1 + + + + + HSI48RDYIE + HSI48 ready interrupt + enable + 14 + 1 + read-write + + + Disabled + HSI48 ready interrupt disabled. + 0 + + + Enabled + HSI48 ready interrupt enabled. + 1 + + + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + Reset + LSIRDYF Cleared. + 1 + + + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + Reset + LSERDYF Cleared. + 1 + + + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + Reset + HSIRDYF Cleared. + 1 + + + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + Reset + HSERDYF Cleared. + 1 + + + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + Reset + PLLRDYF Cleared. + 1 + + + + + HSI14RDYC + HSI 14 MHz Ready Interrupt + Clear + 21 + 1 + write-only + + + Reset + HSI14RDYF Cleared. + 1 + + + + + HSI48RDYC + HSI48 Ready Interrupt + Clear + 22 + 1 + write-only + + + Reset + HSI48RDYF Cleared. + 1 + + + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + Reset + CSSF Cleared. + 1 + + + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + (RCC_APB2RSTR) + 0xC + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + SYSCFG and COMP reset + 0 + 1 + + + Reset + Reset SYSCFG. + 1 + + + + + ADCRST + ADC interface reset + 9 + 1 + + + Reset + Reset ADC. + 1 + + + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + Reset + Reset TIM1 timer. + 1 + + + + + SPI1RST + SPI 1 reset + 12 + 1 + + + Reset + Reset SPI1. + 1 + + + + + USART1RST + USART1 reset + 14 + 1 + + + Reset + Reset USART1. + 1 + + + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + Reset + Reset TIM15 timer. + 1 + + + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + Reset + Reset TIM16 timer. + 1 + + + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + Reset + Reset TIM17 timer. + 1 + + + + + DBGMCURST + Debug MCU reset + 22 + 1 + + + Reset + Reset Debug MCU. + 1 + + + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + (RCC_APB1RSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + Reset + Reset TIM2 timer. + 1 + + + + + TIM3RST + Timer 3 reset + 1 + 1 + + + Reset + Reset TIM3 timer. + 1 + + + + + TIM6RST + Timer 6 reset + 4 + 1 + + + Reset + Reset TIM6 timer. + 1 + + + + + TIM7RST + TIM7 timer reset + 5 + 1 + + + Reset + Reset TIM7 timer. + 1 + + + + + TIM14RST + Timer 14 reset + 8 + 1 + + + Reset + Reset TIM14 timer. + 1 + + + + + WWDGRST + Window watchdog reset + 11 + 1 + + + Reset + Reset window watchdog. + 1 + + + + + SPI2RST + SPI2 reset + 14 + 1 + + + Reset + Reset SPI2. + 1 + + + + + USART2RST + USART 2 reset + 17 + 1 + + + Reset + Reset USART2. + 1 + + + + + USART3RST + USART3 reset + 18 + 1 + + + Reset + Reset USART3. + 1 + + + + + USART4RST + USART4 reset + 19 + 1 + + + Reset + Reset USART4. + 1 + + + + + I2C1RST + I2C1 reset + 21 + 1 + + + Reset + Reset I2C1. + 1 + + + + + I2C2RST + I2C2 reset + 22 + 1 + + + Reset + Reset I2C2. + 1 + + + + + USBRST + USB interface reset + 23 + 1 + + + Reset + Reset USB interface. + 1 + + + + + CANRST + CAN interface reset + 25 + 1 + + + Reset + Reset CAN interface. + 1 + + + + + CRSRST + Clock Recovery System interface + reset + 27 + 1 + + + Reset + Reset CRS interface. + 1 + + + + + PWRRST + Power interface reset + 28 + 1 + + + Reset + Reset power interface. + 1 + + + + + DACRST + DAC interface reset + 29 + 1 + + + Reset + Reset DAC. + 1 + + + + + CECRST + HDMI CEC reset + 30 + 1 + + + Reset + Reset HDMI CEC. + 1 + + + + + + + AHBENR + AHBENR + AHB Peripheral Clock enable register + (RCC_AHBENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + Enabled + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + + + FLITFEN + FLITF clock enable + 4 + 1 + + + + + CRCEN + CRC clock enable + 6 + 1 + + + + + IOPAEN + I/O port A clock enable + 17 + 1 + + + + + IOPBEN + I/O port B clock enable + 18 + 1 + + + + + IOPCEN + I/O port C clock enable + 19 + 1 + + + + + IOPDEN + I/O port D clock enable + 20 + 1 + + + + + IOPFEN + I/O port F clock enable + 22 + 1 + + + + + TSCEN + Touch sensing controller clock + enable + 24 + 1 + + + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + (RCC_APB2ENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + + + ADCEN + ADC 1 interface clock + enable + 9 + 1 + + + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + + + SPI1EN + SPI 1 clock enable + 12 + + + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + + + DBGMCUEN + MCU debug module clock + enable + 22 + 1 + + + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + (RCC_APB1ENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + + + TIM7EN + TIM7 timer clock enable + 5 + 1 + + + + + TIM14EN + Timer 14 clock enable + 8 + 1 + + + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + + + SPI2EN + SPI 2 clock enable + 14 + 1 + + + + + USART2EN + USART 2 clock enable + 17 + 1 + + + + + USART3EN + USART3 clock enable + 18 + 1 + + + + + USART4EN + USART4 clock enable + 19 + 1 + + + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + + + I2C2EN + I2C 2 clock enable + 22 + 1 + + + + + USBRST + USB interface clock enable + 23 + 1 + + + + + CANEN + CAN interface clock enable + 25 + 1 + + + + + CRSEN + Clock Recovery System interface clock + enable + 27 + 1 + + + + + PWREN + Power interface clock + enable + 28 + 1 + + + + + DACEN + DAC interface clock enable + 29 + 1 + + + + + CECEN + HDMI CEC interface clock + enable + 30 + 1 + + + + + + + BDCR + BDCR + Backup domain control register + (RCC_BDCR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + Enabled + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + Enabled + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + LSEDRV + LSE oscillator drive + capability + 3 + 2 + read-write + + + Low + Xtal mode low drive capability. + 0 + + + MediumHigh + Xtal mode medium high drive capability. + 1 + + + MediumLow + Xtal mode medium low drive capability. + 2 + + + High + Xtal mode high drive capability. + 3 + + + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + NoClock + No Clock. + 0 + + + LSE + LSE oscillator clock used as RTC clock. + 1 + + + LSI + LSI oscillator clock used as RTC clock. + 2 + + + HSE + HSE oscillator clock divided by 32 used as RTC clock. + 3 + + + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + Disabled + Disabled. + 0 + + + Enabled + Enabled. + 1 + + + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + NoReset + Reset not activated. + 0 + + + Reset + Resets the entire RTC domain. + 1 + + + + + + + CSR + CSR + Control/status register + (RCC_CSR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + Disabled + LSI oscillator OFF. + 0 + + + Enabled + LSI oscillator ON. + 1 + + + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + Cleared + Clear the reset flags. + 1 + + + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + read-only + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-only + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + IOPARST + I/O port A reset + 17 + 1 + + + Reset + Reset I/O port A. + 1 + + + + + IOPBRST + I/O port B reset + 18 + 1 + + + Reset + Reset I/O port B. + 1 + + + + + IOPCRST + I/O port C reset + 19 + 1 + + + Reset + Reset I/O port C. + 1 + + + + + IOPDRST + I/O port D reset + 20 + 1 + + + Reset + Reset I/O port D. + 1 + + + + + IOPFRST + I/O port F reset + 22 + 1 + + + Reset + Reset I/O port F. + 1 + + + + + TSCRST + Touch sensing controller + reset + 24 + 1 + + + Reset + Reset TSC. + 1 + + + + + + + CFGR2 + CFGR2 + Clock configuration register 2 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDIV + PREDIV division factor + 0 + 4 +* + + Div1 + PREDIV input clock not divided. + 0 + + + Div2 + PREDIV input clock divided by 2. + 1 + + + Div3 + PREDIV input clock divided by 3. + 2 + + + Div4 + PREDIV input clock divided by 4. + 3 + + + Div5 + PREDIV input clock divided by 5. + 4 + + + Div6 + PREDIV input clock divided by 6. + 5 + + + Div7 + PREDIV input clock divided by 7. + 6 + + + Div8 + PREDIV input clock divided by 8. + 7 + + + Div9 + PREDIV input clock divided by 9. + 8 + + + Div10 + PREDIV input clock divided by 10. + 9 + + + Div11 + PREDIV input clock divided by 11. + 10 + + + Div12 + PREDIV input clock divided by 12. + 11 + + + Div13 + PREDIV input clock divided by 13. + 12 + + + Div14 + PREDIV input clock divided by 14. + 13 + + + Div15 + PREDIV input clock divided by 15. + 14 + + + Div16 + PREDIV input clock divided by 16. + 15 + + + + + + + CFGR3 + CFGR3 + Clock configuration register 3 + 0x30 + 0x20 + read-write + 0x00000000 + + + USART1SW + USART1 clock source + selection + 0 + 2 + + + PCLK + PCLK selected as USART3 clock source (default). + 0 + + + SystemClock + System clock (SYSCLK) selected as USART3 clock. + 1 + + + LSE + LSE clock selected as USART3 clock. + 2 + + + HSI + HSI clock selected as USART3 clock. + 3 + + + + + I2C1SW + I2C1 clock source + selection + 4 + 1 + + + HSI + HSI clock selected as I2C1 clock source (default). + 0 + + + SYSCLK + System clock (SYSCLK) selected as I2C1 clock. + 1 + + + + + CECSW + HDMI CEC clock source + selection + 6 + 1 + + + HSI + HSI clock, divided by 244, selected as CEC clock (default). + 0 + + + LSE + LSE clock selected as CEC clock. + 1 + + + + + USBSW + USB clock source selection + 7 + 1 + + + HSI48 + HSI48 clock selected as USB clock source (default). + 0 + + + PLLClock + PLL clock (PLLCLK) selected as USB clock. + 1 + + + + + ADCSW + ADC clock source selection + 8 + 1 + + + USART2SW + USART2 clock source + selection + 16 + 2 + + + PCLK + PCLK selected as USART3 clock source (default). + 0 + + + SystemClock + System clock (SYSCLK) selected as USART3 clock. + 1 + + + LSE + LSE clock selected as USART3 clock. + 2 + + + HSI + HSI clock selected as USART3 clock. + 3 + + + + + + + CR2 + CR2 + Clock control register 2 + 0x34 + 0x20 + 0x00000080 + + + HSI14ON + HSI14 clock enable + 0 + 1 + read-write + + + Disabled + HSI14 oscillator OFF. + 0 + + + Enabled + HSI14 oscillator ON. + 1 + + + + + HSI14RDY + HR14 clock ready flag + 1 + 1 + read-only + + + HSI14DIS + HSI14 clock request from ADC + disable + 2 + 1 + read-write + + + Enabled + ADC interface can turn on the HSI14 oscillator. + 0 + + + Disabled + ADC interface can not turn on the HSI14 oscillator. + 1 + + + + + HSI14TRIM + HSI14 clock trimming + 3 + 5 + read-write + + + 0 + 31 + + + + + HSI14CAL + HSI14 clock calibration + 8 + 8 + read-only + + + HSI48ON + HSI48 clock enable + 16 + 1 + read-write + + + Disabled + HSI48 oscillator OFF. + 0 + + + Enabled + HSI48 oscillator ON. + 1 + + + + + HSI48RDY + HSI48 clock ready flag + 17 + 1 + read-only + + + HSI48CAL + HSI48 factory clock + calibration + 24 + 1 + read-only + + + + + + + SYSCFG_COMP + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x21 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + ADC_DMA_RMP + ADC DMA remapping bit + 8 + 1 + + + USART1_TX_DMA_RMP + USART1_TX DMA remapping + bit + 9 + 1 + + + USART1_RX_DMA_RMP + USART1_RX DMA request remapping + bit + 10 + 1 + + + TIM16_DMA_RMP + TIM16 DMA request remapping + bit + 11 + 1 + + + TIM17_DMA_RMP + TIM17 DMA request remapping + bit + 12 + 1 + + + I2C_PB6_FM + Fast Mode Plus (FM plus) driving + capability activation bits. + 16 + 1 + + + I2C_PB7_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 17 + 1 + + + I2C_PB8_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 18 + 1 + + + I2C_PB9_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 19 + 1 + + + I2C1_FM_plus + FM+ driving capability activation for + I2C1 + 20 + 1 + + + I2C2_FM_plus + FM+ driving capability activation for + I2C2 + 21 + 1 + + + SPI2_DMA_RMP + SPI2 DMA request remapping + bit + 24 + 1 + + + USART2_DMA_RMP + USART2 DMA request remapping + bit + 25 + 1 + + + USART3_DMA_RMP + USART3 DMA request remapping + bit + 26 + 1 + + + I2C1_DMA_RMP + I2C1 DMA request remapping + bit + 27 + 1 + + + TIM1_DMA_RMP + TIM1 DMA request remapping + bit + 28 + 1 + + + TIM2_DMA_RMP + TIM2 DMA request remapping + bit + 29 + 1 + + + TIM3_DMA_RMP + TIM3 DMA request remapping + bit + 30 + 1 + + + + + SYSCFG_EXTICR1 + SYSCFG_EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI 3 configuration bits + 12 + 4 + + + EXTI2 + EXTI 2 configuration bits + 8 + 4 + + + EXTI1 + EXTI 1 configuration bits + 4 + 4 + + + EXTI0 + EXTI 0 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR2 + SYSCFG_EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI 7 configuration bits + 12 + 4 + + + EXTI6 + EXTI 6 configuration bits + 8 + 4 + + + EXTI5 + EXTI 5 configuration bits + 4 + 4 + + + EXTI4 + EXTI 4 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR3 + SYSCFG_EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI 11 configuration bits + 12 + 4 + + + EXTI10 + EXTI 10 configuration bits + 8 + 4 + + + EXTI9 + EXTI 9 configuration bits + 4 + 4 + + + EXTI8 + EXTI 8 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR4 + SYSCFG_EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI 15 configuration bits + 12 + 4 + + + EXTI14 + EXTI 14 configuration bits + 8 + 4 + + + EXTI13 + EXTI 13 configuration bits + 4 + 4 + + + EXTI12 + EXTI 12 configuration bits + 0 + 4 + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x0000 + + + SRAM_PEF + SRAM parity flag + 8 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + SRAM_PARITY_LOCK + SRAM parity lock bit + 1 + 1 + + + LOCUP_LOCK + Cortex-M0 LOCKUP bit enable + bit + 0 + 1 + + + + + COMP_CSR + COMP_CSR + control and status register + 0x1C + 0x20 + 0x00000000 + + + COMP1EN + Comparator 1 enable + 0 + 1 + read-write + + + COMP1_INP_DAC + COMP1_INP_DAC + 1 + 1 + read-write + + + COMP1MODE + Comparator 1 mode + 2 + 2 + read-write + + + COMP1INSEL + Comparator 1 inverting input + selection + 4 + 3 + read-write + + + COMP1OUTSEL + Comparator 1 output + selection + 8 + 3 + read-write + + + COMP1POL + Comparator 1 output + polarity + 11 + 1 + read-write + + + COMP1HYST + Comparator 1 hysteresis + 12 + 2 + read-write + + + COMP1OUT + Comparator 1 output + 14 + 1 + read-only + + + COMP1LOCK + Comparator 1 lock + 15 + 1 + read-write + + + COMP2EN + Comparator 2 enable + 16 + 1 + read-write + + + COMP2MODE + Comparator 2 mode + 18 + 2 + read-write + + + COMP2INSEL + Comparator 2 inverting input + selection + 20 + 3 + read-write + + + WNDWEN + Window mode enable + 23 + 1 + read-write + + + COMP2OUTSEL + Comparator 2 output + selection + 24 + 3 + read-write + + + COMP2POL + Comparator 2 output + polarity + 27 + 1 + read-write + + + COMP2HYST + Comparator 2 hysteresis + 28 + 2 + read-write + + + COMP2OUT + Comparator 2 output + 30 + 1 + read-only + + + COMP2LOCK + Comparator 2 lock + 31 + 1 + read-write + + + + + + + ADC + Analog-to-digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and comparator interrupts + 12 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + Analog watchdog flag + 7 + 1 + + + OVR + ADC overrun + 4 + 1 + + + EOS + End of sequence flag + 3 + 1 + + + EOC + End of conversion flag + 2 + 1 + + + EOSMP + End of sampling flag + 1 + 1 + + + ADRDY + ADC ready + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + Analog watchdog interrupt + enable + 7 + 1 + + + OVRIE + Overrun interrupt enable + 4 + 1 + + + EOSIE + End of conversion sequence interrupt + enable + 3 + 1 + + + EOCIE + End of conversion interrupt + enable + 2 + 1 + + + EOSMPIE + End of sampling flag interrupt + enable + 1 + 1 + + + ADRDYIE + ADC ready interrupt enable + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC calibration + 31 + 1 + + + ADSTP + ADC stop conversion + command + 4 + 1 + + + ADSTART + ADC start conversion + command + 2 + 1 + + + ADDIS + ADC disable command + 1 + 1 + + + ADEN + ADC enable command + 0 + 1 + + + + + CFGR1 + CFGR1 + configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 26 + 5 + + + AWDEN + Analog watchdog enable + 23 + 1 + + + AWDSGL + Enable the watchdog on a single channel + or on all channels + 22 + 1 + + + DISCEN + Discontinuous mode + 16 + 1 + + + AUTOFF + Auto-off mode + 15 + 1 + + + AUTDLY + Auto-delayed conversion + mode + 14 + 1 + + + CONT + Single / continuous conversion + mode + 13 + 1 + + + OVRMOD + Overrun management mode + 12 + 1 + + + EXTEN + External trigger enable and polarity + selection + 10 + 2 + + + EXTSEL + External trigger selection + 6 + 3 + + + ALIGN + Data alignment + 5 + 1 + + + RES + Data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + Direct memery access + configuration + 1 + 1 + + + DMAEN + Direct memory access + enable + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x10 + 0x20 + read-write + 0x00008000 + + + JITOFF_D4 + JITOFF_D4 + 31 + 1 + + + JITOFF_D2 + JITOFF_D2 + 30 + 1 + + + + + SMPR + SMPR + sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMPR + Sampling time selection + 0 + 3 + + + + + TR + TR + watchdog threshold register + 0x20 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 16 + 12 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + CHSELR + CHSELR + channel selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + CHSEL18 + Channel-x selection + 18 + 1 + + + CHSEL17 + Channel-x selection + 17 + 1 + + + CHSEL16 + Channel-x selection + 16 + 1 + + + CHSEL15 + Channel-x selection + 15 + 1 + + + CHSEL14 + Channel-x selection + 14 + 1 + + + CHSEL13 + Channel-x selection + 13 + 1 + + + CHSEL12 + Channel-x selection + 12 + 1 + + + CHSEL11 + Channel-x selection + 11 + 1 + + + CHSEL10 + Channel-x selection + 10 + 1 + + + CHSEL9 + Channel-x selection + 9 + 1 + + + CHSEL8 + Channel-x selection + 8 + 1 + + + CHSEL7 + Channel-x selection + 7 + 1 + + + CHSEL6 + Channel-x selection + 6 + 1 + + + CHSEL5 + Channel-x selection + 5 + 1 + + + CHSEL4 + Channel-x selection + 4 + 1 + + + CHSEL3 + Channel-x selection + 3 + 1 + + + CHSEL2 + Channel-x selection + 2 + 1 + + + CHSEL1 + Channel-x selection + 1 + 1 + + + CHSEL0 + Channel-x selection + 0 + 1 + + + + + DR + DR + data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + Converted data + 0 + 16 + + + + + CCR + CCR + common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + VBATEN + VBAT enable + 24 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + Temperature sensor and VREFINT + enable + 22 + 1 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 27 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UE + USART enable + 0 + 1 + + ENABLED + + Disabled + USART Disabled. + 0 + + + Enabled + USART Enabled. + 1 + + + + + UESM + USART enable in Stop mode + 1 + 1 + + + NotAble + USART not able to wake up the MCU from Stop mode. + 0 + + + Able + USART able to wake up the MCU from Stop mode. + 1 + + + + + RE + Receiver enable + 2 + 1 + + ENABLED + + Disabled + Receiver is disabled. + 0 + + + Enabled + Receiver is enabled and begins searching for a start bit. + 1 + + + + + TE + Transmitter enable + 3 + 1 + + ENABLED + + Disabled + Transmitter is disabled. + 0 + + + Enabled + Transmitter is enabled. + 1 + + + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + ENABLED + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated whenever IDLE=1 in the USART_ISR register. + 1 + + + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + ENABLED + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_ISR register. + 1 + + + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + ENABLED + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated whenever TC=1 in the USART_ISR register. + 1 + + + + + TXEIE + interrupt enable + 7 + 1 + + ENABLED + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated whenever TXE=1 in the USART_ISR register. + 1 + + + + + PEIE + PE interrupt enable + 8 + 1 + + ENABLED + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated whenever PE=1 in the USART_ISR register. + 1 + + + + + PS + Parity selection + 9 + 1 + + + Even + Even parity. + 0 + + + Odd + Odd parity. + 1 + + + + + PCE + Parity control enable + 10 + 1 + + ENABLED + + Disabled + Parity control disabled. + 0 + + + Enabled + Parity control enabled. + 1 + + + + + WAKE + Receiver wakeup method + 11 + 1 + + + Idle + Idle line. + 0 + + + Address + Address mark. + 1 + + + + + M + Word length + 12 + 1 + + + 8bits + 1 Start bit, 8 data bits, n stop bits (Do not miss M1 bit = 0). + 0 + + + 9bits + 1 Start bit, 9 data bits, n stop bits (Do not miss M1 bit = 0). + 1 + + + + + MME + Mute mode enable + 13 + 1 + + + Disabled + Receiver in active mode permanently. + 0 + + + Enabled + Receiver can switch between mute mode and active mode. + 1 + + + + + CMIE + Character match interrupt + enable + 14 + 1 + + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 1 + + + + + OVER8 + Oversampling mode + 15 + 1 + + + Over16 + Oversampling by 16. + 0 + + + Over8 + Oversampling by 8. + 1 + + + + + DEDT + Driver Enable deassertion + time + 16 + 5 + + + 0 + 31 + + + + + DEAT + Driver Enable assertion + time + 21 + 5 + + + 0 + 31 + + + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated when the RTOF bit is set in the USART_ISR register. + 1 + + + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + Disabled + Interrupt is inhibited. + 0 + + + Enabled + An USART interrupt is generated when the EOBF flag is set in the USART_ISR register. + 1 + + + + + M1 + Word length + 28 + 1 + + + 9bits + 1 Start bit, 9 data bits, n stop bits (Do not miss M0 bit = 1). + 0 + + + 7bits + 1 Start bit, 7 data bits, n stop bits (Do not miss M0 bit = 0). + 1 + + + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4 + Address of the USART node + 28 + 4 + + + 0 + 15 + + + + + ADD0 + Address of the USART node + 24 + 4 + + + 0 + 15 + + + + + RTOEN + Receiver timeout enable + 23 + 1 + + + Disabled + Receiver timeout feature disabled. + 0 + + + Enabled + Receiver timeout feature enabled. + 1 + + + + + ABRMOD + Auto baud rate mode + 21 + 2 + + + StartBit + Measurement of the start bit is used to detect the baud rate. + 0 + + + FallingEdge + Falling edge to falling edge measurement. + 1 + + + 0x7F + 0x7F frame detection.. + 2 + + + 0x55 + 0x55 frame detection. + 3 + + + + + ABREN + Auto baud rate enable + 20 + 1 + + + Disabled + Auto baud rate detection disabled. + 0 + + + Enabled + Auto baud rate detection enabled. + 1 + + + + + MSBFIRST + Most significant bit first + 19 + 1 + + + LSB + Data is transmitted/received with data bit 0 first, following the start bit. + 0 + + + MSB + Data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit. + 1 + + + + + DATAINV + Binary data inversion + 18 + 1 + + + POSITIVE + Logical data from the data register are send/received in positive/direct logic. + 0 + + + NEGATIVE + Logical data from the data register are send/received in negative/inverse logic. + 1 + + + + + TXINV + TX pin active level + inversion + 17 + 1 + + + NORMAL + TX pin signal works using the standard logic levels + 0 + + + INVERTED + TX pin signal values are inverted. + 1 + + + + + RXINV + RX pin active level + inversion + 16 + 1 + + + NORMAL + RX pin signal works using the standard logic levels + 0 + + + INVERTED + RX pin signal values are inverted. + 1 + + + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STANDARD + TX/RX pins are used as defined in standard pinout. + 0 + + + SWAPPED + The TX and RX pins functions are swapped. + 1 + + + + + LINEN + LIN mode enable + 14 + 1 + + + DISABLED + LIN mode disabled. + 0 + + + ENABLED + LIN mode enabled. + 1 + + + + + STOP + STOP bits + 12 + 2 + + + 1STOP + 1 stop bit. + 0 + + + HalfSTOP + 0.5 stop bit. + 1 + + + 2STOP + 2 stop bits. + 2 + + + 1HalfSTOP + 1.5 stop bits. + 3 + + + + + CLKEN + Clock enable + 11 + 1 + + + DISABLED + CK pin disabled. + 0 + + + ENABLED + CK pin enabled. + 1 + + + + + CPOL + Clock polarity + 10 + 1 + + + LOW + Steady low value on CK pin outside transmission window. + 0 + + + HIGH + Steady high value on CK pin outside transmission window. + 1 + + + + + CPHA + Clock phase + 9 + 1 + + + FIRST + The first clock transition is the first data capture edge. + 0 + + + SECOND + The second clock transition is the first data capture edge. + 1 + + + + + LBCL + Last bit clock pulse + 8 + 1 + + + NOOUTPUT + The clock pulse of the last data bit is not output to the CK pin. + 0 + + + OUTPUT + The clock pulse of the last data bit is output to the CK pin. + 1 + + + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + DISABLED + Interrupt is inhibited. + 0 + + + ENABLED + An interrupt is generated whenever LBDF=1 in the USART_ISR register. + 1 + + + + + LBDL + LIN break detection length + 5 + 1 + + + 10bits + 10-bit break detection. + 0 + + + 11bits + 11-bit break detection. + 1 + + + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + 4bits + 4-bit address detection. + 0 + + + 7bits + 7-bit address detection (in 8-bit data mode). + 1 + + + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + DISABLED + Interrupt is inhibited. + 0 + + + ENABLED + An USART interrupt is generated whenever WUF=1 in the USART_ISR register. + 1 + + + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + ADDRESS + WUF active on address match. + 0 + + + Reserved + Reserved. + 1 + + + STARTBIT + WuF active on Start bit detection. + 2 + + + RXNE + WUF active on RXNE. + 3 + + + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + 0 + 7 + + + + + DEP + Driver enable polarity + selection + 15 + 1 + + + HIGH + DE signal is active high. + 0 + + + LOW + DE signal is active low. + 1 + + + + + DEM + Driver enable mode + 14 + 1 + + + DISABLED + DE function is disabled. + 0 + + + ENABLED + DE function is enabled. + 1 + + + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + NOTDISABLED + DMA is not disabled in case of reception error. + 0 + + + DISABLED + DMA is disabled following a reception error. + 1 + + + + + OVRDIS + Overrun Disable + 12 + 1 + + + NOTDISABLED + Overrun Error Flag, ORE, is set when received data is not read before receiving new data. + 0 + + + DISABLED + Overrun functionality is disabled. + 1 + + + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + ThreeSamples + Three sample bit method. + 0 + + + OneSample + One sample bit method. + 1 + + + + + CTSIE + CTS interrupt enable + 10 + 1 + + + DISABLED + Interrupt is inhibited. + 0 + + + ENABLED + An interrupt is generated whenever CTSIF=1 in the USART_ISR register. + 1 + + + + + CTSE + CTS enable + 9 + 1 + + + DISABLED + CTS hardware flow control disabled. + 0 + + + ENABLED + CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). + 1 + + + + + RTSE + RTS enable + 8 + 1 + + + DISABLED + RTS hardware flow control disabled. + 0 + + + ENABLED + RTS output enabled, data is only requested when there is space in the receive buffer. + 1 + + + + + DMAT + DMA enable transmitter + 7 + 1 + + + DISABLED + DMA mode is disabled for transmission. + 0 + + + ENABLED + DMA mode is enabled for transmission. + 1 + + + + + DMAR + DMA enable receiver + 6 + 1 + + + DISABLED + DMA mode is disabled for reception. + 0 + + + ENABLED + DMA mode is enabled for reception. + 1 + + + + + SCEN + Smartcard mode enable + 5 + 1 + + + DISABLED + Smartcard Mode disabled. + 0 + + + ENABLED + Smartcard Mode enabled. + 1 + + + + + NACK + Smartcard NACK enable + 4 + 1 + + + DISABLED + NACK transmission in case of parity error is disabled. + 0 + + + ENABLED + NACK transmission during parity error is enabled. + 1 + + + + + HDSEL + Half-duplex selection + 3 + 1 + + + DISABLED + Half duplex mode is not selected. + 0 + + + ENABLED + Half duplex mode is selected. + 1 + + + + + IRLP + IrDA low-power + 2 + 1 + + + NORMAL + Normal mode. + 0 + + + LOWPOWER + Low-power mode. + 1 + + + + + IREN + IrDA mode enable + 1 + 1 + + + DISABLED + IrDA disabled. + 0 + + + ENABLED + IrDA enabled. + 1 + + + + + EIE + Error interrupt enable + 0 + 1 + + + DISABLED + Interrupt is inhibited. + 0 + + + ENABLED + An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register. + 1 + + + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + 0 + 4095 + + + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + 0 + 15 + + + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + 0 + 255 + + + + + PSC + Prescaler value + 0 + 8 + + + 0 + 255 + + + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + 0 + 255 + + + + + RTO + Receiver timeout value + 0 + 24 + + + 0 + 16777215 + + + + + + + RQR + RQR + Request register + 0x18 + 0x20 + read-write + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + SET + write + + Set + sets the TXE flag. + 1 + + + + + RXFRQ + Receive data flush request + 3 + 1 + + CLEAR + write + + Clear + clears the RXNE flag. + 1 + + + + + MMRQ + Mute mode request + 2 + 1 + + SET + write + + Set + sets the RWU flag and puts the USART in mute mode. + 1 + + + + + SBKRQ + Send break request + 1 + 1 + + SET + write + + Set + sets the SBKF flag and request to send a BREAK on the line. + 1 + + + + + ABRRQ + Auto baud rate request + 0 + 1 + + SET + write + + Set + resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 1 + + + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + Receive enable acknowledge + flag + 22 + 1 + + + TEACK + Transmit enable acknowledge + flag + 21 + 1 + + + WUF + Wakeup from Stop mode flag + 20 + 1 + + + RWU + Receiver wakeup from Mute + mode + 19 + 1 + + + SBKF + Send break flag + 18 + 1 + + + CMF + character match flag + 17 + 1 + + + BUSY + Busy flag + 16 + 1 + + + ABRF + Auto baud rate flag + 15 + 1 + + + ABRE + Auto baud rate error + 14 + 1 + + + EOBF + End of block flag + 12 + 1 + + + RTOF + Receiver timeout + 11 + 1 + + + CTS + CTS flag + 10 + 1 + + + CTSIF + CTS interrupt flag + 9 + 1 + + + LBDF + LIN break detection flag + 8 + 1 + + + TXE + Transmit data register + empty + 7 + 1 + + + TC + Transmission complete + 6 + 1 + + + RXNE + Read data register not + empty + 5 + 1 + + + IDLE + Idle line detected + 4 + 1 + + + ORE + Overrun error + 3 + 1 + + + NF + Noise detected flag + 2 + 1 + + + FE + Framing error + 1 + 1 + + + PE + Parity error + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + read-write + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + CLEARED + write + + Clear + clears the WUF flag in the USART_ISR register. + 1 + + + + + CMCF + Character match clear flag + 17 + 1 + + CLEARED + write + + Clear + clears the CMF flag in the USART_ISR register. + 1 + + + + + EOBCF + End of timeout clear flag + 12 + 1 + + CLEARED + write + + Clear + clears the EOBF flag in the USART_ISR register. + 1 + + + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + CLEARED + write + + Clear + clears the RTOF flag in the USART_ISR register. + 1 + + + + + CTSCF + CTS clear flag + 9 + 1 + + CLEARED + write + + Clear + clears the CTSIF flag in the USART_ISR register. + 1 + + + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + CLEARED + write + + Clear + clears the LBDF flag in the USART_ISR register. + 1 + + + + + TCCF + Transmission complete clear + flag + 6 + 1 + + CLEARED + write + + Clear + clears the TC flag in the USART_ISR register. + 1 + + + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + CLEARED + write + + Clear + clears the IDLE flag in the USART_ISR register. + 1 + + + + + ORECF + Overrun error clear flag + 3 + 1 + + CLEARED + write + + Clear + clears the ORE flag in the USART_ISR register. + 1 + + + + + NCF + Noise detected clear flag + 2 + 1 + + CLEARED + write + + Clear + clears the NF flag in the USART_ISR register. + 1 + + + + + FECF + Framing error clear flag + 1 + 1 + + CLEARED + write + + Clear + clears the FE flag in the USART_ISR register. + 1 + + + + + PECF + Parity error clear flag + 0 + 1 + + CLEARED + write + + Clear + clears the PE flag in the USART_ISR register. + 1 + + + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + 0 + 511 + + + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 28 + + + + USART3 + 0x40004800 + + USART3_4 + USART3 and USART4 global + interrupt + 29 + + + + USART4 + 0x40004C00 + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC interrupts + 2 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + 0x00000000 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + read-write + + + REFCKON + RTC_REFIN reference clock detection + enable (50 or 60 Hz) + 4 + 1 + read-write + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + read-write + + + FMT + Hour format + 6 + 1 + read-write + + + ALRAE + Alarm A enable + 8 + 1 + read-write + + + TSE + timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + read-write + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + write-only + + + BKP + Backup + 18 + 1 + read-write + + + COSEL + Calibration output + selection + 19 + 1 + read-write + + + POL + Output polarity + 20 + 1 + read-write + + + OSEL + Output selection + 21 + 2 + read-write + + + COE + Calibration output enable + 23 + 1 + read-write + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format. + 28 + 2 + + + DU + Date units or day in BCD + format. + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + 0 + 255 + + + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format. + 20 + 2 + + + HU + Hour units in BCD format. + 16 + 4 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + ST + Second tens in BCD format. + 4 + 3 + + + SU + Second units in BCD + format. + 0 + 4 + + + + + TSDR + TSDR + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + time-stamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + PC15MODE + PC15 mode + 23 + 1 + + + PC15VALUE + PC15 value + 22 + 1 + + + PC14MODE + PC14 mode + 21 + 1 + + + PC14VALUE + PC14 value + 20 + 1 + + + PC13MODE + PC13 mode + 19 + 1 + + + PC13VALUE + RTC_ALARM output type/PC13 + value + 18 + 1 + + + TAMP_PUDIS + RTC_TAMPx pull-up disable + 15 + 1 + + + TAMP_PRCH + RTC_TAMPx precharge + duration + 13 + 2 + + + TAMPFLT + RTC_TAMPx filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2_TRG + Active level for RTC_TAMP2 + input + 4 + 1 + + + TAMP2E + RTC_TAMP2 input detection + enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for RTC_TAMP1 + input + 1 + 1 + + + TAMP1E + RTC_TAMP1 input detection + enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + TIM15 + General-purpose-timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + TIM15 global interrupt + 20 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Division ratio between the timer clock (CK_INT) frequency and sampling clock + 8 + 2 + + CKD + + Div1 + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow/underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + Reset + OC2=0 (after a dead-time if OC2N is implemented) when MOE=0 + 0 + + + Set + OC2=1 (after a dead-time if OC2N is implemented) when MOE=0 + 1 + + + + + OIS1N + Output Idle state 1 + 9 + 1 + + + Reset + OC1N=0 after a dead-time when MOE=0 + 0 + + + Set + OC1N=1 after a dead-time when MOE=0 + 1 + + + + + OIS1 + Output Idle state 1 + 8 + 1 + + + Reset + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0 + + + Set + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 1 + + + + + MMS + Master mode selection + 4 + 3 + + + Reset + the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. + 0 + + + Enable + the Counter Enable signal CNT_EN is used as trigger output (TRGO). + 1 + + + Update + The update event is selected as trigger output (TRGO). + 2 + + + ComparePulse + The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred.(TRGO). + 3 + + + CompareOC1REF + OC1REF signal is used as trigger output (TRGO) + 4 + + + CompareOC2REF + OC2REF signal is used as trigger output (TRGO) + 5 + + + CompareOC3REF + OC3REF signal is used as trigger output (TRGO) + 6 + + + CompareOC4REF + OC4REF signal is used as trigger output (TRGO) + 7 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCxEvent + CCx DMA request sent when CCx event occurs + 0 + + + Update + CCx DMA requests sent when update event occurs + 1 + + + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + COMGBitOnly + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0 + + + COMGBit_Edge + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 1 + + + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + NotPreloaded + CCxE, CCxNE and OCxM bits are not preloaded + 0 + + + Preloaded + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a communication event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 1 + + + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + MSM + Master/Slave mode + 7 + 1 + + + NoAction + No action + 0 + + + Synchronization + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + 1 + + + + + TS + Trigger selection + 4 + 3 + + TS + + ITR0 + Internal Trigger 0 (ITR0) + 0 + + + ITR1 + Internal Trigger 1 (ITR1) + 1 + + + ITR2 + Internal Trigger 2 (ITR2) + 2 + + + ITR3 + Internal Trigger 3 (ITR3) + 3 + + + TI1F_ED + TI1 Edge Detector + 4 + + + TI1FP1 + Filtered Timer Input 1 + 5 + + + TI2FP2 + Filtered Timer Input 2 + 6 + + + (ETRF) + External Trigger input + 7 + + + + + SMS + Slave mode selection + 0 + 3 + + SMS + + Disabled + Counter disabled + 0 + + + EncoderTI2 + Encoder mode, count up/down on TI2FP1 + 1 + + + EncoderTI1 + Encoder mode, count up/down on TI1FP2 + 2 + + + EncoderTI1TI2 + Encoder mode, count up/down on both TI1FP1 and TI2FP2 + 3 + + + Reset + Rising edge of the selected trigger input (TRGI) reinitializes the counter + 4 + + + Gated + The counter clock is enabled when the trigger input (TRGI) is high + 5 + + + Trigger + The counter starts at a rising edge of the trigger TRGI + 6 + + + External + Rising edges of the selected trigger (TRGI) clock the counter + 7 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + DISABLED + Trigger DMA request disabled. + 0 + + + ENABLED + Trigger DMA request enabled. + 1 + + + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + DISABLED + CC2 DMA request disabled. + 0 + + + ENABLED + CC2 DMA request enabled. + 1 + + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + DISABLED + CC1 DMA request disabled. + 0 + + + ENABLED + CC1 DMA request enabled. + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + + DISABLED + Update DMA request disabled. + 0 + + + ENABLED + Update DMA request enabled. + 1 + + + + + BIE + Break interrupt enable + 7 + 1 + + + DISABLED + Break interrupt disabled. + 0 + + + ENABLED + Break interrupt enabled. + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + + DISABLED + Trigger interrupt disabled. + 0 + + + ENABLED + Trigger interrupt enabled. + 1 + + + + + COMIE + COM interrupt enable + 5 + 1 + + + DISABLED + COM interrupt disabled. + 0 + + + ENABLED + COM interrupt enabled. + 1 + + + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + DISABLED + CC2 interrupt disabled. + 0 + + + ENABLED + CC2 interrupt enabled. + 1 + + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + DISABLED + CC1 interrupt disabled. + 0 + + + ENABLED + CC1 interrupt enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + BIF + Break interrupt flag + 7 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + COMIF + COM interrupt flag + 5 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + NoAction + No action. + 0 + + + BreakEvent + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + TG + Trigger generation + 6 + 1 + + + TIFset + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CCupdate + When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits. + 1 + + + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + Generated + generate an event. + 1 + + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + Generated + generate an event. + 1 + + + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + Frozen + Frozen + 0 + + + CH2ActiveOnMatch + Set channel 2 to active level on match. OC2REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2). + 1 + + + CH2InactiveOnMatch + Set channel 2 to inactive level on match. + 2 + + + Toggle + Toggle - OC2REF toggles when TIMx_CNT=TIMx_CCR2. + 3 + + + ForcedLow + Force inactive level - OC2REF is forced low. + 4 + + + ForcedHigh + Force active level - OC2REF is forced high. + 5 + + + PWMMode1 + PWM Mode 1 + 6 + + + PWMMode2 + PWM Mode 2 + 7 + + + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + Disabled + Preload register on TIMx_CCR2 disabled. TIMx_CCR2 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR2 enabled. Read/Write operations access the preload register. TIMx_CCR2 preload value is loaded in the active register at each update event. + 1 + + + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + Disabled + CC2 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC2 output when an edge occurs on the trigger input is 5 clock cycles + 0 + + + Enabled + An active edge on the trigger input acts like a compare match on CC2 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC2 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs( + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWMMode1 + In upcounting, channel 1 is active. + 6 + + + PWMMode2 + In upcounting, channel y is inactive. + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 1 + + + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + DISABLED + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + CC2output + CC2 channel is configured as output + 0 + + + IC2mappedTI2 + CC2 channel is configured as input, IC2 is mapped on TI2 + 1 + + + IC2mappedTI1 + CC2 channel is configured as input, IC2 is mapped on TI1 + 2 + + + IC2mappedTRC + CC2 channel is configured as input, IC2 is mapped on TRC + 3 + + + + + IC1F + Input capture 1 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + DISABLED + Off + 0 + + + ENABLED + On + 1 + + + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + 0 + 255 + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + 0 + 65535 + + + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + 0 + 65535 + + + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + DISABLED + OC and OCN outputs are disabled or forced to idle state + 0 + + + ENABLED + OC and OCN outputs are enabled if their respective enable bits are set + 1 + + + + + AOE + Automatic output enable + 14 + 1 + + + DISABLED + MOE can be set only by software + 0 + + + ENABLED + MOE can be set by software or automatically at the next update event + 1 + + + + + BKP + Break polarity + 13 + 1 + + + ActiveLow + Break input BRK is active low + 0 + + + ActiveHigh + Break input BRK is active high + 1 + + + + + BKE + Break enable + 12 + 1 + + + Disabled + Break inputs (BRK and CCS clock failure event) disabled + 0 + + + Enabled + Break inputs (BRK and CCS clock failure event) enabled + 1 + + + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are enabled + 1 + + + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1 + 1 + + + + + LOCK + Lock configuration + 8 + 2 + + + LockOff + LOCK OFF - No bit is write protected. + 0 + + + LockLvl1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 1 + + + LockLvl2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 2 + + + LockLvl3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 3 + + + + + DTG + Dead-time generator setup + 0 + 8 + + + 0 + 255 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + 1transfert + 1 transfert. + 0 + + + 2transferts + 2 transferts. + 1 + + + 3transferts + 3 transferts. + 2 + + + 4transferts + 4 transferts. + 3 + + + 5transferts + 5 transferts. + 4 + + + 6transferts + 6 transferts. + 5 + + + 7transferts + 7 transferts. + 6 + + + 8transferts + 8 transferts. + 7 + + + 9transferts + 9 transferts. + 8 + + + 10transferts + 10 transferts. + 9 + + + 11transferts + 11 transferts. + 10 + + + 12transferts + 12 transferts. + 11 + + + 13transferts + 13 transferts. + 12 + + + 14transferts + 14 transferts. + 13 + + + 15transferts + 15 transferts. + 14 + + + 16transferts + 16 transferts. + 15 + + + 17transferts + 17 transferts. + 16 + + + 18transferts + 18 transferts. + 17 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM16 + General-purpose-timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + TIM16 global interrupt + 21 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Division ratio between the timer clock (CK_INT) frequency and sampling clock + 8 + 2 + + CKD + + Div1 + Clock is not divided + 0 + + + Div2 + Clock is divided by 2 + 1 + + + Div4 + Clock is divided by 4 + 2 + + + + + ARPE + Auto-reload preload enable + 7 + 1 + + + NotBuffered + TIMx_ARR register is not buffered + 0 + + + Buffered + TIMx_ARR register is buffered + 1 + + + + + OPM + One-pulse mode + 3 + 1 + + + Continuous + Counter is not stopped at update event + 0 + + + OnePulse + Counter stops counting at the next update event (clearing the CEN bit) + 1 + + + + + URS + Update request source + 2 + 1 + + + AnyEvent + Any of the events generate an update interrupt or DMA request if enabled + 0 + + + OnlyOverUnder + Only counter overflow/underflow generates an update interrupt or DMA request if enabled + 1 + + + + + UDIS + Update disable + 1 + 1 + + + ENABLED + UEV enabled. + 0 + + + DISABLED + UEV disabled. + 1 + + + + + CEN + Counter enable + 0 + 1 + + + Disabled + Counter disabled + 0 + + + Enabled + Counter enabled + 1 + + + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + Reset + OC1N=0 after a dead-time when MOE=0 + 0 + + + Set + OC1N=1 after a dead-time when MOE=0 + 1 + + + + + OIS1 + Output Idle state 1 + 8 + 1 + + + Reset + OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + 0 + + + Set + OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + 1 + + + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCxEvent + CCx DMA request sent when CCx event occurs + 0 + + + Update + CCx DMA requests sent when update event occurs + 1 + + + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + COMGBitOnly + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only + 0 + + + COMGBit_Edge + When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI + 1 + + + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + NotPreloaded + CCxE, CCxNE and OCxM bits are not preloaded + 0 + + + Preloaded + CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a communication event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). + 1 + + + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + DISABLED + Trigger DMA request disabled. + 0 + + + ENABLED + Trigger DMA request enabled. + 1 + + + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + DISABLED + CC1 DMA request disabled. + 0 + + + ENABLED + CC1 DMA request enabled. + 1 + + + + + UDE + Update DMA request enable + 8 + 1 + + + DISABLED + Update DMA request disabled. + 0 + + + ENABLED + Update DMA request enabled. + 1 + + + + + BIE + Break interrupt enable + 7 + 1 + + + DISABLED + Break interrupt disabled. + 0 + + + ENABLED + Break interrupt enabled. + 1 + + + + + TIE + Trigger interrupt enable + 6 + 1 + + + DISABLED + Trigger interrupt disabled. + 0 + + + ENABLED + Trigger interrupt enabled. + 1 + + + + + COMIE + COM interrupt enable + 5 + 1 + + + DISABLED + COM interrupt disabled. + 0 + + + ENABLED + COM interrupt enabled. + 1 + + + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + DISABLED + CC1 interrupt disabled. + 0 + + + ENABLED + CC1 interrupt enabled. + 1 + + + + + UIE + Update interrupt enable + 0 + 1 + + + DISABLED + Update interrupt disabled. + 0 + + + ENABLED + Update interrupt enabled. + 1 + + + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + BIF + Break interrupt flag + 7 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + TIF + Trigger interrupt flag + 6 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + COMIF + COM interrupt flag + 5 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CLEARED + Clear overcapture flag. + 0 + + + + + UIF + Update interrupt flag + 0 + 1 + + read + + NoUpdate + No update occurred + 0 + + + Pending + Update interrupt pending + 1 + + + + write + + Clear + Clears the update interrupt flag + 0 + + + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + NoAction + No action. + 0 + + + BreakEvent + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + TG + Trigger generation + 6 + 1 + + + TIFset + The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. + 1 + + + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CCupdate + When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits. + 1 + + + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + Generated + generate an event. + 1 + + + + + UG + Update generation + 0 + 1 + + + RST_Update + Reinitialize the counter and generates an update of the registers. + 1 + + + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + OC1M + + Frozen + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + 0 + + + SetActive + Set channel y to active level on match. OCyREF signal is forced high when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 1 + + + SetInactive + Set channel y to inactive level on match. OCyREF signal is forced low when the counter TIMx_CNT matches the capture/compare register y (TIMx_CCRy). + 2 + + + Toggle + OCyREF toggles when TIMx_CNT=TIMx_CCRy. + 3 + + + ForceInactive + OCyREF is forced low. + 4 + + + ForceActive + OCyREF is forced high. + 5 + + + PWMMode1 + In upcounting, channel 1 is active. + 6 + + + PWMMode2 + In upcounting, channel y is inactive. + 7 + + + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + Disabled + Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately + 0 + + + Enabled + Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. + 1 + + + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + DISABLED + CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. + 0 + + + ENABLED + An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. + 1 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + NoFilter + No filter, sampling is done at fDTS + 0 + + + fCK_INT_N2 + fSAMPLING = fCK_INT, N = 2 + 1 + + + fCK_INT_N4 + fSAMPLING = fCK_INT, N = 4 + 2 + + + fCK_INT_N8 + fSAMPLING = fCK_INT, N = 8 + 3 + + + fDTSdiv2_N6 + fSAMPLING = fDTS / 2, N = 6 + 4 + + + fDTSdiv2_N8 + fSAMPLING = fDTS / 2, N = 8 + 5 + + + fDTSdiv4_N6 + fSAMPLING = fDTS / 4, N = 6 + 6 + + + fDTSdiv4_N8 + fSAMPLING = fDTS / 4, N = 8 + 7 + + + fDTSdiv8_N6 + fSAMPLING = fDTS / 8, N = 6 + 8 + + + fDTSdiv8_N8 + fSAMPLING = fDTS / 8, N = 8 + 9 + + + fDTSdiv16_N5 + fSAMPLING = fDTS / 16, N = 5 + 10 + + + fDTSdiv16_N6 + fSAMPLING = fDTS / 16, N = 6 + 11 + + + fDTSdiv16_N8 + fSAMPLING = fDTS / 16, N = 8 + 12 + + + fDTSdiv32_N5 + fSAMPLING = fDTS / 32, N = 5 + 13 + + + fDTSdiv32_N6 + fSAMPLING = fDTS / 32, N = 6 + 14 + + + fDTSdiv32_N8 + fSAMPLING = fDTS / 32, N = 8 + 15 + + + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + No + no prescaler, capture is done each time an edge is detected on the capture input + 0 + + + 2events + capture is done once every 2 events + 1 + + + 4events + capture is done once every 4 events + 2 + + + 8events + capture is done once every 8 events + 3 + + + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + CC1output + CC1 channel is configured as output + 0 + + + IC1mappedTI1 + CC1 channel is configured as input, IC1 is mapped on TI1 + 1 + + + IC1mappedTI2 + CC1 channel is configured as input, IC1 is mapped on TI2 + 2 + + + IC1mappedTRC + CC1 channel is configured as input, IC1 is mapped on TRC + 3 + + + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + DISABLED + Off + 0 + + + ENABLED + On + 1 + + + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + HIGH + active high + 0 + + + LOW + active low + 1 + + + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + Inactive + Output : OC1 is not active - Input : Capture disabled + 0 + + + Active + Output : OC1 signal is output on the corresponding output pin - Input : Capture enabled + 1 + + + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + 0 + 65535 + + + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + 0 + 65535 + + + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + 0 + 65535 + + + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + 0 + 255 + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + 0 + 65535 + + + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + DISABLED + OC and OCN outputs are disabled or forced to idle state + 0 + + + ENABLED + OC and OCN outputs are enabled if their respective enable bits are set + 1 + + + + + AOE + Automatic output enable + 14 + 1 + + + DISABLED + MOE can be set only by software + 0 + + + ENABLED + MOE can be set by software or automatically at the next update event + 1 + + + + + BKP + Break polarity + 13 + 1 + + + ActiveLow + Break input BRK is active low + 0 + + + ActiveHigh + Break input BRK is active high + 1 + + + + + BKE + Break enable + 12 + 1 + + + Disabled + Break inputs (BRK and CCS clock failure event) disabled + 0 + + + Enabled + Break inputs (BRK and CCS clock failure event) enabled + 1 + + + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are enabled + 1 + + + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + Disabled + When inactive, OC/OCN outputs are disabled + 0 + + + Enabled + When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1 + 1 + + + + + LOCK + Lock configuration + 8 + 2 + + + LockOff + LOCK OFF - No bit is write protected. + 0 + + + LockLvl1 + LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + 1 + + + LockLvl2 + LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + 2 + + + LockLvl3 + LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + 3 + + + + + DTG + Dead-time generator setup + 0 + 8 + + + 0 + 255 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + 1transfert + 1 transfert. + 0 + + + 2transferts + 2 transferts. + 1 + + + 3transferts + 3 transferts. + 2 + + + 4transferts + 4 transferts. + 3 + + + 5transferts + 5 transferts. + 4 + + + 6transferts + 6 transferts. + 5 + + + 7transferts + 7 transferts. + 6 + + + 8transferts + 8 transferts. + 7 + + + 9transferts + 9 transferts. + 8 + + + 10transferts + 10 transferts. + 9 + + + 11transferts + 11 transferts. + 10 + + + 12transferts + 12 transferts. + 11 + + + 13transferts + 13 transferts. + 12 + + + 14transferts + 14 transferts. + 13 + + + 15transferts + 15 transferts. + 14 + + + 16transferts + 16 transferts. + 15 + + + 17transferts + 17 transferts. + 16 + + + 18transferts + 18 transferts. + 17 + + + + + DBA + DMA base address + 0 + 5 + + + 0 + 31 + + + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + 0 + 65535 + + + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global interrupt + 22 + + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + TSC + Touch sensing interrupt + 8 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin + polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller + enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt + enable + 1 + 1 + + + EOAIE + End of acquisition interrupt + enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt + clear + 1 + 1 + + + EOAIC + End of acquisition interrupt + clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-write + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control + register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G6_IO4 + G6_IO4 Schmitt trigger hysteresis + mode + 23 + 1 + + + G6_IO3 + G6_IO3 Schmitt trigger hysteresis + mode + 22 + 1 + + + G6_IO2 + G6_IO2 Schmitt trigger hysteresis + mode + 21 + 1 + + + G6_IO1 + G6_IO1 Schmitt trigger hysteresis + mode + 20 + 1 + + + G5_IO4 + G5_IO4 Schmitt trigger hysteresis + mode + 19 + 1 + + + G5_IO3 + G5_IO3 Schmitt trigger hysteresis + mode + 18 + 1 + + + G5_IO2 + G5_IO2 Schmitt trigger hysteresis + mode + 17 + 1 + + + G5_IO1 + G5_IO1 Schmitt trigger hysteresis + mode + 16 + 1 + + + G4_IO4 + G4_IO4 Schmitt trigger hysteresis + mode + 15 + 1 + + + G4_IO3 + G4_IO3 Schmitt trigger hysteresis + mode + 14 + 1 + + + G4_IO2 + G4_IO2 Schmitt trigger hysteresis + mode + 13 + 1 + + + G4_IO1 + G4_IO1 Schmitt trigger hysteresis + mode + 12 + 1 + + + G3_IO4 + G3_IO4 Schmitt trigger hysteresis + mode + 11 + 1 + + + G3_IO3 + G3_IO3 Schmitt trigger hysteresis + mode + 10 + 1 + + + G3_IO2 + G3_IO2 Schmitt trigger hysteresis + mode + 9 + 1 + + + G3_IO1 + G3_IO1 Schmitt trigger hysteresis + mode + 8 + 1 + + + G2_IO4 + G2_IO4 Schmitt trigger hysteresis + mode + 7 + 1 + + + G2_IO3 + G2_IO3 Schmitt trigger hysteresis + mode + 6 + 1 + + + G2_IO2 + G2_IO2 Schmitt trigger hysteresis + mode + 5 + 1 + + + G2_IO1 + G2_IO1 Schmitt trigger hysteresis + mode + 4 + 1 + + + G1_IO4 + G1_IO4 Schmitt trigger hysteresis + mode + 3 + 1 + + + G1_IO3 + G1_IO3 Schmitt trigger hysteresis + mode + 2 + 1 + + + G1_IO2 + G1_IO2 Schmitt trigger hysteresis + mode + 1 + 1 + + + G1_IO1 + G1_IO1 Schmitt trigger hysteresis + mode + 0 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G6_IO4 + G6_IO4 analog switch + enable + 23 + 1 + + + G6_IO3 + G6_IO3 analog switch + enable + 22 + 1 + + + G6_IO2 + G6_IO2 analog switch + enable + 21 + 1 + + + G6_IO1 + G6_IO1 analog switch + enable + 20 + 1 + + + G5_IO4 + G5_IO4 analog switch + enable + 19 + 1 + + + G5_IO3 + G5_IO3 analog switch + enable + 18 + 1 + + + G5_IO2 + G5_IO2 analog switch + enable + 17 + 1 + + + G5_IO1 + G5_IO1 analog switch + enable + 16 + 1 + + + G4_IO4 + G4_IO4 analog switch + enable + 15 + 1 + + + G4_IO3 + G4_IO3 analog switch + enable + 14 + 1 + + + G4_IO2 + G4_IO2 analog switch + enable + 13 + 1 + + + G4_IO1 + G4_IO1 analog switch + enable + 12 + 1 + + + G3_IO4 + G3_IO4 analog switch + enable + 11 + 1 + + + G3_IO3 + G3_IO3 analog switch + enable + 10 + 1 + + + G3_IO2 + G3_IO2 analog switch + enable + 9 + 1 + + + G3_IO1 + G3_IO1 analog switch + enable + 8 + 1 + + + G2_IO4 + G2_IO4 analog switch + enable + 7 + 1 + + + G2_IO3 + G2_IO3 analog switch + enable + 6 + 1 + + + G2_IO2 + G2_IO2 analog switch + enable + 5 + 1 + + + G2_IO1 + G2_IO1 analog switch + enable + 4 + 1 + + + G1_IO4 + G1_IO4 analog switch + enable + 3 + 1 + + + G1_IO3 + G1_IO3 analog switch + enable + 2 + 1 + + + G1_IO2 + G1_IO2 analog switch + enable + 1 + 1 + + + G1_IO1 + G1_IO1 analog switch + enable + 0 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G6_IO4 + G6_IO4 sampling mode + 23 + 1 + + + G6_IO3 + G6_IO3 sampling mode + 22 + 1 + + + G6_IO2 + G6_IO2 sampling mode + 21 + 1 + + + G6_IO1 + G6_IO1 sampling mode + 20 + 1 + + + G5_IO4 + G5_IO4 sampling mode + 19 + 1 + + + G5_IO3 + G5_IO3 sampling mode + 18 + 1 + + + G5_IO2 + G5_IO2 sampling mode + 17 + 1 + + + G5_IO1 + G5_IO1 sampling mode + 16 + 1 + + + G4_IO4 + G4_IO4 sampling mode + 15 + 1 + + + G4_IO3 + G4_IO3 sampling mode + 14 + 1 + + + G4_IO2 + G4_IO2 sampling mode + 13 + 1 + + + G4_IO1 + G4_IO1 sampling mode + 12 + 1 + + + G3_IO4 + G3_IO4 sampling mode + 11 + 1 + + + G3_IO3 + G3_IO3 sampling mode + 10 + 1 + + + G3_IO2 + G3_IO2 sampling mode + 9 + 1 + + + G3_IO1 + G3_IO1 sampling mode + 8 + 1 + + + G2_IO4 + G2_IO4 sampling mode + 7 + 1 + + + G2_IO3 + G2_IO3 sampling mode + 6 + 1 + + + G2_IO2 + G2_IO2 sampling mode + 5 + 1 + + + G2_IO1 + G2_IO1 sampling mode + 4 + 1 + + + G1_IO4 + G1_IO4 sampling mode + 3 + 1 + + + G1_IO3 + G1_IO3 sampling mode + 2 + 1 + + + G1_IO2 + G1_IO2 sampling mode + 1 + 1 + + + G1_IO1 + G1_IO1 sampling mode + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G6_IO4 + G6_IO4 channel mode + 23 + 1 + + + G6_IO3 + G6_IO3 channel mode + 22 + 1 + + + G6_IO2 + G6_IO2 channel mode + 21 + 1 + + + G6_IO1 + G6_IO1 channel mode + 20 + 1 + + + G5_IO4 + G5_IO4 channel mode + 19 + 1 + + + G5_IO3 + G5_IO3 channel mode + 18 + 1 + + + G5_IO2 + G5_IO2 channel mode + 17 + 1 + + + G5_IO1 + G5_IO1 channel mode + 16 + 1 + + + G4_IO4 + G4_IO4 channel mode + 15 + 1 + + + G4_IO3 + G4_IO3 channel mode + 14 + 1 + + + G4_IO2 + G4_IO2 channel mode + 13 + 1 + + + G4_IO1 + G4_IO1 channel mode + 12 + 1 + + + G3_IO4 + G3_IO4 channel mode + 11 + 1 + + + G3_IO3 + G3_IO3 channel mode + 10 + 1 + + + G3_IO2 + G3_IO2 channel mode + 9 + 1 + + + G3_IO1 + G3_IO1 channel mode + 8 + 1 + + + G2_IO4 + G2_IO4 channel mode + 7 + 1 + + + G2_IO3 + G2_IO3 channel mode + 6 + 1 + + + G2_IO2 + G2_IO2 channel mode + 5 + 1 + + + G2_IO1 + G2_IO1 channel mode + 4 + 1 + + + G1_IO4 + G1_IO4 channel mode + 3 + 1 + + + G1_IO3 + G1_IO3 channel mode + 2 + 1 + + + G1_IO2 + G1_IO2 channel mode + 1 + 1 + + + G1_IO1 + G1_IO1 channel mode + 0 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-write + + + G7S + Analog I/O group x status + 22 + 1 + read-write + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + CEC + HDMI-CEC controller + CEC + 0x40007800 + + 0x0 + 0x400 + registers + + + CEC_CAN + CEC and CAN global interrupt + 30 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + TXEOM + Tx End Of Message + 2 + 1 + + + TXSOM + Tx start of message + 1 + 1 + + + CECEN + CEC Enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + LBPEGEN + Generate Error-Bit on Long Bit Period + Error + 11 + 1 + + + BREGEN + Generate error-bit on bit rising + error + 10 + 1 + + + BRESTP + Rx-stop on bit rising + error + 9 + 1 + + + RXTOL + Rx-Tolerance + 8 + 1 + + + SFT + Signal Free Time + 5 + 3 + + + LSTN + Listen mode + 4 + 1 + + + OAR + Own Address + 0 + 4 + + + + + TXDR + TXDR + Tx data register + 0x8 + 0x20 + write-only + 0x00000000 + + + TXD + Tx Data register + 0 + 8 + + + 0 + 255 + + + + + + + RXDR + RXDR + Rx Data Register + 0xC + 0x20 + read-only + 0x00000000 + + + RXDR + CEC Rx Data Register + 0 + 8 + + + 0 + 255 + + + + + + + ISR + ISR + Interrupt and Status Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXACKE + Tx-Missing acknowledge + error + 12 + 1 + + + TXERR + Tx-Error + 11 + 1 + + + TXUDR + Tx-Buffer Underrun + 10 + 1 + + + TXEND + End of Transmission + 9 + 1 + + + TXBR + Tx-Byte Request + 8 + 1 + + + ARBLST + Arbitration Lost + 7 + 1 + + + RXACKE + Rx-Missing Acknowledge + 6 + 1 + + + LBPE + Rx-Long Bit Period Error + 5 + 1 + + + SBPE + Rx-Short Bit period error + 4 + 1 + + + BRE + Rx-Bit rising error + 3 + 1 + + + RXOVR + Rx-Overrun + 2 + 1 + + + RXEND + End Of Reception + 1 + 1 + + + RXBR + Rx-Byte Received + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt + Enable + 12 + 1 + + + TXERRIE + Tx-Error Interrupt Enable + 11 + 1 + + + TXUDRIE + Tx-Underrun interrupt + enable + 10 + 1 + + + TXENDIE + Tx-End of message interrupt + enable + 9 + 1 + + + TXBRIE + Tx-Byte Request Interrupt + Enable + 8 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt + Enable + 7 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt + Enable + 6 + 1 + + + LBPEIE + Long Bit Period Error Interrupt + Enable + 5 + 1 + + + SBPEIE + Short Bit Period Error Interrupt + Enable + 4 + 1 + + + BREIE + Bit Rising Error Interrupt + Enable + 3 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt + Enable + 2 + 1 + + + RXENDIE + End Of Reception Interrupt + Enable + 1 + 1 + + + RXBRIE + Rx-Byte Received Interrupt + Enable + 0 + 1 + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + LATENCY + 0 + 3 + read-write + + + 0WaitState + Zero wait state, if SYSCLK is below or equal to 24 MHz. + 0 + + + 1WaitState + One wait state, if SYSCLK is greater 24MHz and below or equal to 48 MHz. + 1 + + + + + PRFTBE + PRFTBE + 4 + 1 + read-write + + + Disabled + Prefetch is disabled. + 0 + + + Enabled + Prefetch is enabled. + 1 + + + + + PRFTBS + PRFTBS + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + FKEYR + Flash Key + 0 + 32 + + + 0 + 4294967295 + + + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + 0 + 4294967295 + + + + + + + SR + SR + Flash status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRT + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Flash control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FORCE_OPTLOAD + Force option byte loading + 13 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + LOCK + Lock + 7 + 1 + + + STRT + Start + 6 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash address + 0 + 32 + + + 0 + 4294967295 + + + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFF2 + + + OPTERR + Option byte error + 0 + 1 + + + RDPRT + Read protection level + status + 1 + 2 + + + WDG_SW + WDG_SW + 8 + 1 + + + nRST_STOP + nRST_STOP + 9 + 1 + + + nRST_STDBY + nRST_STDBY + 10 + 1 + + + nBOOT0 + nBOOT0 + 11 + 1 + + + nBOOT1 + BOOT1 + 12 + 1 + + + VDDA_MONITOR + VDDA_MONITOR + 13 + 1 + + + RAM_PARITY_CHECK + RAM_PARITY_CHECK + 14 + 1 + + + BOOT_SEL + BOOT_SEL + 15 + 1 + + + Data0 + Data0 + 16 + 8 + + + 0 + 255 + + + + + Data1 + Data1 + 24 + 8 + + + 0 + 255 + + + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + 0 + 4294967295 + + + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + DIV_ID + Division Identifier + 12 + 4 + + + REV_ID + Revision Identifier + 16 + 16 + read + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + + + APB1_FZ + APB1_FZ + Debug MCU APB1 freeze register + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIM2_STOP + TIM2 counter stopped when core is + halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM6_STOP + TIM6 counter stopped when core is + halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is + halted + 5 + 1 + + + DBG_TIM14_STOP + TIM14 counter stopped when core is + halted + 8 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug window watchdog stopped when core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug independent watchdog stopped when + core is halted + 12 + 1 + + + DBG_I2C1_SMBUS_TIMEOUT + SMBUS timeout mode stopped when core is + halted + 21 + 1 + + + DBG_CAN_STOP + CAN stopped when core is + halted + 25 + 1 + + + + + APB2_FZ + APB2_FZ + Debug MCU APB2 freeze register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 11 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is + halted + 18 + 1 + + + + + + + USB + Universal serial bus full-speed device + interface + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + USB + USB global interrupt + 31 + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + CNTR + CNTR + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + L1RESUME + LPM L1 Resume request + 5 + 1 + + + L1REQM + LPM L1 state request interrupt + mask + 7 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + read-only + + + DIR + Direction of transaction + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + 7 + 1 + read-write + + + ESOF + Expected start frame + 8 + 1 + read-write + + + SOF + start of frame + 9 + 1 + read-write + + + RESET + reset request + 10 + 1 + read-write + + + SUSP + Suspend mode request + 11 + 1 + read-write + + + WKUP + Wakeup + 12 + 1 + read-write + + + ERR + Error + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + read-write + + + CTR + Correct transfer + 15 + 1 + read-only + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + LPMCSR + LPMCSR + LPM control and status + register + 0x54 + 0x20 + 0x0000 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM Token acknowledge + enable + 1 + 1 + read-write + + + REMWAKE + bRemoteWake value + 3 + 1 + read-only + + + BESL + BESL value + 4 + 4 + read-only + + + + + BCDR + BCDR + Battery charging detector + 0x58 + 0x20 + 0x0000 + + + BCDEN + Battery charging detector (BCD) + enable + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode + enable + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode + enable + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode + enable + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) + status + 4 + 1 + read-only + + + PDET + Primary detection (PD) + status + 5 + 1 + read-only + + + SDET + Secondary detection (SD) + status + 6 + 1 + read-only + + + PS2DET + DM pull-up detection + status + 7 + 1 + read-only + + + DPPU + DP pull-up control + 15 + 1 + read-write + + + + + + + CRS + Clock recovery system + CRS + 0x40006C00 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TRIM + HSI48 oscillator smooth + trimming + 8 + 6 + + + SWSYNC + Generate software SYNC + event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter + enable + 5 + 1 + + + Disabled + Frequency error counter disabled + 0 + + + Enabled + Frequency error counter enabled + 1 + + + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source + selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + 0 + 255 + + + + + RELOAD + Counter reload value + 0 + 16 + + + 0 + 65535 + + + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + 0 + 65535 + + + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or + underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + CAN + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + + CAN_MCR + CAN_MCR + CAN_MCR + 0x0 + 0x20 + read-write + 0x00000000 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + CAN_MSR + CAN_MSR + CAN_MSR + 0x4 + 0x20 + 0x00000000 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + CAN_TSR + CAN_TSR + CAN_TSR + 0x8 + 0x20 + 0x00000000 + + + LOW2 + Lowest priority flag for mailbox + 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox + 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox + 0 + 29 + 1 + read-only + + + TME2 + Lowest priority flag for mailbox + 2 + 28 + 1 + read-only + + + TME1 + Lowest priority flag for mailbox + 1 + 27 + 1 + read-only + + + TME0 + Lowest priority flag for mailbox + 0 + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 1 + read-write + + + ALST1 + ALST1 + 10 + 1 + read-write + + + TXOK1 + TXOK1 + 9 + 1 + read-write + + + RQCP1 + RQCP1 + 8 + 1 + read-write + + + ABRQ0 + ABRQ0 + 7 + 1 + read-write + + + TERR0 + TERR0 + 3 + 1 + read-write + + + ALST0 + ALST0 + 2 + 1 + read-write + + + TXOK0 + TXOK0 + 1 + 1 + read-write + + + RQCP0 + RQCP0 + 0 + 1 + read-write + + + + + CAN_RF0R + CAN_RF0R + CAN_RF0R + 0xC + 0x20 + 0x00000000 + + + RFOM0 + RFOM0 + 5 + 1 + read-write + + + FOVR0 + FOVR0 + 4 + 1 + read-write + + + FULL0 + FULL0 + 3 + 1 + read-write + + + FMP0 + FMP0 + 0 + 2 + read-only + + + + + CAN_RF1R + CAN_RF1R + CAN_RF1R + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + RFOM1 + 5 + 1 + read-write + + + FOVR1 + FOVR1 + 4 + 1 + read-write + + + FULL1 + FULL1 + 3 + 1 + read-write + + + FMP1 + FMP1 + 0 + 2 + read-only + + + + + CAN_IER + CAN_IER + CAN_IER + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + SLKIE + 17 + 1 + + + WKUIE + WKUIE + 16 + 1 + + + ERRIE + ERRIE + 15 + 1 + + + LECIE + LECIE + 11 + 1 + + + BOFIE + BOFIE + 10 + 1 + + + EPVIE + EPVIE + 9 + 1 + + + EWGIE + EWGIE + 8 + 1 + + + FOVIE1 + FOVIE1 + 6 + 1 + + + FFIE1 + FFIE1 + 5 + 1 + + + FMPIE1 + FMPIE1 + 4 + 1 + + + FOVIE0 + FOVIE0 + 3 + 1 + + + FFIE0 + FFIE0 + 2 + 1 + + + FMPIE0 + FMPIE0 + 1 + 1 + + + TMEIE + TMEIE + 0 + 1 + + + + + CAN_ESR + CAN_ESR + CAN_ESR + 0x18 + 0x20 + 0x00000000 + + + REC + REC + 24 + 8 + read-only + + + TEC + TEC + 16 + 8 + read-only + + + LEC + LEC + 4 + 3 + read-write + + + BOFF + BOFF + 2 + 1 + read-only + + + EPVF + EPVF + 1 + 1 + read-only + + + EWGF + EWGF + 0 + 1 + read-only + + + + + CAN_BTR + CAN_BTR + CAN BTR + 0x1C + 0x20 + read-write + 0x00000000 + + + SILM + SILM + 31 + 1 + + + LBKM + LBKM + 30 + 1 + + + SJW + SJW + 24 + 2 + + + TS2 + TS2 + 20 + 3 + + + TS1 + TS1 + 16 + 4 + + + BRP + BRP + 0 + 10 + + + + + CAN_TI0R + CAN_TI0R + CAN_TI0R + 0x180 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + CAN_TDT0R + CAN_TDT0R + CAN_TDT0R + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + 0 + 65535 + + + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + CAN_TDL0R + CAN_TDL0R + CAN_TDL0R + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + 0 + 255 + + + + + DATA2 + DATA2 + 16 + 8 + + + 0 + 255 + + + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + CAN_TDH0R + CAN_TDH0R + CAN_TDH0R + 0x18C + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + CAN_TI1R + CAN_TI1R + CAN_TI1R + 0x190 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + CAN_TDT1R + CAN_TDT1R + CAN_TDT1R + 0x194 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + 0 + 65535 + + + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + CAN_TDL1R + CAN_TDL1R + CAN_TDL1R + 0x198 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + CAN_TDH1R + CAN_TDH1R + CAN_TDH1R + 0x19C + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + CAN_TI2R + CAN_TI2R + CAN_TI2R + 0x1A0 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + CAN_TDT2R + CAN_TDT2R + CAN_TDT2R + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + 0 + 65535 + + + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + CAN_TDL2R + CAN_TDL2R + CAN_TDL2R + 0x1A8 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + CAN_TDH2R + CAN_TDH2R + CAN_TDH2R + 0x1AC + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + CAN_RI0R + CAN_RI0R + CAN_RI0R + 0x1B0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + + + CAN_RDT0R + CAN_RDT0R + CAN_RDT0R + 0x1B4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + 0 + 65535 + + + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + + + CAN_RDL0R + CAN_RDL0R + CAN_RDL0R + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + CAN_RDH0R + CAN_RDH0R + CAN_RDH0R + 0x1BC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + CAN_RI1R + CAN_RI1R + CAN_RI1R + 0x1C0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + + + CAN_RDT1R + CAN_RDT1R + CAN_RDT1R + 0x1C4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + 0 + 65535 + + + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + + + CAN_RDL1R + CAN_RDL1R + CAN_RDL1R + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + CAN_RDH1R + CAN_RDH1R + CAN_RDH1R + 0x1CC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + CAN_FMR + CAN_FMR + CAN_FMR + 0x200 + 0x20 + read-write + 0x00000000 + + + CAN2SB + CAN2SB + 8 + 6 + + + FINIT + FINIT + 0 + 1 + + + + + CAN_FM1R + CAN_FM1R + CAN_FM1R + 0x204 + 0x20 + read-write + 0x00000000 + + + FBM0 + Filter mode + 0 + 1 + + + FBM1 + Filter mode + 1 + 1 + + + FBM2 + Filter mode + 2 + 1 + + + FBM3 + Filter mode + 3 + 1 + + + FBM4 + Filter mode + 4 + 1 + + + FBM5 + Filter mode + 5 + 1 + + + FBM6 + Filter mode + 6 + 1 + + + FBM7 + Filter mode + 7 + 1 + + + FBM8 + Filter mode + 8 + 1 + + + FBM9 + Filter mode + 9 + 1 + + + FBM10 + Filter mode + 10 + 1 + + + FBM11 + Filter mode + 11 + 1 + + + FBM12 + Filter mode + 12 + 1 + + + FBM13 + Filter mode + 13 + 1 + + + FBM14 + Filter mode + 14 + 1 + + + FBM15 + Filter mode + 15 + 1 + + + FBM16 + Filter mode + 16 + 1 + + + FBM17 + Filter mode + 17 + 1 + + + FBM18 + Filter mode + 18 + 1 + + + FBM19 + Filter mode + 19 + 1 + + + FBM20 + Filter mode + 20 + 1 + + + FBM21 + Filter mode + 21 + 1 + + + FBM22 + Filter mode + 22 + 1 + + + FBM23 + Filter mode + 23 + 1 + + + FBM24 + Filter mode + 24 + 1 + + + FBM25 + Filter mode + 25 + 1 + + + FBM26 + Filter mode + 26 + 1 + + + FBM27 + Filter mode + 27 + 1 + + + + + CAN_FS1R + CAN_FS1R + CAN_FS1R + 0x20C + 0x20 + read-write + 0x00000000 + + + FSC0 + Filter scale configuration + 0 + 1 + + + FSC1 + Filter scale configuration + 1 + 1 + + + FSC2 + Filter scale configuration + 2 + 1 + + + FSC3 + Filter scale configuration + 3 + 1 + + + FSC4 + Filter scale configuration + 4 + 1 + + + FSC5 + Filter scale configuration + 5 + 1 + + + FSC6 + Filter scale configuration + 6 + 1 + + + FSC7 + Filter scale configuration + 7 + 1 + + + FSC8 + Filter scale configuration + 8 + 1 + + + FSC9 + Filter scale configuration + 9 + 1 + + + FSC10 + Filter scale configuration + 10 + 1 + + + FSC11 + Filter scale configuration + 11 + 1 + + + FSC12 + Filter scale configuration + 12 + 1 + + + FSC13 + Filter scale configuration + 13 + 1 + + + FSC14 + Filter scale configuration + 14 + 1 + + + FSC15 + Filter scale configuration + 15 + 1 + + + FSC16 + Filter scale configuration + 16 + 1 + + + FSC17 + Filter scale configuration + 17 + 1 + + + FSC18 + Filter scale configuration + 18 + 1 + + + FSC19 + Filter scale configuration + 19 + 1 + + + FSC20 + Filter scale configuration + 20 + 1 + + + FSC21 + Filter scale configuration + 21 + 1 + + + FSC22 + Filter scale configuration + 22 + 1 + + + FSC23 + Filter scale configuration + 23 + 1 + + + FSC24 + Filter scale configuration + 24 + 1 + + + FSC25 + Filter scale configuration + 25 + 1 + + + FSC26 + Filter scale configuration + 26 + 1 + + + FSC27 + Filter scale configuration + 27 + 1 + + + + + CAN_FFA1R + CAN_FFA1R + CAN_FFA1R + 0x214 + 0x20 + read-write + 0x00000000 + + + FFA0 + Filter FIFO assignment for filter + 0 + 0 + 1 + + + FFA1 + Filter FIFO assignment for filter + 1 + 1 + 1 + + + FFA2 + Filter FIFO assignment for filter + 2 + 2 + 1 + + + FFA3 + Filter FIFO assignment for filter + 3 + 3 + 1 + + + FFA4 + Filter FIFO assignment for filter + 4 + 4 + 1 + + + FFA5 + Filter FIFO assignment for filter + 5 + 5 + 1 + + + FFA6 + Filter FIFO assignment for filter + 6 + 6 + 1 + + + FFA7 + Filter FIFO assignment for filter + 7 + 7 + 1 + + + FFA8 + Filter FIFO assignment for filter + 8 + 8 + 1 + + + FFA9 + Filter FIFO assignment for filter + 9 + 9 + 1 + + + FFA10 + Filter FIFO assignment for filter + 10 + 10 + 1 + + + FFA11 + Filter FIFO assignment for filter + 11 + 11 + 1 + + + FFA12 + Filter FIFO assignment for filter + 12 + 12 + 1 + + + FFA13 + Filter FIFO assignment for filter + 13 + 13 + 1 + + + FFA14 + Filter FIFO assignment for filter + 14 + 14 + 1 + + + FFA15 + Filter FIFO assignment for filter + 15 + 15 + 1 + + + FFA16 + Filter FIFO assignment for filter + 16 + 16 + 1 + + + FFA17 + Filter FIFO assignment for filter + 17 + 17 + 1 + + + FFA18 + Filter FIFO assignment for filter + 18 + 18 + 1 + + + FFA19 + Filter FIFO assignment for filter + 19 + 19 + 1 + + + FFA20 + Filter FIFO assignment for filter + 20 + 20 + 1 + + + FFA21 + Filter FIFO assignment for filter + 21 + 21 + 1 + + + FFA22 + Filter FIFO assignment for filter + 22 + 22 + 1 + + + FFA23 + Filter FIFO assignment for filter + 23 + 23 + 1 + + + FFA24 + Filter FIFO assignment for filter + 24 + 24 + 1 + + + FFA25 + Filter FIFO assignment for filter + 25 + 25 + 1 + + + FFA26 + Filter FIFO assignment for filter + 26 + 26 + 1 + + + FFA27 + Filter FIFO assignment for filter + 27 + 27 + 1 + + + + + CAN_FA1R + CAN_FA1R + CAN_FA1R + 0x21C + 0x20 + read-write + 0x00000000 + + + FACT0 + Filter active + 0 + 1 + + + FACT1 + Filter active + 1 + 1 + + + FACT2 + Filter active + 2 + 1 + + + FACT3 + Filter active + 3 + 1 + + + FACT4 + Filter active + 4 + 1 + + + FACT5 + Filter active + 5 + 1 + + + FACT6 + Filter active + 6 + 1 + + + FACT7 + Filter active + 7 + 1 + + + FACT8 + Filter active + 8 + 1 + + + FACT9 + Filter active + 9 + 1 + + + FACT10 + Filter active + 10 + 1 + + + FACT11 + Filter active + 11 + 1 + + + FACT12 + Filter active + 12 + 1 + + + FACT13 + Filter active + 13 + 1 + + + FACT14 + Filter active + 14 + 1 + + + FACT15 + Filter active + 15 + 1 + + + FACT16 + Filter active + 16 + 1 + + + FACT17 + Filter active + 17 + 1 + + + FACT18 + Filter active + 18 + 1 + + + FACT19 + Filter active + 19 + 1 + + + FACT20 + Filter active + 20 + 1 + + + FACT21 + Filter active + 21 + 1 + + + FACT22 + Filter active + 22 + 1 + + + FACT23 + Filter active + 23 + 1 + + + FACT24 + Filter active + 24 + 1 + + + FACT25 + Filter active + 25 + 1 + + + FACT26 + Filter active + 26 + 1 + + + FACT27 + Filter active + 27 + 1 + + + + + F0R1 + F0R1 + Filter bank 0 register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F0R2 + F0R2 + Filter bank 0 register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R1 + F1R1 + Filter bank 1 register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R2 + F1R2 + Filter bank 1 register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R1 + F2R1 + Filter bank 2 register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R2 + F2R2 + Filter bank 2 register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R1 + F3R1 + Filter bank 3 register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R2 + F3R2 + Filter bank 3 register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R1 + F4R1 + Filter bank 4 register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R2 + F4R2 + Filter bank 4 register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R1 + F5R1 + Filter bank 5 register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R2 + F5R2 + Filter bank 5 register 2 + 0x26C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R1 + F6R1 + Filter bank 6 register 1 + 0x270 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R2 + F6R2 + Filter bank 6 register 2 + 0x274 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R1 + F7R1 + Filter bank 7 register 1 + 0x278 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R2 + F7R2 + Filter bank 7 register 2 + 0x27C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R1 + F8R1 + Filter bank 8 register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R2 + F8R2 + Filter bank 8 register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R1 + F9R1 + Filter bank 9 register 1 + 0x288 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R2 + F9R2 + Filter bank 9 register 2 + 0x28C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R1 + F10R1 + Filter bank 10 register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R2 + F10R2 + Filter bank 10 register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R1 + F11R1 + Filter bank 11 register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R2 + F11R2 + Filter bank 11 register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R1 + F12R1 + Filter bank 4 register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R2 + F12R2 + Filter bank 12 register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R1 + F13R1 + Filter bank 13 register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R2 + F13R2 + Filter bank 13 register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R1 + F14R1 + Filter bank 14 register 1 + 0x2B0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R2 + F14R2 + Filter bank 14 register 2 + 0x2B4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R1 + F15R1 + Filter bank 15 register 1 + 0x2B8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R2 + F15R2 + Filter bank 15 register 2 + 0x2BC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R1 + F16R1 + Filter bank 16 register 1 + 0x2C0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R2 + F16R2 + Filter bank 16 register 2 + 0x2C4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R1 + F17R1 + Filter bank 17 register 1 + 0x2C8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R2 + F17R2 + Filter bank 17 register 2 + 0x2CC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R1 + F18R1 + Filter bank 18 register 1 + 0x2D0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R2 + F18R2 + Filter bank 18 register 2 + 0x2D4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R1 + F19R1 + Filter bank 19 register 1 + 0x2D8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R2 + F19R2 + Filter bank 19 register 2 + 0x2DC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R1 + F20R1 + Filter bank 20 register 1 + 0x2E0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R2 + F20R2 + Filter bank 20 register 2 + 0x2E4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R1 + F21R1 + Filter bank 21 register 1 + 0x2E8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R2 + F21R2 + Filter bank 21 register 2 + 0x2EC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R1 + F22R1 + Filter bank 22 register 1 + 0x2F0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R2 + F22R2 + Filter bank 22 register 2 + 0x2F4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R1 + F23R1 + Filter bank 23 register 1 + 0x2F8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R2 + F23R2 + Filter bank 23 register 2 + 0x2FC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R1 + F24R1 + Filter bank 24 register 1 + 0x300 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R2 + F24R2 + Filter bank 24 register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R1 + F25R1 + Filter bank 25 register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R2 + F25R2 + Filter bank 25 register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R1 + F26R1 + Filter bank 26 register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R2 + F26R2 + Filter bank 26 register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R1 + F27R1 + Filter bank 27 register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R2 + F27R2 + Filter bank 27 register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + diff --git a/neo/mgmt-stm32/build.rs b/neo/mgmt-stm32/build.rs new file mode 100644 index 0000000..2e1f422 --- /dev/null +++ b/neo/mgmt-stm32/build.rs @@ -0,0 +1,22 @@ +use std::env; +use std::path::PathBuf; + +fn main() { + println!("cargo::rerun-if-changed=STM32F0x2.svd"); + + let bindings = svdgen::Builder::default() + .svd_file("STM32F0x2.svd") + .include("RCC") + .include("FLASH") + .include("GPIOA") + .include("GPIOB") + .include("USART1") + .include("USART2") + .build() + .expect("Unable to parse SVD file"); + + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap()); + bindings + .write_to_file(out_path.join("stm32f0x2.rs")) + .expect("Unable to translate SVD file"); +} diff --git a/neo/mgmt-stm32/mem072.x b/neo/mgmt-stm32/mem072.x new file mode 100644 index 0000000..97493c2 --- /dev/null +++ b/neo/mgmt-stm32/mem072.x @@ -0,0 +1,61 @@ +/* Info for STM32F072C8T6 */ + +_Heap_Size = 0x0; +_Stack_Size = 0x100; + +MEMORY +{ + FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (XRW): ORIGIN = 0x20000000, LENGTH = 16K +} + +ENTRY(Reset_Handler); + +/* setup stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +SECTIONS +{ + .vector_table ORIGIN(FLASH) : + { + LONG(_estack); + KEEP(*(.vector_table.reset_vector)); + KEEP(*(.vector_table.exceptions)); + } > FLASH + + .text : ALIGN(4) + { + *(.text .text.*); + } > FLASH + + .rodata : ALIGN(4) + { + *(.rodata .rodata.*); + } > FLASH + + .data : ALIGN(4) + { + _sdata = .; + *(.data .data.*); + _edata = .; + } > RAM AT > FLASH + + _sidata = LOADADDR(.data); + + .bss : ALIGN(4) + { + _sbss = .; + *(.bss .bss.*); + _ebss = .; + } > RAM + + /* Heap and stack symbols defined without creating sections */ + _heap_start = .; + _stack_reserve_start = _heap_start + _Heap_Size; + _stack_reserve_end = _stack_reserve_start + _Stack_Size; + + .stack_sizes (INFO) : + { + KEEP(*(.stack_sizes)); + } +} \ No newline at end of file diff --git a/neo/mgmt-stm32/src/board/led.rs b/neo/mgmt-stm32/src/board/led.rs new file mode 100644 index 0000000..40ff9dc --- /dev/null +++ b/neo/mgmt-stm32/src/board/led.rs @@ -0,0 +1,67 @@ +use crate::hal::gpio; + +#[derive(Copy, Clone)] +pub enum Color { + Black, + White, + Red, + Green, + Blue, + Teal, + Yellow, + Purple, +} + +impl Color { + fn rgb(&self) -> (bool, bool, bool) { + match self { + Self::Black => (false, false, false), + Self::Red => (true, false, false), + Self::Green => (false, true, false), + Self::Blue => (false, false, true), + Self::Teal => (false, true, true), + Self::Purple => (true, false, true), + Self::Yellow => (true, true, false), + Self::White => (true, true, true), + } + } +} + +pub struct Led { + r: gpio::Output, + g: gpio::Output, + b: gpio::Output, +} + +impl Default for Led +where + R: gpio::Fields, + G: gpio::Fields, + B: gpio::Fields, +{ + fn default() -> Self { + let r = R::output(); + let g = G::output(); + let b = B::output(); + + r.set_low(); + g.set_low(); + b.set_low(); + + Self { r, g, b } + } +} + +impl Led +where + R: gpio::Fields, + G: gpio::Fields, + B: gpio::Fields, +{ + pub fn set(&self, c: Color) { + let (r, g, b) = c.rgb(); + self.r.set(r ^ INVERT); + self.g.set(g ^ INVERT); + self.b.set(b ^ INVERT); + } +} diff --git a/neo/mgmt-stm32/src/board/mod.rs b/neo/mgmt-stm32/src/board/mod.rs new file mode 100644 index 0000000..991effe --- /dev/null +++ b/neo/mgmt-stm32/src/board/mod.rs @@ -0,0 +1,100 @@ +pub mod led; + +use crate::hal::uart::{USART1, USART2}; +use crate::hal::{clock, gpio, uart}; +use led::Led; + +use crate::hal::gpio::Fields as _; +use crate::hal::uart::Fields as _; + +mod led_a { + use crate::hal::gpio::gpioa; + pub type RedPin = gpioa::PA4; + pub type GreenPin = gpioa::PA6; + pub type BluePin = gpioa::PA7; +} + +mod led_b { + use crate::hal::gpio::gpiob; + pub type RedPin = gpiob::PB0; + pub type GreenPin = gpiob::PB14; + pub type BluePin = gpiob::PB15; +} + +mod console { + use crate::hal::{gpio::gpioa, uart}; + pub type Tx = gpioa::PA9; + pub type Rx = gpioa::PA10; + pub type Usart = uart::USART1; + pub const BAUD_RATE: u32 = 115_200; +} + +mod ui { + use crate::hal::gpio::{gpioa, gpiob}; + use crate::hal::uart; + + pub type Tx = gpioa::PA2; + pub type Rx = gpioa::PA3; + pub type Usart = uart::USART2; + pub const BAUD_RATE: u32 = 115_200; + + pub type BootPin = gpioa::PA15; + pub type ResetPin = gpiob::PB3; +} + +mod net { + use crate::hal::gpio::gpiob; + use crate::hal::uart; + + pub type Tx = gpiob::PB10; + pub type Rx = gpiob::PB11; + pub type Usart = uart::USART2; + pub const BAUD_RATE: u32 = 115_200; + + pub type BootPin = gpiob::PB5; + pub type ResetPin = gpiob::PB4; +} + +pub struct Board { + pub led_a: Led, + pub led_b: Led, + + pub ui_boot: gpio::Output, + pub ui_reset: gpio::Output, + + pub console: uart::Uart, + pub ui_uart: uart::Uart, +} + +impl Board { + pub fn new(hse_clk_freq: u32) -> Self { + clock::init(hse_clk_freq); + gpio::init(); + uart::init(); + + let ui_boot = ui::BootPin::output(); + ui_boot.set_low(); + + let ui_reset = ui::ResetPin::output(); + ui_reset.open_drain(); + ui_reset.pull_up(); + + let net_boot = net::BootPin::output(); + net_boot.set_low(); + + let net_reset = net::ResetPin::output(); + net_reset.open_drain(); + net_reset.pull_up(); + + Self { + led_a: Default::default(), + led_b: Default::default(), + + ui_boot, + ui_reset, + + console: USART1::get(console::BAUD_RATE), + ui_uart: USART2::get(ui::BAUD_RATE), + } + } +} diff --git a/neo/mgmt-stm32/src/hal/clock.rs b/neo/mgmt-stm32/src/hal/clock.rs new file mode 100644 index 0000000..3cd9201 --- /dev/null +++ b/neo/mgmt-stm32/src/hal/clock.rs @@ -0,0 +1,64 @@ +//! # Clock Module +//! +//! This module provides functions to initialize and validate the clock configuration for the system. +//! It handles setting up the PLL (Phase-Locked Loop), external clock, and various clock dividers. +//! +//! ## Functions +//! +//! - `init`: Initializes the clock configuration based on the board-specific settings. +//! - `validate`: Validates the clock configuration to ensure it is set up correctly. +//! +//! ## Usage +//! +//! The `init` function should be called during system startup to configure the clock. The `validate` function +//! can be used to check if the clock configuration is correct. +//! + +use crate::hal::gpio::{gpioa, Fields, Output}; +use crate::svd::{Read, Write, RCC}; + +/// Initializes the clock configuration based on the board-specific settings. +pub fn init(hse_clk_freq: u32) { + let pll_m = match hse_clk_freq { + 16_000_000 => 4, + _ => unreachable!("Invalid HSE clock frequency {hse_clk_freq}"), + }; + + // Enable HSE + RCC::CR::HSEON::write(true); + while !RCC::CR::HSERDY::read() {} + + // Configure PLL + RCC::CFGR::PLLSRC::write(1); // HSE as PLL source + RCC::CFGR::PLLMUL::write(pll_m); // PLL multiplier + RCC::CFGR::PPRE::write(0); // No AHB prescaler + + // Enable PLL + RCC::CR::PLLON::write(true); + while !RCC::CR::PLLRDY::read() {} + + // Select PLL as system clock source + RCC::CFGR::SW::write(0b10); + while RCC::CFGR::SWS::read() != 0b10 {} +} + +/// Configure MCO to output half of the PLLCLK frequency +pub fn configure_mco(_pin: &Output, mco_freq: u32) { + assert_eq!(mco_freq, 24_000_000); + + // Enable GPIOA clock + RCC::AHBENR::IOPAEN::write(true); + + // Configure PA8 as an alternate function (MCO) + // TODO(RLB) move this to the GPIO module? + ::MODER::write(0b10); // Set mode to alternate function + ::AFR::write(0); // Set AF0 for MCO + + // Set MCO to output PLLCLK / 2 + RCC::CFGR::MCO::write(0b0111); // Set MCO source to PLLCLK + RCC::CFGR::PLLNODIV::write(true); // PLL is NOT divided by 2 + RCC::CFGR::MCOPRE::write(0b001); // Set MCO prescaler to divide by 2 +} + +/// Validates the clock configuration to ensure it is set up correctly. +pub fn validate() {} diff --git a/neo/mgmt-stm32/src/hal/gpio.rs b/neo/mgmt-stm32/src/hal/gpio.rs new file mode 100644 index 0000000..84a68b7 --- /dev/null +++ b/neo/mgmt-stm32/src/hal/gpio.rs @@ -0,0 +1,207 @@ +//! ## Example +//! +//! ``` rust +//! use crate::hal::gpio::{self, Pin}; +//! use crate::hal::cpu; +//! use crate::hal::clock; +//! +//! fn main() { +//! cpu::init(); +//! clock::init( 16_000_000 ); +//! gpio::init(); +//! +//! let pin = gpio::gpioa::PA5::output(); +//! pin.set_high(); +//! +//! let pin = gpio::gpioa::PA4::input(); +//! println!("Pin state: {}", pin.read()); +//! } +//! ``` +#![allow(non_camel_case_types)] + +use crate::svd::{Read, Write, RCC}; + +pub fn init() { + RCC::AHBENR::IOPAEN::write(true); + RCC::AHBENR::IOPBEN::write(true); +} + +pub trait Fields: Sized { + type IDR: Read; + type MODER: Write; + type ODR: Write; + type OTYPER: Write; + type PUPDR: Write; + type OSPEEDR: Write; + type BR: Write; + type BS: Write; + type AFR: Write; + + fn alt_fun(af_mode: u8, fast: bool) -> AltFun { + Self::MODER::write(0b10); // Set mode to output + Self::ODR::write(false); // Set output to low + Self::OTYPER::write(false); // Set as push-pull + Self::PUPDR::write(0b00); // Set no pull up; no pull down + + Self::OSPEEDR::write(if fast { 0b10 } else { 0b00 }); + Self::AFR::write(af_mode); + + AltFun::new() + } + + fn output() -> Output { + Self::MODER::write(0b01); // mode = output + Self::ODR::write(false); // output = low + Self::OTYPER::write(false); // push-pull + Self::PUPDR::write(0b00); // no pull down or pull up + Self::OSPEEDR::write(0b00); // speed = slow + + Output::new() + } + + fn input() -> Input { + Self::MODER::write(0b00); // mode = input + Self::PUPDR::write(0b10); // pull down + + Input::new() + } +} + +pub struct AltFun { + _phantom: core::marker::PhantomData, +} + +impl AltFun +where + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } +} + +pub struct Output { + _phantom: core::marker::PhantomData, +} + +impl Output +where + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } + + pub fn set(&self, high: bool) { + if high { + self.set_high() + } else { + self.set_low() + } + } + + pub fn set_low(&self) { + F::BR::write(true); + } + + pub fn set_high(&self) { + F::BS::write(true); + } + + pub fn pull_up(&self) { + F::PUPDR::write(0b10); + } + + pub fn open_drain(&self) { + F::OTYPER::write(true); // Set output type to open-drain + F::ODR::write(false); // Set output to low + // XXX(RLB) Comment says "high" in bare-rust + F::PUPDR::write(0b01); // Set pull up + F::OSPEEDR::write(0b00); // Set speed to slow + } +} + +pub struct Input { + _phantom: core::marker::PhantomData, +} + +impl Input +where + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } + + pub fn pull_up(&self) { + F::PUPDR::write(0b10); + } + + pub fn pull_down(&self) { + F::PUPDR::write(0b01); + } + + pub fn read(&self) -> bool { + F::IDR::read() + } +} + +use paste::paste; + +macro_rules! pin { + ($name:ident, $pin:literal, $lohi:ident) => { + paste! { + pub struct [

]; + + impl Fields for [

] { + type MODER = []::MODER::[]; + type OTYPER = []::OTYPER::[]; + type OSPEEDR = []::OSPEEDR::[]; + type PUPDR = []::PUPDR::[]; + type IDR = []::IDR::[]; + type ODR = []::ODR::[]; + type BR = []::BSRR::[
]; + type BS = []::BSRR::[]; + type AFR = []::[]::[]; + } + } + }; +} + +macro_rules! bus { + ($name:expr) => { + paste! { + pub mod [] { + use paste::paste; + use super::Fields; + use crate::svd::[]; + + pin! { $name, 0, L } + pin! { $name, 1, L } + pin! { $name, 2, L } + pin! { $name, 3, L } + pin! { $name, 4, L } + pin! { $name, 5, L } + pin! { $name, 6, L } + pin! { $name, 7, L } + pin! { $name, 8, H } + pin! { $name, 9, H } + pin! { $name, 10, H } + pin! { $name, 11, H } + pin! { $name, 12, H } + pin! { $name, 13, H } + pin! { $name, 14, H } + pin! { $name, 15, H } + } + } + }; +} + +bus! { A } +bus! { B } diff --git a/neo/mgmt-stm32/src/hal/mod.rs b/neo/mgmt-stm32/src/hal/mod.rs new file mode 100644 index 0000000..d9abd13 --- /dev/null +++ b/neo/mgmt-stm32/src/hal/mod.rs @@ -0,0 +1,3 @@ +pub mod clock; +pub mod gpio; +pub mod uart; diff --git a/neo/mgmt-stm32/src/hal/uart.rs b/neo/mgmt-stm32/src/hal/uart.rs new file mode 100644 index 0000000..13e98dc --- /dev/null +++ b/neo/mgmt-stm32/src/hal/uart.rs @@ -0,0 +1,169 @@ +//! ## Example +//! +//! ``` rust +//! use crate::hal::gpio::{self, Pin}; +//! use crate::hal::cpu; +//! use crate::hal::clock; +//! +//! fn main() { +//! cpu::init(); +//! clock::init( 16_000_000 ); +//! gpio::init(); +//! +//! let pin = gpio::gpioa::PA5::output(); +//! pin.set_high(); +//! +//! let pin = gpio::gpioa::PA4::input(); +//! println!("Pin state: {}", pin.read()); +//! } +//! ``` +#![allow(non_camel_case_types)] + +use crate::hal::gpio; +use crate::svd::{Read, Write, RCC}; + +pub fn init() { + RCC::APB2ENR::USART1EN::write(true); + RCC::APB1ENR::USART2EN::write(true); +} + +pub trait Fields: Sized { + const APB_FREQ: u32; + + type DIV_MANTISSA: Write; + type DIV_FRACTION: Write; + type PCE: Write; + type PS: Write; + type STOP: Write; + type UE: Write; + type TE: Write; + type RE: Write; + type TXE: Read; + type TDR: Write; + type RXNE: Read; + type RDR: Read; + + fn get(baud_rate: u32) -> Uart { + // Acquire and configure the GPIO pins + let _tx_pin = Tx::alt_fun(1, false); // AF1 work for USART1 to 3 + let _rx_pin = Rx::alt_fun(1, false); // AF1 work for USART1 to 3 + + // Set the baud rate + // XXX(RLB) The bare-rust equivalent of this code writes directly to the BRR register, but + // the SVD file exposes only Mantissa and Fraction fields. The Fraction field is 4 bits + // wide, so this should be equivalent. + const FRACTION_WIDTH: usize = 4; + const FRACTION_MASK: u32 = (1 << FRACTION_WIDTH) - 1; + + let div = Self::APB_FREQ / baud_rate; + Self::DIV_MANTISSA::write((div >> FRACTION_WIDTH) as u16); + Self::DIV_FRACTION::write((div & FRACTION_MASK) as u8); + + // Set no parity + Self::PCE::write(false); // No parity + Self::STOP::write(0b00); // 1 stop bit + + // Enable the USART bus as transmitter and receiver + Self::UE::write(true); // USART enable + Self::TE::write(true); // Transmitter enable + Self::RE::write(true); // Receiver enable + + Uart::new() + } +} + +pub struct Uart { + _phantom: core::marker::PhantomData<(Tx, Rx, F)>, +} + +impl Uart +where + Tx: gpio::Fields, + Rx: gpio::Fields, + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } + + pub fn write_ready(&self) -> bool { + !F::TXE::read() + } + + pub fn read_ready(&self) -> bool { + !F::RXNE::read() + } + + pub fn write_byte(&self, byte: u8) { + while !self.write_ready() {} + F::TDR::write(byte.into()) + } + + pub fn read_byte(&self) -> u8 { + while !self.read_ready() {} + F::RDR::read() as u8 + } + + pub fn write(&self, buffer: impl AsRef<[u8]>) { + for byte in buffer.as_ref() { + self.write_byte(*byte); + } + } + + pub fn read_exact(&self, buffer: &mut [u8]) { + buffer.fill_with(|| self.read_byte()); + } + + pub fn read_until<'a>(&self, delim: char, buffer: &'a mut [u8]) -> &'a [u8] { + let mut utf8 = [0_u8; 1]; + delim.encode_utf8(&mut utf8); + + let mut len = 0; + let mut done = false; + buffer.fill_with(|| { + if done { + return 0; + } + + let c = self.read_byte(); + done = c == utf8[0]; + len += 1; + + c + }); + + &buffer[..len] + } +} + +use crate::svd; +use paste::paste; + +macro_rules! device { + ($name:ident, $apb_freq:expr) => { + paste! { + pub struct $name; + + impl Fields for $name { + const APB_FREQ: u32 = $apb_freq; + type DIV_MANTISSA = svd::$name::BRR::DIV_Mantissa; + type DIV_FRACTION = svd::$name::BRR::DIV_Fraction; + type PCE = svd::$name::CR1::PCE; + type PS = svd::$name::CR1::PS; + type STOP = svd::$name::CR2::STOP; + type UE = svd::$name::CR1::UE; + type TE = svd::$name::CR1::TE; + type RE = svd::$name::CR1::RE; + type TXE = svd::$name::ISR::TXE; + type TDR = svd::$name::TDR::TDR; + type RXNE = svd::$name::ISR::RXNE; + type RDR = svd::$name::RDR::RDR; + } + } + }; +} + +device! { USART1, 48_000_000 } +device! { USART2, 48_000_000 } diff --git a/neo/mgmt-stm32/src/main.rs b/neo/mgmt-stm32/src/main.rs new file mode 100644 index 0000000..6ccd7b4 --- /dev/null +++ b/neo/mgmt-stm32/src/main.rs @@ -0,0 +1,34 @@ +#![no_std] +#![no_main] +#![allow(dead_code)] // TODO(RLB) Remove once things are more complete + +mod board; +mod hal; +mod startup; +mod svd; + +use board::led::Color; +use board::Board; + +#[unsafe(no_mangle)] +pub extern "C" fn main() -> ! { + // XXX(RLB): Lazy static? + let board = Board::new(16_000_000); + + // Set the LEDs to a startup pattern + board.led_a.set(Color::White); + board.led_b.set(Color::White); + + // Forward UART from console to UI + loop { + if board.ui_uart.read_ready() { + let c = board.ui_uart.read_byte(); + board.console.write_byte(c); + } + + if board.console.read_ready() { + let c = board.console.read_byte(); + board.ui_uart.write_byte(c); + } + } +} diff --git a/neo/mgmt-stm32/src/startup.rs b/neo/mgmt-stm32/src/startup.rs new file mode 100644 index 0000000..06a141e --- /dev/null +++ b/neo/mgmt-stm32/src/startup.rs @@ -0,0 +1,552 @@ +// XXX(RLB): I have just copied this over blindly from the initial bare-rust code. Just some light +// clean-up to get things to build. It seems like there's a lot of duplication here (how many +// Default_Handler functions do we need??), and cleanup that could be done, e.g., skipping a lot of +// the initialization code and turning the IRQ table into a struct. But I don't feel like I +// understand what's going on here well enough to make changes. + +//! Startup code for ARM Cortex-M microcontrollers +//! +//! The `Reset_Handler` function is the entry point of the program +//! and is called after the microcontroller is reset. It initializes +//! the `.bss` and `.data` sections, and then calls the `main` function. +//! +//! The `Default_Handler` function is an exception handler that is called +//! when an exception with no specific handler is raised. It simply +//! turns on the red LED and enters an infinite loop. +//! +//! The `XXX_IRQHandler` functions are interrupt handlers that are called +//! when a specific interrupt is raised. +//! +//! More information about the startup process can be found in +//! the [Cortex-M4 Technical Reference Manual](https://documentation-service.arm.com/static/5f19da2a20b7cf4bc524d99a). +//! +//! The code in this module is closely tied to the linker configuration +//! script in the `linker.ld` file. +//! + +use core::ptr; + +const STACK_PAINT_BYTE: u8 = 0xCC; + +unsafe extern "C" { + fn main() -> !; +} + +use core::panic::PanicInfo; + +// XXX(RLB) This is at odds with our construction of a Board as an owned object. It might be +// possible to make it static, since calls to it aren't mutable. But we would want something like +// OnceCell so that we could initialize it at runtime. Or we could cheat and make the default +// value uninitialized + init() method, but that would have the unpleasant side effect of exposing +// an uninitialized value. +// +// ANS(RLB) +// * Need to loop{}, can never come out of panic +// * Can't do serial or anything +#[panic_handler] +fn panic(_panic: &PanicInfo) -> ! { + /* + const LED_RED_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 4); + const LED_GREEN_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 6); + const LED_BLUE_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 7); + + LED_RED_PIN.output(); + LED_GREEN_PIN.output(); + LED_BLUE_PIN.output(); + + LED_RED_PIN.low(); + LED_GREEN_PIN.high(); + LED_BLUE_PIN.high(); + */ + loop {} +} + +unsafe extern "C" { + static mut _sbss: u8; + static _ebss: u8; + static mut _sdata: u8; + static _edata: u8; + static _sidata: u8; + static _estack: u8; + static mut _heap_start: u8; +} + +// XXX(RLB) Under what circumstances is this called? It doesn't look like there's a comparable +// method defined in the C firmware for the mgmt chip. +// +// ANS(RLB): It's the first thing that is called on startup. Probably in ASM in the C version. +#[unsafe(no_mangle)] +#[allow(static_mut_refs)] +pub extern "C" fn Reset_Handler() -> ! { + unsafe { + // XXX(RLB) Why do we care about the initial contents of this section? + // ANS(RLB) Makes it easier to debug. + + // initialize the BSS section with zeros + let count = &_ebss as *const u8 as usize - &_sbss as *const u8 as usize; + ptr::write_bytes(&mut _sbss as *mut u8, 0, count); + } + unsafe { + // XXX(RLB) What function does this serve? + // ANS(RLB) Compiler/linker act as if the data are in memory (in the DATA section), but in + // our binary, they are actually in the FLASH section. + + // initialize the DATA section with the data from the flash + let count = &_edata as *const u8 as usize - &_sdata as *const u8 as usize; + ptr::copy_nonoverlapping(&_sidata as *const u8, &mut _sdata as *mut u8, count); + } + unsafe { + // XXX(RLB) If we're not doing stack painting for stack usage measurements, do we need to + // do this? + // ANS(RLB) Only for stack painting. Nice to have a clean stack when in debugger. + // ANS(RLB) The magic "100" is to keep it clear of this function's stack usage. + + // initialize the heap and stack to 0xC1 + // leave 100 bytes free for this function + let count = &_estack as *const u8 as usize - &_heap_start as *const u8 as usize - 100; + ptr::write_bytes(&mut _heap_start as *mut u8, STACK_PAINT_BYTE, count); + } + + unsafe { main() } +} + +// XXX(RLB): Similar problems with Board ownership here. +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler() { + /* + const LED_RED_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 4); + const LED_GREEN_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 6); + const LED_BLUE_PIN: gpio::Pin = gpio::Pin(cpu::GPIOA, 7); + + LED_GREEN_PIN.output(); + LED_RED_PIN.output(); + LED_BLUE_PIN.output(); + + LED_GREEN_PIN.high(); + LED_RED_PIN.low(); + LED_BLUE_PIN.high(); + */ + + loop {} +} + +// XXX(RLB) Do we need to define all these duplicate symbols? I don't see them at all in the C +// code. In the IRQ vectors, it seems like we could just link to a single `Default_Handler`. +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerA() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerB() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerC() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerD() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerE() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerF() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerG() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_HandlerH() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler1a() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler1b() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler1c() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler1d() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler2() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler3() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler4() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler5() { + Default_Handler(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn Default_Handler6() { + Default_Handler(); +} + +// XXX(RLB) Interesting question of how to enable an application to selectively override some of +// the IRQ handlers, without having to list all the ones they're not using. I think something like +// the following would work thanks to some Rust syntactic sugar: +// +// * Define an IrqTable type that replaces the array below +// * impl Default for IrqTable // just has DefaultHandler for everything +// +// static Exceptions: IrqTable = IrqTable { +// TIM1: &tim1_handler, +// TIM2: &tim2_handler, +// .. Default::default() +// }; +#[unsafe(no_mangle)] +pub extern "C" fn TIM1_UP_TIM10_IRQHandler() { + //hal::timer::handle_tim1_irq(); +} + +#[unsafe(no_mangle)] +pub extern "C" fn TIM2_IRQHandler() { + // TODO(RLB): Implement timers + //hal::timer::handle_tim2_irq(); +} + +// XXX(RLB) Why do we need a union here? On a 32-bit system, the `fn` pointer will be 32 bits, so +// this ends up being the same size. +// +// ANS(RLB) Cullen is mystified by this as well +#[allow(dead_code)] +pub union IrqVector { + not_used: u32, + handler: unsafe extern "C" fn(), +} + +// XXX(RLB) It would be a little nicer to just define this as an `extern "C" fn`. Is there a +// reason for it to be a pointer variable like this? +// +// ANS(RLB): This needs to be a function pointer, not the function itself. There might still be a +// nicer way to express it. +#[unsafe(link_section = ".vector_table.reset_vector")] +#[unsafe(no_mangle)] +pub static Reset_Vector: extern "C" fn() -> ! = Reset_Handler; + +// XXX(RLB) Could we make this a struct instead of an array? You could arrange it so that the +// memory layout was the same; in fact, I think just doing the obvious thing would work: +// +// pub type IrqVector = unsafe extern "C" fn(); +// +// struct IrqTable { +// pub NMI: IrqVector, +// pub HardFault: IrqVector, +// pub SVC: IrqVector, +// ... +// } +// +// It would also be nice to generate this struct off of the SVD file. Looking at the SVD file, I +// don't see anything about the first 5 entries here, but I see things like this: +// +// +// TIM7 +// TIM7 global interrupt +// 18 +// +// +// So maybe we could hard-code the first 5 enteries, then generate the rest of the struct/table +// from objects in the SVD? +// +// ANS(RLB): All the Default_Handler functions are for debugging, so you can put a breakpoint in +// them. Can be simplified. +// +// ANS(RLB): Struct should work, check ASM to make sure it comes out the same. +#[unsafe(link_section = ".vector_table.exceptions")] +#[unsafe(no_mangle)] +pub static Exceptions: [IrqVector; 5 + 81] = [ + IrqVector { + handler: Default_HandlerA, + }, // NMI + IrqVector { + handler: Default_HandlerB, + }, // hard fault + IrqVector { + handler: Default_HandlerC, + }, // SVC + IrqVector { + handler: Default_HandlerD, + }, // Pend SV + IrqVector { + handler: Default_HandlerE, + }, // Sys Timer + // TODO - int vectors are wrong + IrqVector { + handler: Default_Handler1a, + }, // WWDG + IrqVector { + handler: Default_Handler1b, + }, // PVD + IrqVector { + handler: Default_Handler, + }, // RTC_WKUP + IrqVector { + handler: Default_Handler, + }, // FLASH + IrqVector { + handler: Default_Handler, + }, // RCC + IrqVector { + handler: Default_Handler, + }, // EXTI0 + IrqVector { + handler: Default_Handler, + }, // EXTI1 + IrqVector { + handler: Default_Handler, + }, // EXTI2 + IrqVector { + handler: Default_Handler, + }, // EXTI3 + IrqVector { + handler: Default_Handler, + }, // EXTI4 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream0 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream1 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream2 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream3 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream4 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream5 + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream6 + IrqVector { + handler: Default_Handler, + }, // ADC + IrqVector { + handler: Default_Handler, + }, // CAN1_TX + IrqVector { + handler: Default_Handler, + }, // CAN1_RX0 + IrqVector { + handler: Default_Handler, + }, // CAN1_RX1 + IrqVector { + handler: Default_Handler, + }, // CAN1_SCE + IrqVector { + handler: Default_Handler, + }, // EXTI9_5 + IrqVector { + handler: Default_Handler1c, + }, // TIM1_BRK_TIM9 + IrqVector { + handler: TIM1_UP_TIM10_IRQHandler, + }, // TIM1_UP_TIM10 + IrqVector { + handler: Default_Handler2, + }, // TIM1_TRG_COM_TIM11 + IrqVector { + handler: Default_Handler3, + }, // TIM1_CC + IrqVector { + handler: TIM2_IRQHandler, + }, // TIM2 + IrqVector { + handler: Default_Handler, + }, // TIM3 + IrqVector { + handler: Default_Handler, + }, // TIM4 + IrqVector { + handler: Default_Handler, + }, // I2C1_EV + IrqVector { + handler: Default_Handler, + }, // I2C1_ER + IrqVector { + handler: Default_Handler, + }, // I2C2_EV + IrqVector { + handler: Default_Handler, + }, // I2C2_ER + IrqVector { + handler: Default_Handler, + }, // SPI1 + IrqVector { + handler: Default_Handler, + }, // SPI2 + IrqVector { + handler: Default_Handler, + }, // USART1 + IrqVector { + handler: Default_Handler, + }, // USART2 + IrqVector { + handler: Default_Handler, + }, // USART3 + IrqVector { + handler: Default_Handler, + }, // EXTI15_10 + IrqVector { + handler: Default_Handler, + }, // RTC_Alarm + IrqVector { + handler: Default_Handler, + }, // OTG_FS_WKUP + IrqVector { + handler: Default_Handler, + }, // TIM8_BRK_TIM12 + IrqVector { + handler: Default_Handler, + }, // TIM8_UP_TIM13 + IrqVector { + handler: Default_Handler, + }, // TIM8_TRG_COM_TIM14 + IrqVector { + handler: Default_Handler, + }, // TIM8_CC + IrqVector { + handler: Default_Handler, + }, // DMA1_Stream7 + IrqVector { + handler: Default_Handler, + }, // FSMC + IrqVector { + handler: Default_Handler, + }, // SDIO + IrqVector { + handler: Default_Handler, + }, // TIM5 + IrqVector { + handler: Default_Handler, + }, // SPI3 + IrqVector { + handler: Default_Handler, + }, // UART4 + IrqVector { + handler: Default_Handler, + }, // UART5 + IrqVector { + handler: Default_Handler, + }, // TIM6_DAC + IrqVector { + handler: Default_Handler, + }, // TIM7 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream0 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream1 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream2 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream3 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream4 + IrqVector { + handler: Default_Handler, + }, // ETH + IrqVector { + handler: Default_Handler, + }, // ETH_WKUP + IrqVector { + handler: Default_Handler, + }, // CAN2_TX + IrqVector { + handler: Default_Handler, + }, // CAN2_RX0 + IrqVector { + handler: Default_Handler, + }, // CAN2_RX1 + IrqVector { + handler: Default_Handler, + }, // CAN2_SCE + IrqVector { + handler: Default_Handler, + }, // OTG_FS + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream5 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream6 + IrqVector { + handler: Default_Handler, + }, // DMA2_Stream7 + IrqVector { + handler: Default_Handler, + }, // USART6 + IrqVector { + handler: Default_Handler, + }, // I2C3_EV + IrqVector { + handler: Default_Handler, + }, // I2C3_ER + IrqVector { + handler: Default_Handler, + }, // OTG_HS_EP1_OUT + IrqVector { + handler: Default_Handler, + }, // OTG_HS_EP1_IN + IrqVector { + handler: Default_Handler, + }, // OTG_HS_WKUP + IrqVector { + handler: Default_Handler, + }, // OTG_HS + IrqVector { + handler: Default_Handler, + }, // DCMI + IrqVector { + handler: Default_Handler, + }, // CRYP + IrqVector { + handler: Default_Handler, + }, // HASH_RNG + IrqVector { + handler: Default_Handler, + }, // FPU +]; diff --git a/neo/mgmt-stm32/src/svd.rs b/neo/mgmt-stm32/src/svd.rs new file mode 100644 index 0000000..d30af3e --- /dev/null +++ b/neo/mgmt-stm32/src/svd.rs @@ -0,0 +1,7 @@ +#![allow(dead_code)] +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::identity_op)] +#![allow(unused_imports)] + +include!(concat!(env!("OUT_DIR"), "/stm32f0x2.rs")); diff --git a/neo/svdgen/Cargo.toml b/neo/svdgen/Cargo.toml new file mode 100644 index 0000000..7cdb7a1 --- /dev/null +++ b/neo/svdgen/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "svdgen" +version = "0.1.0" +edition = "2024" + +[dependencies] +serde-xml-rs = "0.8.1" +serde = { version = "1.0.219", features = ["derive"] } +clap = { version = "4.5.41", features = ["derive"] } +quote = "1.0.40" +anyhow = "1.0.98" +prettyplease = "0.2.35" +syn = "2.0.104" +proc-macro2 = "1.0.95" diff --git a/neo/svdgen/README.md b/neo/svdgen/README.md new file mode 100644 index 0000000..20e01f3 --- /dev/null +++ b/neo/svdgen/README.md @@ -0,0 +1,71 @@ +# svd + +This crate contains tooling to convert an SVD file in to Rust code that provides +reasonably safe access to device registers. The tool reads an SVD file and +outputs a Rust file with the following contents: + +* Definitions for a `Field` struct and marker structs for access control levels +* For each ``, a Rust module of the same name +* For each ``, a submodule of its peripheral's module +* For each ``, a specialization of the `Field` struct + +For example, if a device has + +The output file is self-contained, with no dependencies, and is suitable for inclusion +as a module in another project. + +## build.rs + +Usage is similar to +[`bindgen`](https://rust-lang.github.io/rust-bindgen/tutorial-3.html). In +`build.rs`: + +``` rust +use std::env; +use std::path::PathBuf; + +fn main() { + println!("cargo::rerun-if-changed=DEVICE.svd"); + + let bindings = svdgen::Builder::default() + .svd_file("DEVICE.svd") + .include("GPIOA") + .include("UART1") + .build() + .expect("Unable to parse SVD file"); + + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap()); + bindings + .write_to_file(out_path.join("DEVICE.rs")) + .expect("Unable to translate SVD file"); +} +``` + +In a file within the crate: + +``` rust +#![allow(dead_code)] +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::identity_op)] +#![allow(unused_imports)] + +include!(concat!(env!("OUT_DIR"), "/DEVICE.rs")); +``` + +## Command line + +``` +> cargo run -- --help +Usage: svdgen [OPTIONS] + +Arguments: + The path of the SVD file to parse + The path of the Rust file to output + +Options: + --only If this vector is non-empty, then only the listed peripherals are included + -h, --help Print help +``` + + diff --git a/neo/svdgen/src/lib.rs b/neo/svdgen/src/lib.rs new file mode 100644 index 0000000..234f08f --- /dev/null +++ b/neo/svdgen/src/lib.rs @@ -0,0 +1,458 @@ +use anyhow::Result; +use proc_macro2::TokenStream; +use quote::{format_ident, quote, ToTokens}; +use serde::{ + de::{Error, Visitor}, + Deserialize, Deserializer, +}; +use std::fs::File; +use std::io::{BufReader, Write}; +use std::path::Path; + +#[derive(Debug, Copy, Clone)] +struct U32(u32); + +impl<'de> Deserialize<'de> for U32 { + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + deserializer.deserialize_str(U32Visitor) + } +} + +struct U32Visitor; + +impl Visitor<'_> for U32Visitor { + type Value = U32; + + fn expecting(&self, formatter: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(formatter, "a decimal or hex integer") + } + + fn visit_str(self, v: &str) -> Result + where + E: Error, + { + let original = v.to_ascii_lowercase(); + let digits = original.trim_start_matches("0x"); + let radix = if original == digits { + 10 // No 0x prefix => decimal + } else { + 16 // 0x prefix present => hex + }; + + u32::from_str_radix(digits, radix) + .map(|n| U32(n)) + .map_err(|e| { + Error::custom(format!( + "Invalid integer (base {}): {} '{}'", + radix, e, digits + )) + }) + } +} + +#[derive(Copy, Clone, Debug)] +enum Access { + ReadOnly, + WriteOnly, + ReadWrite, +} + +impl Default for Access { + fn default() -> Self { + Self::ReadWrite + } +} + +impl ToTokens for Access { + fn to_tokens(&self, tokens: &mut TokenStream) { + match self { + Self::ReadOnly => tokens.extend(quote! { ReadOnly }), + Self::WriteOnly => tokens.extend(quote! { WriteOnly }), + Self::ReadWrite => tokens.extend(quote! { ReadWrite }), + } + } +} + +impl<'de> Deserialize<'de> for Access { + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + deserializer.deserialize_str(AccessVisitor) + } +} + +struct AccessVisitor; + +impl Visitor<'_> for AccessVisitor { + type Value = Access; + + fn expecting(&self, formatter: &mut std::fmt::Formatter) -> std::fmt::Result { + write!(formatter, "an Access enum string") + } + + fn visit_str(self, v: &str) -> Result + where + E: serde::de::Error, + { + match v { + "read-only" => Ok(Access::ReadOnly), + "write-only" => Ok(Access::WriteOnly), + "read-write" => Ok(Access::ReadWrite), + _ => Err(Error::custom(format!("Invalid access value: {}", v))), + } + } +} + +#[derive(Deserialize, Debug, Clone)] +#[serde(rename_all = "camelCase")] +struct Field { + name: String, + bit_offset: usize, + bit_width: usize, + access: Option, +} + +impl ToTokens for Field { + fn to_tokens(&self, tokens: &mut TokenStream) { + let Some(access) = self.access else { + eprintln!("Skipping field {}: Missing access", self.name); + return; + }; + + let name = format_ident!("{}", self.name); + let bit_offset = self.bit_offset; + let bit_width = self.bit_width; + + let access_type = match self.bit_width { + 1 => format_ident!("bool"), + ..=8 => format_ident!("u8"), + ..=16 => format_ident!("u16"), + ..=32 => format_ident!("u16"), + _ => return Default::default(), + }; + + tokens.extend(quote! { + pub type #name = Field<#access_type, { ADDR }, #bit_offset, #bit_width, #access>; + }) + } +} + +#[derive(Deserialize, Debug, Clone)] +struct Fields { + #[serde(rename = "field")] + fields: Vec, +} + +#[derive(Deserialize, Debug, Clone)] +#[serde(rename_all = "camelCase")] +struct Register { + name: String, + address_offset: U32, + // size: Usize, // TODO: Do something with this + access: Option, + fields: Fields, +} + +impl ToTokens for Register { + fn to_tokens(&self, tokens: &mut TokenStream) { + let name = format_ident!("{}", self.name); + let address_offset = self.address_offset.0; + let fields = self.fields.fields.iter(); + + tokens.extend(quote! { + pub mod #name { + use super::*; + + pub const ADDR: u32 = BASE_ADDR + #address_offset; + + #(#fields)* + } + }) + } +} + +#[derive(Deserialize, Debug, Clone)] +struct Registers { + #[serde(rename = "register")] + registers: Vec, +} + +#[derive(Deserialize, Debug, Clone)] +#[serde(rename_all = "camelCase")] +struct Peripheral { + #[serde(rename = "@derivedFrom")] + derived_from: Option, + name: String, + base_address: Option, + registers: Option, +} + +impl Peripheral { + fn rebase(&mut self, base: &Peripheral) { + // Use values from `base` if not present in this object + // This will need to be updated if more fields are introduced to Peripheral + let Peripheral { + base_address, + registers, + .. + } = base.clone(); + + let base_address = self.base_address.clone().or(base_address); + let registers = self.registers.clone().or(registers); + + self.base_address = base_address; + self.registers = registers; + } +} + +impl ToTokens for Peripheral { + fn to_tokens(&self, tokens: &mut TokenStream) { + let Some(base_address) = self.base_address.as_ref() else { + eprintln!("Skipping peripheral {}: Missing base_address", self.name); + return; + }; + + let Some(registers) = self.registers.as_ref() else { + eprintln!("Skipping peripheral {}: Missing registers", self.name); + return; + }; + + let name = format_ident!("{}", self.name); + let base_addr = base_address.0; + let registers = registers.registers.iter(); + + tokens.extend(quote! { + pub mod #name { + use super::{Field, ReadOnly, WriteOnly, ReadWrite}; + + const BASE_ADDR: u32 = #base_addr; + + #(#registers)* + } + }) + } +} + +#[derive(Deserialize, Debug)] +struct Peripherals { + #[serde(rename = "peripheral")] + peripherals: Vec, +} + +#[derive(Deserialize, Debug)] +#[serde(rename_all = "camelCase")] +struct Device { + peripherals: Peripherals, +} + +impl Device { + fn find_peripheral(&self, name: &str) -> Peripheral { + self.peripherals + .peripherals + .iter() + .find(|p| p.name == name) + .cloned() + .expect(&format!("Unknown peripheral: {}", name)) + } + + fn normalize(&mut self) { + use std::collections::HashMap; + + // Follow derivedFrom relationships + let rewrite: HashMap = self + .peripherals + .peripherals + .iter() + .filter_map(|p| { + p.derived_from + .as_ref() + .map(|df| (p.name.clone(), df.clone())) + }) + .map(|(n, df)| (n, self.find_peripheral(&df))) + .collect(); + + for p in self.peripherals.peripherals.iter_mut() { + rewrite.get(&p.name).map(|q| p.rebase(q)); + } + + // Apply access rules from registers down to fields + for p in self.peripherals.peripherals.iter_mut() { + for r in p.registers.as_mut().unwrap().registers.iter_mut() { + for f in r.fields.fields.iter_mut() { + f.access = f.access.or(r.access); + } + } + } + } + + fn filter(&mut self, only: &[String]) { + if only.is_empty() { + return; + } + + self.peripherals + .peripherals + .retain(|p| only.contains(&p.name)); + } +} + +const PRELUDE: &str = " +pub struct ReadOnly; +pub struct WriteOnly; +pub struct ReadWrite; + +pub trait FromU32 { + fn from_u32(x: u32) -> Self; +} + +impl FromU32 for bool { + fn from_u32(x: u32) -> Self { x != 0 } +} + +impl FromU32 for u8 { + fn from_u32(x: u32) -> Self { x as Self } +} + +impl FromU32 for u16 { + fn from_u32(x: u32) -> Self { x as Self } +} + +pub trait Read { + fn read() -> T; +} + +pub trait Write { + fn write(t: T); +} + +#[derive(Default)] +pub struct Field( + core::marker::PhantomData<(T, A)>, +); + +impl Field +{ + const ADDRESS: *mut u32 = ADDR as *mut u32; + const MASK: u32 = ((1 << W) - 1) << OFF; + const OFFSET: usize = OFF; +} + +impl Read for Field +where + T: FromU32, +{ + fn read() -> T { + let raw = unsafe { Self::ADDRESS.read_volatile() }; + T::from_u32((raw & Self::MASK) >> Self::OFFSET) + } +} + +impl Read for Field +where + T: FromU32, +{ + fn read() -> T { + let raw = unsafe { Self::ADDRESS.read_volatile() }; + T::from_u32((raw & Self::MASK) >> Self::OFFSET) + } +} + +impl Write for Field +where + u32: From, +{ + fn write(t: T) { + // TODO: Enforce a critical section around this + let v = u32::from(t) << Self::OFFSET; + let curr = unsafe { Self::ADDRESS.read_volatile() }; + let next = (curr & !Self::MASK) | (v & Self::MASK); + unsafe { Self::ADDRESS.write_volatile(next) }; + } +} + +impl Write for Field +where + T: FromU32, + u32: From, +{ + fn write(t: T) { + // TODO: Enforce a critical section around this + let v = u32::from(t) << Self::OFFSET; + let curr = unsafe { Self::ADDRESS.read_volatile() }; + let next = (curr & !Self::MASK) | (v & Self::MASK); + unsafe { Self::ADDRESS.write_volatile(next) }; + } +} +"; + +#[derive(Default)] +struct Options { + svd_file: String, + only: Vec, +} + +/// A Builder is used to configure an SVD-to-Rust translation task. Typical usage: +/// +/// ``` +/// let svd_file = svd::Builder::default() +/// .svd_file("STM32F405.svd") +/// .include("GPIOA") +/// .include("UART1") +/// .build(); +/// ``` +#[derive(Default)] +pub struct Builder { + options: Options, +} + +impl Builder { + /// Specify the SVD file to be translated. + pub fn svd_file(mut self, svd_file: &str) -> Self { + self.options.svd_file = svd_file.to_string(); + self + } + + /// Specify a peripheral to be translated. If this method is never invoked, then all + /// peripherals are translated. + pub fn include(mut self, peripheral: &str) -> Self { + self.options.only.push(peripheral.to_string()); + self + } + + /// Parse the SVD file with the provided options. Returns a representation of the parsed SVD + /// file which can then be written to a file. + pub fn build(self) -> Result { + let file = File::open(&self.options.svd_file)?; + let reader = BufReader::new(file); + + let mut device: Device = serde_xml_rs::from_reader(reader)?; + device.normalize(); + device.filter(&self.options.only); + + Ok(DeviceDescription { device }) + } +} + +/// A device description parsed from an SVD file, ready to be translated to Rust. +pub struct DeviceDescription { + device: Device, +} + +impl DeviceDescription { + /// Write Rust code to the provided path. + pub fn write_to_file>(self, path: P) -> Result<()> { + let peripherals = self.device.peripherals.peripherals.iter(); + let tokens = quote! { #(#peripherals)* }; + let ast = syn::parse2(tokens).unwrap(); + let formatted = prettyplease::unparse(&ast); + + let mut file = File::create(path)?; + file.write_all(PRELUDE.as_bytes())?; + file.write_all(formatted.as_bytes())?; + Ok(()) + } +} diff --git a/neo/svdgen/src/main.rs b/neo/svdgen/src/main.rs new file mode 100644 index 0000000..1f21006 --- /dev/null +++ b/neo/svdgen/src/main.rs @@ -0,0 +1,31 @@ +use anyhow::Result; +use clap::Parser; + +#[derive(Parser, Debug)] +struct Args { + /// A comma-separated list of peripheral names to translate. If this vector is empty, then all + /// peripherals will be translated. + #[clap(long)] + only: Vec, + + /// The path of the SVD file to parse + svd_file: String, + + /// The path of the Rust file to output + rust_file: String, +} + +fn main() -> Result<()> { + let args = Args::parse(); + + let mut builder = svdgen::Builder::default().svd_file(&args.svd_file); + + for name in args.only { + builder = builder.include(&name); + } + + let device = builder.build()?; + device.write_to_file(&args.rust_file)?; + + Ok(()) +} diff --git a/neo/ui-stm32/Cargo.toml b/neo/ui-stm32/Cargo.toml new file mode 100644 index 0000000..53e9241 --- /dev/null +++ b/neo/ui-stm32/Cargo.toml @@ -0,0 +1,10 @@ +[package] +name = "ui-stm32" +version = "0.1.0" +edition = "2024" + +[build-dependencies] +svdgen = { path = "../svdgen" } + +[dependencies] +paste = "1.0.15" diff --git a/neo/ui-stm32/STM32F405.svd b/neo/ui-stm32/STM32F405.svd new file mode 100644 index 0000000..22fbbfa --- /dev/null +++ b/neo/ui-stm32/STM32F405.svd @@ -0,0 +1,59120 @@ + + + + STM32F405 + 1.7 + STM32F405 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + FPU + FPU interrupt + 81 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + FSMC + Flexible memory controller + FSMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FSMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR3 + PCR3 + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR3 + SR3 + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR4 + PCR4 + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR4 + SR4 + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers + 3 + BWTR1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers + 4 + BWTR2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + SDCR1 + SDCR1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address + bits + 0 + 2 + + + NR + Number of row address bits + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + NB + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WP + Write protection + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + RBURST + Burst read + 12 + 1 + + + RPIPE + Read pipe + 13 + 2 + + + + + SDCR2 + SDCR2 + SDRAM Control Register 2 + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address + bits + 0 + 2 + + + NR + Number of row address bits + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + NB + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WP + Write protection + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + + + SDTR1 + SDTR1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to + Active + 0 + 4 + + + TXSR + Exit self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDTR2 + SDTR2 + SDRAM Timing register 2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to + Active + 0 + 4 + + + TXSR + Exit self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDCMR + SDCMR + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + MODE + Command mode + 0 + 3 + write-only + + + CTB2 + Command target bank 2 + 3 + 1 + write-only + + + CTB1 + Command target bank 1 + 4 + 1 + write-only + + + NRFS + Number of Auto-refresh + 5 + 4 + read-write + + + MRD + Mode Register definition + 9 + 13 + read-write + + + + + SDRTR + SDRTR + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag + 0 + 1 + write-only + + + COUNT + Refresh Timer Count + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag + 0 + 1 + + + MODES1 + Status Mode for Bank 1 + 1 + 2 + + + MODES2 + Status Mode for Bank 2 + 3 + 2 + + + BUSY + Busy status + 5 + 1 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + IDCODE + 0x0 + 0x20 + read-only + 0x10006411 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + DBGMCU_CR + DBGMCU_CR + Control Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 16 + 1 + + + DBG_TIM8_STOP + DBG_TIM8_STOP + 17 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 18 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 19 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 20 + 1 + + + + + DBGMCU_APB1_FZ + DBGMCU_APB1_FZ + Debug MCU APB1 Freeze registe + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 0 + 1 + + + DBG_TIM3_STOP + DBG_TIM3 _STOP + 1 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 2 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 3 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 4 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 5 + 1 + + + DBG_TIM12_STOP + DBG_TIM12_STOP + 6 + 1 + + + DBG_TIM13_STOP + DBG_TIM13_STOP + 7 + 1 + + + DBG_TIM14_STOP + DBG_TIM14_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 11 + 1 + + + DBG_IWDEG_STOP + DBG_IWDEG_STOP + 12 + 1 + + + DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT + 22 + 1 + + + DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT + 23 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 25 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 26 + 1 + + + + + DBGMCU_APB2_FZ + DBGMCU_APB2_FZ + Debug MCU APB2 Freeze registe + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 0 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM9_STOP + TIM9 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM10_STOP + TIM10 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM11_STOP + TIM11 counter stopped when core is + halted + 18 + 1 + + + + + + + DMA2 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x400 + registers + + + DMA2_Stream0 + DMA2 Stream0 global interrupt + 56 + + + DMA2_Stream1 + DMA2 Stream1 global interrupt + 57 + + + DMA2_Stream2 + DMA2 Stream2 global interrupt + 58 + + + DMA2_Stream3 + DMA2 Stream3 global interrupt + 59 + + + DMA2_Stream4 + DMA2 Stream4 global interrupt + 60 + + + DMA2_Stream5 + DMA2 Stream5 global interrupt + 68 + + + DMA2_Stream6 + DMA2 Stream6 global interrupt + 69 + + + DMA2_Stream7 + DMA2 Stream7 global interrupt + 70 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + CHTIF6 + Stream x clear half transfer interrupt + flag (x = 7..4) + 20 + 1 + + + CTEIF6 + Stream x clear transfer error interrupt + flag (x = 7..4) + 19 + 1 + + + CDMEIF6 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 18 + 1 + + + CFEIF6 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 16 + 1 + + + CTCIF5 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 11 + 1 + + + CHTIF5 + Stream x clear half transfer interrupt + flag (x = 7..4) + 10 + 1 + + + CTEIF5 + Stream x clear transfer error interrupt + flag (x = 7..4) + 9 + 1 + + + CDMEIF5 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 8 + 1 + + + CFEIF5 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 6 + 1 + + + CTCIF4 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 5 + 1 + + + CHTIF4 + Stream x clear half transfer interrupt + flag (x = 7..4) + 4 + 1 + + + CTEIF4 + Stream x clear transfer error interrupt + flag (x = 7..4) + 3 + 1 + + + CDMEIF4 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 2 + 1 + + + CFEIF4 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 0 + 1 + + + + + S0CR + S0CR + stream x configuration + register + 0x10 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S0NDTR + S0NDTR + stream x number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S0PAR + S0PAR + stream x peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S0M0AR + S0M0AR + stream x memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S0M1AR + S0M1AR + stream x memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S0FCR + S0FCR + stream x FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S1CR + S1CR + stream x configuration + register + 0x28 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S1NDTR + S1NDTR + stream x number of data + register + 0x2C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S1PAR + S1PAR + stream x peripheral address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S1M0AR + S1M0AR + stream x memory 0 address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S1M1AR + S1M1AR + stream x memory 1 address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S1FCR + S1FCR + stream x FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S2CR + S2CR + stream x configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S2NDTR + S2NDTR + stream x number of data + register + 0x44 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S2PAR + S2PAR + stream x peripheral address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S2M0AR + S2M0AR + stream x memory 0 address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S2M1AR + S2M1AR + stream x memory 1 address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S2FCR + S2FCR + stream x FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S3CR + S3CR + stream x configuration + register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S3NDTR + S3NDTR + stream x number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S3PAR + S3PAR + stream x peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S3M0AR + S3M0AR + stream x memory 0 address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S3M1AR + S3M1AR + stream x memory 1 address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S3FCR + S3FCR + stream x FIFO control register + 0x6C + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S4CR + S4CR + stream x configuration + register + 0x70 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S4NDTR + S4NDTR + stream x number of data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S4PAR + S4PAR + stream x peripheral address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S4M0AR + S4M0AR + stream x memory 0 address + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S4M1AR + S4M1AR + stream x memory 1 address + register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S4FCR + S4FCR + stream x FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S5CR + S5CR + stream x configuration + register + 0x88 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S5NDTR + S5NDTR + stream x number of data + register + 0x8C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S5PAR + S5PAR + stream x peripheral address + register + 0x90 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S5M0AR + S5M0AR + stream x memory 0 address + register + 0x94 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S5M1AR + S5M1AR + stream x memory 1 address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S5FCR + S5FCR + stream x FIFO control register + 0x9C + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S6CR + S6CR + stream x configuration + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S6NDTR + S6NDTR + stream x number of data + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S6PAR + S6PAR + stream x peripheral address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S6M0AR + S6M0AR + stream x memory 0 address + register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S6M1AR + S6M1AR + stream x memory 1 address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S6FCR + S6FCR + stream x FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S7CR + S7CR + stream x configuration + register + 0xB8 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S7NDTR + S7NDTR + stream x number of data + register + 0xBC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S7PAR + S7PAR + stream x peripheral address + register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S7M0AR + S7M0AR + stream x memory 0 address + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S7M1AR + S7M1AR + stream x memory 1 address + register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S7FCR + S7FCR + stream x FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + + + DMA1 + 0x40026000 + + DMA1_Stream0 + DMA1 Stream0 global interrupt + 11 + + + DMA1_Stream1 + DMA1 Stream1 global interrupt + 12 + + + DMA1_Stream2 + DMA1 Stream2 global interrupt + 13 + + + DMA1_Stream3 + DMA1 Stream3 global interrupt + 14 + + + DMA1_Stream4 + DMA1 Stream4 global interrupt + 15 + + + DMA1_Stream5 + DMA1 Stream5 global interrupt + 16 + + + DMA1_Stream6 + DMA1 Stream6 global interrupt + 17 + + + DMA1_Stream7 + DMA1 Stream7 global interrupt + 47 + + + + RCC + Reset and clock control + RCC + 0x40023800 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + 0x00000083 + + + PLLI2SRDY + PLLI2S clock ready flag + 27 + 1 + read-only + + + PLLI2SON + PLLI2S enable + 26 + 1 + read-write + + + PLLRDY + Main PLL (PLL) clock ready + flag + 25 + 1 + read-only + + + PLLON + Main PLL (PLL) enable + 24 + 1 + read-write + + + CSSON + Clock security system + enable + 19 + 1 + read-write + + + HSEBYP + HSE clock bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + HSICAL + Internal high-speed clock + calibration + 8 + 8 + read-only + + + HSITRIM + Internal high-speed clock + trimming + 3 + 5 + read-write + + + HSIRDY + Internal high-speed clock ready + flag + 1 + 1 + read-only + + + HSION + Internal high-speed clock + enable + 0 + 1 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0x4 + 0x20 + read-write + 0x24003010 + + + PLLQ3 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 27 + 1 + + + PLLQ2 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 26 + 1 + + + PLLQ1 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 25 + 1 + + + PLLQ0 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 24 + 1 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) + entry clock source + 22 + 1 + + + PLLP1 + Main PLL (PLL) division factor for main + system clock + 17 + 1 + + + PLLP0 + Main PLL (PLL) division factor for main + system clock + 16 + 1 + + + PLLN8 + Main PLL (PLL) multiplication factor for + VCO + 14 + 1 + + + PLLN7 + Main PLL (PLL) multiplication factor for + VCO + 13 + 1 + + + PLLN6 + Main PLL (PLL) multiplication factor for + VCO + 12 + 1 + + + PLLN5 + Main PLL (PLL) multiplication factor for + VCO + 11 + 1 + + + PLLN4 + Main PLL (PLL) multiplication factor for + VCO + 10 + 1 + + + PLLN3 + Main PLL (PLL) multiplication factor for + VCO + 9 + 1 + + + PLLN2 + Main PLL (PLL) multiplication factor for + VCO + 8 + 1 + + + PLLN1 + Main PLL (PLL) multiplication factor for + VCO + 7 + 1 + + + PLLN0 + Main PLL (PLL) multiplication factor for + VCO + 6 + 1 + + + PLLM5 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 5 + 1 + + + PLLM4 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 4 + 1 + + + PLLM3 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 3 + 1 + + + PLLM2 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 2 + 1 + + + PLLM1 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 1 + 1 + + + PLLM0 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 0 + 1 + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output + 2 + 30 + 2 + read-write + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + + MCO1 + Microcontroller clock output + 1 + 21 + 2 + read-write + + + RTCPRE + HSE division factor for RTC + clock + 16 + 5 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 13 + 3 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 10 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS1 + System clock switch status + 3 + 1 + read-only + + + SWS0 + System clock switch status + 2 + 1 + read-only + + + SW1 + System clock switch + 1 + 1 + read-write + + + SW0 + System clock switch + 0 + 1 + read-write + + + + + CIR + CIR + clock interrupt register + 0xC + 0x20 + 0x00000000 + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + PLLI2SRDYC + PLLI2S ready interrupt + clear + 21 + 1 + write-only + + + PLLRDYC + Main PLL(PLL) ready interrupt + clear + 20 + 1 + write-only + + + HSERDYC + HSE ready interrupt clear + 19 + 1 + write-only + + + HSIRDYC + HSI ready interrupt clear + 18 + 1 + write-only + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + + PLLI2SRDYIE + PLLI2S ready interrupt + enable + 13 + 1 + read-write + + + PLLRDYIE + Main PLL (PLL) ready interrupt + enable + 12 + 1 + read-write + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + + CSSF + Clock security system interrupt + flag + 7 + 1 + read-only + + + PLLI2SRDYF + PLLI2S ready interrupt + flag + 5 + 1 + read-only + + + PLLRDYF + Main PLL (PLL) ready interrupt + flag + 4 + 1 + read-only + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + ETHMACRST + Ethernet MAC reset + 25 + 1 + + + DMA2RST + DMA2 reset + 22 + 1 + + + DMA1RST + DMA2 reset + 21 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + GPIOIRST + IO port I reset + 8 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + RNGRST + Random number generator module + reset + 6 + 1 + + + DCMIRST + Camera interface reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FSMCRST + Flexible static memory controller module + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACRST + DAC reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C2RST + I2C 2 reset + 22 + 1 + + + I2C1RST + I2C 1 reset + 21 + 1 + + + UART5RST + USART 5 reset + 20 + 1 + + + UART4RST + USART 4 reset + 19 + 1 + + + UART3RST + USART 3 reset + 18 + 1 + + + UART2RST + USART 2 reset + 17 + 1 + + + SPI3RST + SPI 3 reset + 15 + 1 + + + SPI2RST + SPI 2 reset + 14 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + TIM14RST + TIM14 reset + 8 + 1 + + + TIM13RST + TIM13 reset + 7 + 1 + + + TIM12RST + TIM12 reset + 6 + 1 + + + TIM7RST + TIM7 reset + 5 + 1 + + + TIM6RST + TIM6 reset + 4 + 1 + + + TIM5RST + TIM5 reset + 3 + 1 + + + TIM4RST + TIM4 reset + 2 + 1 + + + TIM3RST + TIM3 reset + 1 + 1 + + + TIM2RST + TIM2 reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM11RST + TIM11 reset + 18 + 1 + + + TIM10RST + TIM10 reset + 17 + 1 + + + TIM9RST + TIM9 reset + 16 + 1 + + + SYSCFGRST + System configuration controller + reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + SDIORST + SDIO reset + 11 + 1 + + + ADCRST + ADC interface reset (common to all + ADCs) + 8 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + TIM8RST + TIM8 reset + 1 + 1 + + + TIM1RST + TIM1 reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock + enable + 30 + 1 + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + ETHMACPTPEN + Ethernet PTP clock enable + 28 + 1 + + + ETHMACRXEN + Ethernet Reception clock + enable + 27 + 1 + + + ETHMACTXEN + Ethernet Transmission clock + enable + 26 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 25 + 1 + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + CCMDATARAMEN + CCM data RAM clock enable + 20 + 1 + + + BKPSRAMEN + Backup SRAM interface clock + enable + 18 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + RNGEN + Random number generator clock + enable + 6 + 1 + + + DCMIEN + Camera interface enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + FSMCEN + Flexible static memory controller module + clock enable + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x40 + 0x20 + read-write + 0x00000000 + + + DACEN + DAC interface clock enable + 29 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + TIM2EN + TIM2 clock enable + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + SYSCFGEN + System configuration controller clock + enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SDIOEN + SDIO clock enable + 11 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + TIM1EN + TIM1 clock enable + 0 + 1 + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power + mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during + Sleep mode + 30 + 1 + + + OTGHSLPEN + USB OTG HS clock enable during Sleep + mode + 29 + 1 + + + ETHMACPTPLPEN + Ethernet PTP clock enable during Sleep + mode + 28 + 1 + + + ETHMACRXLPEN + Ethernet reception clock enable during + Sleep mode + 27 + 1 + + + ETHMACTXLPEN + Ethernet transmission clock enable + during Sleep mode + 26 + 1 + + + ETHMACLPEN + Ethernet MAC clock enable during Sleep + mode + 25 + 1 + + + DMA2LPEN + DMA2 clock enable during Sleep + mode + 22 + 1 + + + DMA1LPEN + DMA1 clock enable during Sleep + mode + 21 + 1 + + + BKPSRAMLPEN + Backup SRAM interface clock enable + during Sleep mode + 18 + 1 + + + SRAM2LPEN + SRAM 2 interface clock enable during + Sleep mode + 17 + 1 + + + SRAM1LPEN + SRAM 1interface clock enable during + Sleep mode + 16 + 1 + + + FLITFLPEN + Flash interface clock enable during + Sleep mode + 15 + 1 + + + CRCLPEN + CRC clock enable during Sleep + mode + 12 + 1 + + + GPIOILPEN + IO port I clock enable during Sleep + mode + 8 + 1 + + + GPIOHLPEN + IO port H clock enable during Sleep + mode + 7 + 1 + + + GPIOGLPEN + IO port G clock enable during Sleep + mode + 6 + 1 + + + GPIOFLPEN + IO port F clock enable during Sleep + mode + 5 + 1 + + + GPIOELPEN + IO port E clock enable during Sleep + mode + 4 + 1 + + + GPIODLPEN + IO port D clock enable during Sleep + mode + 3 + 1 + + + GPIOCLPEN + IO port C clock enable during Sleep + mode + 2 + 1 + + + GPIOBLPEN + IO port B clock enable during Sleep + mode + 1 + 1 + + + GPIOALPEN + IO port A clock enable during sleep + mode + 0 + 1 + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power + mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep + mode + 7 + 1 + + + RNGLPEN + Random number generator clock enable + during Sleep mode + 6 + 1 + + + DCMILPEN + Camera interface enable during Sleep + mode + 0 + 1 + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power + mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FSMCLPEN + Flexible static memory controller module + clock enable during Sleep mode + 0 + 1 + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power + mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + DACLPEN + DAC interface clock enable during Sleep + mode + 29 + 1 + + + PWRLPEN + Power interface clock enable during + Sleep mode + 28 + 1 + + + CAN2LPEN + CAN 2 clock enable during Sleep + mode + 26 + 1 + + + CAN1LPEN + CAN 1 clock enable during Sleep + mode + 25 + 1 + + + I2C3LPEN + I2C3 clock enable during Sleep + mode + 23 + 1 + + + I2C2LPEN + I2C2 clock enable during Sleep + mode + 22 + 1 + + + I2C1LPEN + I2C1 clock enable during Sleep + mode + 21 + 1 + + + UART5LPEN + UART5 clock enable during Sleep + mode + 20 + 1 + + + UART4LPEN + UART4 clock enable during Sleep + mode + 19 + 1 + + + USART3LPEN + USART3 clock enable during Sleep + mode + 18 + 1 + + + USART2LPEN + USART2 clock enable during Sleep + mode + 17 + 1 + + + SPI3LPEN + SPI3 clock enable during Sleep + mode + 15 + 1 + + + SPI2LPEN + SPI2 clock enable during Sleep + mode + 14 + 1 + + + WWDGLPEN + Window watchdog clock enable during + Sleep mode + 11 + 1 + + + TIM14LPEN + TIM14 clock enable during Sleep + mode + 8 + 1 + + + TIM13LPEN + TIM13 clock enable during Sleep + mode + 7 + 1 + + + TIM12LPEN + TIM12 clock enable during Sleep + mode + 6 + 1 + + + TIM7LPEN + TIM7 clock enable during Sleep + mode + 5 + 1 + + + TIM6LPEN + TIM6 clock enable during Sleep + mode + 4 + 1 + + + TIM5LPEN + TIM5 clock enable during Sleep + mode + 3 + 1 + + + TIM4LPEN + TIM4 clock enable during Sleep + mode + 2 + 1 + + + TIM3LPEN + TIM3 clock enable during Sleep + mode + 1 + 1 + + + TIM2LPEN + TIM2 clock enable during Sleep + mode + 0 + 1 + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power + mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM11LPEN + TIM11 clock enable during Sleep + mode + 18 + 1 + + + TIM10LPEN + TIM10 clock enable during Sleep + mode + 17 + 1 + + + TIM9LPEN + TIM9 clock enable during sleep + mode + 16 + 1 + + + SYSCFGLPEN + System configuration controller clock + enable during Sleep mode + 14 + 1 + + + SPI1LPEN + SPI 1 clock enable during Sleep + mode + 12 + 1 + + + SDIOLPEN + SDIO clock enable during Sleep + mode + 11 + 1 + + + ADC3LPEN + ADC 3 clock enable during Sleep + mode + 10 + 1 + + + ADC2LPEN + ADC2 clock enable during Sleep + mode + 9 + 1 + + + ADC1LPEN + ADC1 clock enable during Sleep + mode + 8 + 1 + + + USART6LPEN + USART6 clock enable during Sleep + mode + 5 + 1 + + + USART1LPEN + USART1 clock enable during Sleep + mode + 4 + 1 + + + TIM8LPEN + TIM8 clock enable during Sleep + mode + 1 + 1 + + + TIM1LPEN + TIM1 clock enable during Sleep + mode + 0 + 1 + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL1 + RTC clock source selection + 9 + 1 + read-write + + + RTCSEL0 + RTC clock source selection + 8 + 1 + read-write + + + LSEBYP + External low-speed oscillator + bypass + 2 + 1 + read-write + + + LSERDY + External low-speed oscillator + ready + 1 + 1 + read-only + + + LSEON + External low-speed oscillator + enable + 0 + 1 + read-write + + + + + CSR + CSR + clock control & status + register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + WDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator + ready + 1 + 1 + read-only + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + SSCGR + SSCGR + spread spectrum clock generation + register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation + enable + 31 + 1 + + + SPREADSEL + Spread Select + 30 + 1 + + + INCSTEP + Incrementation step + 13 + 15 + + + MODPER + Modulation period + 0 + 13 + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SRx + PLLI2S division factor for I2S + clocks + 28 + 3 + + + PLLI2SNx + PLLI2S multiplication factor for + VCO + 6 + 9 + + + + + + + GPIOI + General-purpose I/Os + GPIO + 0x40022000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOH + 0x40021C00 + + + GPIOG + 0x40021800 + + + GPIOF + 0x40021400 + + + GPIOE + 0x40021000 + + + GPIOD + 0X40020C00 + + + GPIOC + 0x40020800 + + + GPIOJ + 0x40022400 + + + GPIOK + 0x40022800 + + + GPIOB + General-purpose I/Os + GPIO + 0x40020400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000280 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRM + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + MEM_MODE + 0 + 2 + + + + + PMC + PMC + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + Ethernet PHY interface + selection + 23 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control + register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell + power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + FRF + Frame format + 4 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2S2ext + 0x40003400 + + + I2S3ext + 0x40004000 + + + SDIO + Secure digital input/output + interface + SDIO + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132. + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132. + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132. + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132. + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x51 + registers + + + ADC + ADC1, ADC2 and ADC3 global interrupts + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + + RES + Resolution + 24 + 2 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 30 + 1 + + + EXTEN + External trigger enable for regular + channels + 28 + 2 + + + EXTSEL + External event select for regular + group + 24 + 4 + + + JSWSTART + Start conversion of injected + channels + 22 + 1 + + + JEXTEN + External trigger enable for injected + channels + 20 + 2 + + + JEXTSEL + External event select for injected + group + 16 + 4 + + + ALIGN + Data alignment + 11 + 1 + + + EOCS + End of conversion + selection + 10 + 1 + + + DDS + DMA disable selection (for single ADC + mode) + 9 + 1 + + + DMA + Direct memory access mode (for single + ADC mode) + 8 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D Converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + JDR1 + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR2 + JDR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR3 + JDR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR4 + JDR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + + ADC3 + 0x40012200 + + + USART6 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011400 + + 0x0 + 0x400 + registers + + + USART6 + USART6 global interrupt + 71 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART1 + 0x40011000 + + USART1 + USART1 global interrupt + 37 + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + FPDS + Flash power down in Stop + mode + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + PLS + PVD level selection + 5 + 3 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + LPDS + Low-power deep sleep + 0 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output + selection ready bit + 14 + 1 + read-write + + + + + + + I2C3 + Inter-integrated circuit + I2C + 0x40005C00 + + 0x0 + 0x400 + registers + + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + ADD10 + Interface address + 8 + 2 + + + ADD7 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C1 + 0x40005400 + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0000h) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x7F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x7F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + Timer base + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTC_Alarm + RTC Alarms (A and B) through EXTI line + interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + + + OSEL + Output selection + 21 + 2 + + + POL + Output polarity + 20 + 1 + + + BKP + Backup + 18 + 1 + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + DCE + Coarse digital calibration + enable + 7 + 1 + + + FMT + Hour format + 6 + 1 + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + TAMPER2 detection flag + 14 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + CALIBR + CALIBR + calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCS + Digital calibration sign + 7 + 1 + + + DC + Digital calibration + 0 + 5 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + UART4 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + C_ADC + Common ADC registers + ADC + 0x40012300 + + 0x0 + 0x400 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + STRT3 + Regular channel Start flag of ADC + 3 + 20 + 1 + + + JSTRT3 + Injected channel Start flag of ADC + 3 + 19 + 1 + + + JEOC3 + Injected channel end of conversion of + ADC 3 + 18 + 1 + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + AWD3 + Analog watchdog flag of ADC + 3 + 16 + 1 + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + STRT2 + Regular channel Start flag of ADC + 2 + 12 + 1 + + + JSTRT2 + Injected channel Start flag of ADC + 2 + 11 + 1 + + + JEOC2 + Injected channel end of conversion of + ADC 2 + 10 + 1 + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + AWD2 + Analog watchdog flag of ADC + 2 + 8 + 1 + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + + STRT1 + Regular channel Start flag of ADC + 1 + 4 + 1 + + + JSTRT1 + Injected channel Start flag of ADC + 1 + 3 + 1 + + + JEOC1 + Injected channel end of conversion of + ADC 1 + 2 + 1 + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + + AWD1 + Analog watchdog flag of ADC + 1 + 0 + 1 + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + VBATE + VBAT enable + 22 + 1 + + + ADCPRE + ADC prescaler + 16 + 2 + + + DMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + DDS + DMA disable selection for multi-ADC + mode + 13 + 1 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + MULT + Multi ADC mode selection + 0 + 5 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular + conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular + conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + + TIM8 + 0x40010400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1PE + OC1PE + 3 + 1 + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + OC4CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + OC4PE + OC4PE + 11 + 1 + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + + OC3PE + OC3PE + 3 + 1 + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value + 16 + 16 + + + CNT_L + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 + value + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 + value + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR + OR + TIM5 option register + 0x50 + 0x20 + read-write + 0x0000 + + + ITR1_RMP + Timer Input 4 remap + 10 + 2 + + + + + + + TIM3 + General purpose timers + TIM + 0x40000400 + + 0x0 + 0x400 + registers + + + TIM3 + TIM3 global interrupt + 29 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1PE + OC1PE + 3 + 1 + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + OC4CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + OC4PE + OC4PE + 11 + 1 + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + + OC3PE + OC3PE + 3 + 1 + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value + 16 + 16 + + + CNT_L + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 + value + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 + value + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + + TIM5 + General-purpose-timers + TIM + 0x40000C00 + + 0x0 + 0x400 + registers + + + TIM5 + TIM5 global interrupt + 50 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1PE + OC1PE + 3 + 1 + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + OC4CE + 15 + 1 + + + OC4M + OC4M + 12 + 3 + + + OC4PE + OC4PE + 11 + 1 + + + OC4FE + OC4FE + 10 + 1 + + + CC4S + CC4S + 8 + 2 + + + OC3CE + OC3CE + 7 + 1 + + + OC3M + OC3M + 4 + 3 + + + OC3PE + OC3PE + 3 + 1 + + + OC3FE + OC3FE + 2 + 1 + + + CC3S + CC3S + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value + 16 + 16 + + + CNT_L + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 + value + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 + value + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR + OR + TIM5 option register + 0x50 + 0x20 + read-write + 0x0000 + + + IT4_RMP + Timer Input 4 remap + 6 + 2 + + + + + + + TIM9 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 3 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 3 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + + + TIM12 + 0x40001800 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + + TIM10 + General-purpose-timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + + + TIM13 + 0x40001C00 + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + + TIM14 + 0x40002000 + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + + TIM11 + General-purpose-timers + TIM + 0x40014800 + + 0x0 + 0x400 + registers + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + OR + OR + option register + 0x50 + 0x20 + read-write + 0x00000000 + + + RMP + Input 1 remapping + capability + 0 + 2 + + + + + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + Ethernet_MAC + Ethernet: media access control + (MAC) + Ethernet + 0x40028000 + + 0x0 + 0x61 + registers + + + ETH + Ethernet global interrupt + 61 + + + ETH_WKUP + Ethernet Wakeup through EXTI line + interrupt + 62 + + + + MACCR + MACCR + Ethernet MAC configuration + register + 0x0 + 0x20 + read-write + 0x0008000 + + + RE + RE + 2 + 1 + + + TE + TE + 3 + 1 + + + DC + DC + 4 + 1 + + + BL + BL + 5 + 2 + + + APCS + APCS + 7 + 1 + + + RD + RD + 9 + 1 + + + IPCO + IPCO + 10 + 1 + + + DM + DM + 11 + 1 + + + LM + LM + 12 + 1 + + + ROD + ROD + 13 + 1 + + + FES + FES + 14 + 1 + + + CSD + CSD + 16 + 1 + + + IFG + IFG + 17 + 3 + + + JD + JD + 22 + 1 + + + WD + WD + 23 + 1 + + + CSTF + CSTF + 25 + 1 + + + + + MACFFR + MACFFR + Ethernet MAC frame filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + PM + PM + 0 + 1 + + + HU + HU + 1 + 1 + + + HM + HM + 2 + 1 + + + DAIF + DAIF + 3 + 1 + + + RAM + RAM + 4 + 1 + + + BFD + BFD + 5 + 1 + + + PCF + PCF + 6 + 1 + + + SAIF + SAIF + 7 + 1 + + + SAF + SAF + 8 + 1 + + + HPF + HPF + 9 + 1 + + + RA + RA + 31 + 1 + + + + + MACHTHR + MACHTHR + Ethernet MAC hash table high + register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + HTH + 0 + 32 + + + + + MACHTLR + MACHTLR + Ethernet MAC hash table low + register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + HTL + 0 + 32 + + + + + MACMIIAR + MACMIIAR + Ethernet MAC MII address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MB + 0 + 1 + + + MW + MW + 1 + 1 + + + CR + CR + 2 + 3 + + + MR + MR + 6 + 5 + + + PA + PA + 11 + 5 + + + + + MACMIIDR + MACMIIDR + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + TD + TD + 0 + 16 + + + + + MACFCR + MACFCR + Ethernet MAC flow control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB + FCB + 0 + 1 + + + TFCE + TFCE + 1 + 1 + + + RFCE + RFCE + 2 + 1 + + + UPFD + UPFD + 3 + 1 + + + PLT + PLT + 4 + 2 + + + ZQPD + ZQPD + 7 + 1 + + + PT + PT + 16 + 16 + + + + + MACVLANTR + MACVLANTR + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VLANTI + VLANTI + 0 + 16 + + + VLANTC + VLANTC + 16 + 1 + + + + + MACPMTCSR + MACPMTCSR + Ethernet MAC PMT control and status + register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + PD + 0 + 1 + + + MPE + MPE + 1 + 1 + + + WFE + WFE + 2 + 1 + + + MPR + MPR + 5 + 1 + + + WFR + WFR + 6 + 1 + + + GU + GU + 9 + 1 + + + WFFRPR + WFFRPR + 31 + 1 + + + + + MACDBGR + MACDBGR + Ethernet MAC debug register + 0x34 + 0x20 + read-only + 0x00000000 + + + CR + CR + 0 + 1 + + + CSR + CSR + 1 + 1 + + + ROR + ROR + 2 + 1 + + + MCF + MCF + 3 + 1 + + + MCP + MCP + 4 + 1 + + + MCFHP + MCFHP + 5 + 1 + + + + + MACSR + MACSR + Ethernet MAC interrupt status + register + 0x38 + 0x20 + 0x00000000 + + + PMTS + PMTS + 3 + 1 + read-only + + + MMCS + MMCS + 4 + 1 + read-only + + + MMCRS + MMCRS + 5 + 1 + read-only + + + MMCTS + MMCTS + 6 + 1 + read-only + + + TSTS + TSTS + 9 + 1 + read-write + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask + register + 0x3C + 0x20 + read-write + 0x00000000 + + + PMTIM + PMTIM + 3 + 1 + + + TSTIM + TSTIM + 9 + 1 + + + + + MACA0HR + MACA0HR + Ethernet MAC address 0 high + register + 0x40 + 0x20 + 0x0010FFFF + + + MACA0H + MAC address0 high + 0 + 16 + read-write + + + MO + Always 1 + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Ethernet MAC address 0 low + register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MACA0L + 0 + 0 + 32 + + + + + MACA1HR + MACA1HR + Ethernet MAC address 1 high + register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MACA1H + MACA1H + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA1LR + MACA1LR + Ethernet MAC address1 low + register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MACA1LR + MACA1LR + 0 + 32 + + + + + MACA2HR + MACA2HR + Ethernet MAC address 2 high + register + 0x50 + 0x20 + read-write + 0x0000FFFF + + + MAC2AH + MAC2AH + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA2LR + MACA2LR + Ethernet MAC address 2 low + register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MACA2L + MACA2L + 0 + 31 + + + + + MACA3HR + MACA3HR + Ethernet MAC address 3 high + register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MACA3H + MACA3H + 0 + 16 + + + MBC + MBC + 24 + 6 + + + SA + SA + 30 + 1 + + + AE + AE + 31 + 1 + + + + + MACA3LR + MACA3LR + Ethernet MAC address 3 low + register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MBCA3L + MBCA3L + 0 + 32 + + + + + + + Ethernet_MMC + Ethernet: MAC management counters + Ethernet + 0x40028100 + + 0x0 + 0x400 + registers + + + + MMCCR + MMCCR + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CR + CR + 0 + 1 + + + CSR + CSR + 1 + 1 + + + ROR + ROR + 2 + 1 + + + MCF + MCF + 3 + 1 + + + MCP + MCP + 4 + 1 + + + MCFHP + MCFHP + 5 + 1 + + + + + MMCRIR + MMCRIR + Ethernet MMC receive interrupt + register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCES + RFCES + 5 + 1 + + + RFAES + RFAES + 6 + 1 + + + RGUFS + RGUFS + 17 + 1 + + + + + MMCTIR + MMCTIR + Ethernet MMC transmit interrupt + register + 0x8 + 0x20 + read-only + 0x00000000 + + + TGFSCS + TGFSCS + 14 + 1 + + + TGFMSCS + TGFMSCS + 15 + 1 + + + TGFS + TGFS + 21 + 1 + + + + + MMCRIMR + MMCRIMR + Ethernet MMC receive interrupt mask + register + 0xC + 0x20 + read-write + 0x00000000 + + + RFCEM + RFCEM + 5 + 1 + + + RFAEM + RFAEM + 6 + 1 + + + RGUFM + RGUFM + 17 + 1 + + + + + MMCTIMR + MMCTIMR + Ethernet MMC transmit interrupt mask + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TGFSCM + TGFSCM + 14 + 1 + + + TGFMSCM + TGFMSCM + 15 + 1 + + + TGFM + TGFM + 16 + 1 + + + + + MMCTGFSCCR + MMCTGFSCCR + Ethernet MMC transmitted good frames after a + single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + TGFSCC + 0 + 32 + + + + + MMCTGFMSCCR + MMCTGFMSCCR + Ethernet MMC transmitted good frames after + more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + TGFMSCC + 0 + 32 + + + + + MMCTGFCR + MMCTGFCR + Ethernet MMC transmitted good frames counter + register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + HTL + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error + counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + RFCFC + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment + error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + RFAEC + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + RGUFC + 0 + 32 + + + + + + + Ethernet_PTP + Ethernet: Precision time protocol + Ethernet + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control + register + 0x0 + 0x20 + read-write + 0x00002000 + + + TSE + TSE + 0 + 1 + + + TSFCU + TSFCU + 1 + 1 + + + TSPTPPSV2E + TSPTPPSV2E + 10 + 1 + + + TSSPTPOEFE + TSSPTPOEFE + 11 + 1 + + + TSSIPV6FE + TSSIPV6FE + 12 + 1 + + + TSSIPV4FE + TSSIPV4FE + 13 + 1 + + + TSSEME + TSSEME + 14 + 1 + + + TSSMRME + TSSMRME + 15 + 1 + + + TSCNT + TSCNT + 16 + 2 + + + TSPFFMAE + TSPFFMAE + 18 + 1 + + + TSSTI + TSSTI + 2 + 1 + + + TSSTU + TSSTU + 3 + 1 + + + TSITE + TSITE + 4 + 1 + + + TTSARU + TTSARU + 5 + 1 + + + TSSARFE + TSSARFE + 8 + 1 + + + TSSSR + TSSSR + 9 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment + register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + STSSI + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high + register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + STS + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low + register + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + STSS + 0 + 31 + + + STPNS + STPNS + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + TSUS + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update + register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + TSUSS + 0 + 31 + + + TSUPNS + TSUPNS + 31 + 1 + + + + + PTPTSAR + PTPTSAR + Ethernet PTP time stamp addend + register + 0x18 + 0x20 + read-write + 0x00000000 + + + TSA + TSA + 0 + 32 + + + + + PTPTTHR + PTPTTHR + Ethernet PTP target time high + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSH + 0 + 0 + 32 + + + + + PTPTTLR + PTPTTLR + Ethernet PTP target time low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTSL + TTSL + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status + register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSSO + TSSO + 0 + 1 + + + TSTTR + TSTTR + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control + register + 0x2C + 0x20 + read-only + 0x00000000 + + + TSSO + TSSO + 0 + 1 + + + TSTTR + TSTTR + 1 + 1 + + + + + + + Ethernet_DMA + Ethernet: DMA controller operation + Ethernet + 0x40029000 + + 0x0 + 0x400 + registers + + + + DMABMR + DMABMR + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x00002101 + + + SR + SR + 0 + 1 + + + DA + DA + 1 + 1 + + + DSL + DSL + 2 + 5 + + + EDFE + EDFE + 7 + 1 + + + PBL + PBL + 8 + 6 + + + RTPR + RTPR + 14 + 2 + + + FB + FB + 16 + 1 + + + RDP + RDP + 17 + 6 + + + USP + USP + 23 + 1 + + + FPM + FPM + 24 + 1 + + + AAB + AAB + 25 + 1 + + + MB + MB + 26 + 1 + + + + + DMATPDR + DMATPDR + Ethernet DMA transmit poll demand + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + TPD + 0 + 32 + + + + + DMARPDR + DMARPDR + EHERNET DMA receive poll demand + register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + RPD + 0 + 32 + + + + + DMARDLAR + DMARDLAR + Ethernet DMA receive descriptor list address + register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + SRL + 0 + 32 + + + + + DMATDLAR + DMATDLAR + Ethernet DMA transmit descriptor list + address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + STL + 0 + 32 + + + + + DMASR + DMASR + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TS + TS + 0 + 1 + read-write + + + TPSS + TPSS + 1 + 1 + read-write + + + TBUS + TBUS + 2 + 1 + read-write + + + TJTS + TJTS + 3 + 1 + read-write + + + ROS + ROS + 4 + 1 + read-write + + + TUS + TUS + 5 + 1 + read-write + + + RS + RS + 6 + 1 + read-write + + + RBUS + RBUS + 7 + 1 + read-write + + + RPSS + RPSS + 8 + 1 + read-write + + + PWTS + PWTS + 9 + 1 + read-write + + + ETS + ETS + 10 + 1 + read-write + + + FBES + FBES + 13 + 1 + read-write + + + ERS + ERS + 14 + 1 + read-write + + + AIS + AIS + 15 + 1 + read-write + + + NIS + NIS + 16 + 1 + read-write + + + RPS + RPS + 17 + 3 + read-only + + + TPS + TPS + 20 + 3 + read-only + + + EBS + EBS + 23 + 3 + read-only + + + MMCS + MMCS + 27 + 1 + read-only + + + PMTS + PMTS + 28 + 1 + read-only + + + TSTS + TSTS + 29 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode + register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + SR + 1 + 1 + + + OSF + OSF + 2 + 1 + + + RTC + RTC + 3 + 2 + + + FUGF + FUGF + 6 + 1 + + + FEF + FEF + 7 + 1 + + + ST + ST + 13 + 1 + + + TTC + TTC + 14 + 3 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DFRF + DFRF + 24 + 1 + + + RSF + RSF + 25 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 1 + + + TPSIE + TPSIE + 1 + 1 + + + TBUIE + TBUIE + 2 + 1 + + + TJTIE + TJTIE + 3 + 1 + + + ROIE + ROIE + 4 + 1 + + + TUIE + TUIE + 5 + 1 + + + RIE + RIE + 6 + 1 + + + RBUIE + RBUIE + 7 + 1 + + + RPSIE + RPSIE + 8 + 1 + + + RWTIE + RWTIE + 9 + 1 + + + ETIE + ETIE + 10 + 1 + + + FBEIE + FBEIE + 13 + 1 + + + ERIE + ERIE + 14 + 1 + + + AISE + AISE + 15 + 1 + + + NISE + NISE + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + MFC + MFC + 0 + 16 + + + OMFC + OMFC + 16 + 1 + + + MFA + MFA + 17 + 11 + + + OFOC + OFOC + 28 + 1 + + + + + DMARSWTR + DMARSWTR + Ethernet DMA receive status watchdog timer + register + 0x24 + 0x20 + read-write + 0x00000000 + + + RSWTC + RSWTC + 0 + 8 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + HTDAP + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + HRDAP + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + HTBAP + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + HRBAP + 0 + 32 + + + + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + CR + Control regidter + 0 + 1 + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host + mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size + register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics + register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics + register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics + register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics + register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics + register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics + register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics + register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register + (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register + (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register + (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register + (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register + (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register + (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register + (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register + (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register + (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register + (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register + (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register + (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register + (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + DOEPCTL1 + DOEPCTL1 + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + device endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + device endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DTXFSTS0 + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTG_FS device IN endpoint transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTG_FS device IN endpoint transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + FS_PCGCCTL + FS_PCGCCTL + OTG_FS power and clock gating control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupts + 19 + + + CAN1_RX0 + CAN1 RX0 interrupts + 20 + + + CAN1_RX1 + CAN1 RX1 interrupts + 21 + + + CAN1_SCE + CAN1 SCE interrupt + 22 + + + + MCR + MCR + master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + MSR + MSR + master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + TSR + TSR + transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox + 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox + 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox + 0 + 29 + 1 + read-only + + + TME2 + Lowest priority flag for mailbox + 2 + 28 + 1 + read-only + + + TME1 + Lowest priority flag for mailbox + 1 + 27 + 1 + read-only + + + TME0 + Lowest priority flag for mailbox + 0 + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 1 + read-write + + + ALST1 + ALST1 + 10 + 1 + read-write + + + TXOK1 + TXOK1 + 9 + 1 + read-write + + + RQCP1 + RQCP1 + 8 + 1 + read-write + + + ABRQ0 + ABRQ0 + 7 + 1 + read-write + + + TERR0 + TERR0 + 3 + 1 + read-write + + + ALST0 + ALST0 + 2 + 1 + read-write + + + TXOK0 + TXOK0 + 1 + 1 + read-write + + + RQCP0 + RQCP0 + 0 + 1 + read-write + + + + + RF0R + RF0R + receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RFOM0 + RFOM0 + 5 + 1 + read-write + + + FOVR0 + FOVR0 + 4 + 1 + read-write + + + FULL0 + FULL0 + 3 + 1 + read-write + + + FMP0 + FMP0 + 0 + 2 + read-only + + + + + RF1R + RF1R + receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + RFOM1 + 5 + 1 + read-write + + + FOVR1 + FOVR1 + 4 + 1 + read-write + + + FULL1 + FULL1 + 3 + 1 + read-write + + + FMP1 + FMP1 + 0 + 2 + read-only + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + SLKIE + 17 + 1 + + + WKUIE + WKUIE + 16 + 1 + + + ERRIE + ERRIE + 15 + 1 + + + LECIE + LECIE + 11 + 1 + + + BOFIE + BOFIE + 10 + 1 + + + EPVIE + EPVIE + 9 + 1 + + + EWGIE + EWGIE + 8 + 1 + + + FOVIE1 + FOVIE1 + 6 + 1 + + + FFIE1 + FFIE1 + 5 + 1 + + + FMPIE1 + FMPIE1 + 4 + 1 + + + FOVIE0 + FOVIE0 + 3 + 1 + + + FFIE0 + FFIE0 + 2 + 1 + + + FMPIE0 + FMPIE0 + 1 + 1 + + + TMEIE + TMEIE + 0 + 1 + + + + + ESR + ESR + interrupt enable register + 0x18 + 0x20 + 0x00000000 + + + REC + REC + 24 + 8 + read-only + + + TEC + TEC + 16 + 8 + read-only + + + LEC + LEC + 4 + 3 + read-write + + + BOFF + BOFF + 2 + 1 + read-only + + + EPVF + EPVF + 1 + 1 + read-only + + + EWGF + EWGF + 0 + 1 + read-only + + + + + BTR + BTR + bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + SILM + SILM + 31 + 1 + + + LBKM + LBKM + 30 + 1 + + + SJW + SJW + 24 + 2 + + + TS2 + TS2 + 20 + 3 + + + TS1 + TS1 + 16 + 4 + + + BRP + BRP + 0 + 10 + + + + + TI0R + TI0R + TX mailbox identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + TDT0R + TDT0R + mailbox data length control and time stamp + register + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + TDL0R + TDL0R + mailbox data low register + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + TDH0R + TDH0R + mailbox data high register + 0x18C + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + TI1R + TI1R + mailbox identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + TDT1R + TDT1R + mailbox data length control and time stamp + register + 0x194 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + TDL1R + TDL1R + mailbox data low register + 0x198 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + TDH1R + TDH1R + mailbox data high register + 0x19C + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + TI2R + TI2R + mailbox identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + TDT2R + TDT2R + mailbox data length control and time stamp + register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + TDL2R + TDL2R + mailbox data low register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + TDH2R + TDH2R + mailbox data high register + 0x1AC + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + RI0R + RI0R + receive FIFO mailbox identifier + register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + + + RDT0R + RDT0R + mailbox data high register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + + + RDL0R + RDL0R + mailbox data high register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + RDH0R + RDH0R + receive FIFO mailbox data high + register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + RI1R + RI1R + mailbox data high register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + + + RDT1R + RDT1R + mailbox data high register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + TIME + TIME + 16 + 16 + + + FMI + FMI + 8 + 8 + + + DLC + DLC + 0 + 4 + + + + + RDL1R + RDL1R + mailbox data high register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + RDH1R + RDH1R + mailbox data high register + 0x1CC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + FMR + FMR + filter master register + 0x200 + 0x20 + read-write + 0x2A1C0E01 + + + CAN2SB + CAN2SB + 8 + 6 + + + FINIT + FINIT + 0 + 1 + + + + + FM1R + FM1R + filter mode register + 0x204 + 0x20 + read-write + 0x00000000 + + + FBM0 + Filter mode + 0 + 1 + + + FBM1 + Filter mode + 1 + 1 + + + FBM2 + Filter mode + 2 + 1 + + + FBM3 + Filter mode + 3 + 1 + + + FBM4 + Filter mode + 4 + 1 + + + FBM5 + Filter mode + 5 + 1 + + + FBM6 + Filter mode + 6 + 1 + + + FBM7 + Filter mode + 7 + 1 + + + FBM8 + Filter mode + 8 + 1 + + + FBM9 + Filter mode + 9 + 1 + + + FBM10 + Filter mode + 10 + 1 + + + FBM11 + Filter mode + 11 + 1 + + + FBM12 + Filter mode + 12 + 1 + + + FBM13 + Filter mode + 13 + 1 + + + FBM14 + Filter mode + 14 + 1 + + + FBM15 + Filter mode + 15 + 1 + + + FBM16 + Filter mode + 16 + 1 + + + FBM17 + Filter mode + 17 + 1 + + + FBM18 + Filter mode + 18 + 1 + + + FBM19 + Filter mode + 19 + 1 + + + FBM20 + Filter mode + 20 + 1 + + + FBM21 + Filter mode + 21 + 1 + + + FBM22 + Filter mode + 22 + 1 + + + FBM23 + Filter mode + 23 + 1 + + + FBM24 + Filter mode + 24 + 1 + + + FBM25 + Filter mode + 25 + 1 + + + FBM26 + Filter mode + 26 + 1 + + + FBM27 + Filter mode + 27 + 1 + + + + + FS1R + FS1R + filter scale register + 0x20C + 0x20 + read-write + 0x00000000 + + + FSC0 + Filter scale configuration + 0 + 1 + + + FSC1 + Filter scale configuration + 1 + 1 + + + FSC2 + Filter scale configuration + 2 + 1 + + + FSC3 + Filter scale configuration + 3 + 1 + + + FSC4 + Filter scale configuration + 4 + 1 + + + FSC5 + Filter scale configuration + 5 + 1 + + + FSC6 + Filter scale configuration + 6 + 1 + + + FSC7 + Filter scale configuration + 7 + 1 + + + FSC8 + Filter scale configuration + 8 + 1 + + + FSC9 + Filter scale configuration + 9 + 1 + + + FSC10 + Filter scale configuration + 10 + 1 + + + FSC11 + Filter scale configuration + 11 + 1 + + + FSC12 + Filter scale configuration + 12 + 1 + + + FSC13 + Filter scale configuration + 13 + 1 + + + FSC14 + Filter scale configuration + 14 + 1 + + + FSC15 + Filter scale configuration + 15 + 1 + + + FSC16 + Filter scale configuration + 16 + 1 + + + FSC17 + Filter scale configuration + 17 + 1 + + + FSC18 + Filter scale configuration + 18 + 1 + + + FSC19 + Filter scale configuration + 19 + 1 + + + FSC20 + Filter scale configuration + 20 + 1 + + + FSC21 + Filter scale configuration + 21 + 1 + + + FSC22 + Filter scale configuration + 22 + 1 + + + FSC23 + Filter scale configuration + 23 + 1 + + + FSC24 + Filter scale configuration + 24 + 1 + + + FSC25 + Filter scale configuration + 25 + 1 + + + FSC26 + Filter scale configuration + 26 + 1 + + + FSC27 + Filter scale configuration + 27 + 1 + + + + + FFA1R + FFA1R + filter FIFO assignment + register + 0x214 + 0x20 + read-write + 0x00000000 + + + FFA0 + Filter FIFO assignment for filter + 0 + 0 + 1 + + + FFA1 + Filter FIFO assignment for filter + 1 + 1 + 1 + + + FFA2 + Filter FIFO assignment for filter + 2 + 2 + 1 + + + FFA3 + Filter FIFO assignment for filter + 3 + 3 + 1 + + + FFA4 + Filter FIFO assignment for filter + 4 + 4 + 1 + + + FFA5 + Filter FIFO assignment for filter + 5 + 5 + 1 + + + FFA6 + Filter FIFO assignment for filter + 6 + 6 + 1 + + + FFA7 + Filter FIFO assignment for filter + 7 + 7 + 1 + + + FFA8 + Filter FIFO assignment for filter + 8 + 8 + 1 + + + FFA9 + Filter FIFO assignment for filter + 9 + 9 + 1 + + + FFA10 + Filter FIFO assignment for filter + 10 + 10 + 1 + + + FFA11 + Filter FIFO assignment for filter + 11 + 11 + 1 + + + FFA12 + Filter FIFO assignment for filter + 12 + 12 + 1 + + + FFA13 + Filter FIFO assignment for filter + 13 + 13 + 1 + + + FFA14 + Filter FIFO assignment for filter + 14 + 14 + 1 + + + FFA15 + Filter FIFO assignment for filter + 15 + 15 + 1 + + + FFA16 + Filter FIFO assignment for filter + 16 + 16 + 1 + + + FFA17 + Filter FIFO assignment for filter + 17 + 17 + 1 + + + FFA18 + Filter FIFO assignment for filter + 18 + 18 + 1 + + + FFA19 + Filter FIFO assignment for filter + 19 + 19 + 1 + + + FFA20 + Filter FIFO assignment for filter + 20 + 20 + 1 + + + FFA21 + Filter FIFO assignment for filter + 21 + 21 + 1 + + + FFA22 + Filter FIFO assignment for filter + 22 + 22 + 1 + + + FFA23 + Filter FIFO assignment for filter + 23 + 23 + 1 + + + FFA24 + Filter FIFO assignment for filter + 24 + 24 + 1 + + + FFA25 + Filter FIFO assignment for filter + 25 + 25 + 1 + + + FFA26 + Filter FIFO assignment for filter + 26 + 26 + 1 + + + FFA27 + Filter FIFO assignment for filter + 27 + 27 + 1 + + + + + FA1R + FA1R + filter activation register + 0x21C + 0x20 + read-write + 0x00000000 + + + FACT0 + Filter active + 0 + 1 + + + FACT1 + Filter active + 1 + 1 + + + FACT2 + Filter active + 2 + 1 + + + FACT3 + Filter active + 3 + 1 + + + FACT4 + Filter active + 4 + 1 + + + FACT5 + Filter active + 5 + 1 + + + FACT6 + Filter active + 6 + 1 + + + FACT7 + Filter active + 7 + 1 + + + FACT8 + Filter active + 8 + 1 + + + FACT9 + Filter active + 9 + 1 + + + FACT10 + Filter active + 10 + 1 + + + FACT11 + Filter active + 11 + 1 + + + FACT12 + Filter active + 12 + 1 + + + FACT13 + Filter active + 13 + 1 + + + FACT14 + Filter active + 14 + 1 + + + FACT15 + Filter active + 15 + 1 + + + FACT16 + Filter active + 16 + 1 + + + FACT17 + Filter active + 17 + 1 + + + FACT18 + Filter active + 18 + 1 + + + FACT19 + Filter active + 19 + 1 + + + FACT20 + Filter active + 20 + 1 + + + FACT21 + Filter active + 21 + 1 + + + FACT22 + Filter active + 22 + 1 + + + FACT23 + Filter active + 23 + 1 + + + FACT24 + Filter active + 24 + 1 + + + FACT25 + Filter active + 25 + 1 + + + FACT26 + Filter active + 26 + 1 + + + FACT27 + Filter active + 27 + 1 + + + + + F0R1 + F0R1 + Filter bank 0 register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F0R2 + F0R2 + Filter bank 0 register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R1 + F1R1 + Filter bank 1 register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R2 + F1R2 + Filter bank 1 register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R1 + F2R1 + Filter bank 2 register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R2 + F2R2 + Filter bank 2 register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R1 + F3R1 + Filter bank 3 register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R2 + F3R2 + Filter bank 3 register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R1 + F4R1 + Filter bank 4 register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R2 + F4R2 + Filter bank 4 register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R1 + F5R1 + Filter bank 5 register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R2 + F5R2 + Filter bank 5 register 2 + 0x26C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R1 + F6R1 + Filter bank 6 register 1 + 0x270 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R2 + F6R2 + Filter bank 6 register 2 + 0x274 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R1 + F7R1 + Filter bank 7 register 1 + 0x278 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R2 + F7R2 + Filter bank 7 register 2 + 0x27C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R1 + F8R1 + Filter bank 8 register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R2 + F8R2 + Filter bank 8 register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R1 + F9R1 + Filter bank 9 register 1 + 0x288 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R2 + F9R2 + Filter bank 9 register 2 + 0x28C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R1 + F10R1 + Filter bank 10 register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R2 + F10R2 + Filter bank 10 register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R1 + F11R1 + Filter bank 11 register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R2 + F11R2 + Filter bank 11 register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R1 + F12R1 + Filter bank 4 register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R2 + F12R2 + Filter bank 12 register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R1 + F13R1 + Filter bank 13 register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R2 + F13R2 + Filter bank 13 register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R1 + F14R1 + Filter bank 14 register 1 + 0x2B0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R2 + F14R2 + Filter bank 14 register 2 + 0x2B4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R1 + F15R1 + Filter bank 15 register 1 + 0x2B8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R2 + F15R2 + Filter bank 15 register 2 + 0x2BC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R1 + F16R1 + Filter bank 16 register 1 + 0x2C0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R2 + F16R2 + Filter bank 16 register 2 + 0x2C4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R1 + F17R1 + Filter bank 17 register 1 + 0x2C8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R2 + F17R2 + Filter bank 17 register 2 + 0x2CC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R1 + F18R1 + Filter bank 18 register 1 + 0x2D0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R2 + F18R2 + Filter bank 18 register 2 + 0x2D4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R1 + F19R1 + Filter bank 19 register 1 + 0x2D8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R2 + F19R2 + Filter bank 19 register 2 + 0x2DC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R1 + F20R1 + Filter bank 20 register 1 + 0x2E0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R2 + F20R2 + Filter bank 20 register 2 + 0x2E4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R1 + F21R1 + Filter bank 21 register 1 + 0x2E8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R2 + F21R2 + Filter bank 21 register 2 + 0x2EC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R1 + F22R1 + Filter bank 22 register 1 + 0x2F0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R2 + F22R2 + Filter bank 22 register 2 + 0x2F4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R1 + F23R1 + Filter bank 23 register 1 + 0x2F8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R2 + F23R2 + Filter bank 23 register 2 + 0x2FC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R1 + F24R1 + Filter bank 24 register 1 + 0x300 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R2 + F24R2 + Filter bank 24 register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R1 + F25R1 + Filter bank 25 register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R2 + F25R2 + Filter bank 25 register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R1 + F26R1 + Filter bank 26 register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R2 + F26R2 + Filter bank 26 register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R1 + F27R1 + Filter bank 27 register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R2 + F27R2 + Filter bank 27 register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupts + 63 + + + CAN2_RX0 + CAN2 RX0 interrupts + 64 + + + CAN2_RX1 + CAN2 RX1 interrupts + 65 + + + CAN2_SCE + CAN2 SCE interrupt + 66 + + + + FLASH + FLASH + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000000 + + + LATENCY + Latency + 0 + 3 + read-write + + + PRFTEN + Prefetch enable + 8 + 1 + read-write + + + ICEN + Instruction cache enable + 9 + 1 + read-write + + + DCEN + Data cache enable + 10 + 1 + read-write + + + ICRST + Instruction cache reset + 11 + 1 + write-only + + + DCRST + Data cache reset + 12 + 1 + read-write + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + WRPERR + Write protection error + 4 + 1 + read-write + + + PGAERR + Programming alignment + error + 5 + 1 + read-write + + + PGPERR + Programming parallelism + error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x80000000 + + + PG + Programming + 0 + 1 + + + SER + Sector Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + SNB + Sector number + 3 + 4 + + + PSIZE + Program size + 8 + 2 + + + STRT + Start + 16 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + LOCK + Lock + 31 + 1 + + + + + OPTCR + OPTCR + Flash option control register + 0x14 + 0x20 + read-write + 0x00000014 + + + OPTLOCK + Option lock + 0 + 1 + + + OPTSTRT + Option start + 1 + 1 + + + BOR_LEV + BOR reset Level + 2 + 2 + + + WDG_SW + WDG_SW User option bytes + 5 + 1 + + + nRST_STOP + nRST_STOP User option + bytes + 6 + 1 + + + nRST_STDBY + nRST_STDBY User option + bytes + 7 + 1 + + + RDP + Read protect + 8 + 8 + + + nWRP + Not write protect + 16 + 12 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40013C00 + + 0x0 + 0x400 + registers + + + TAMP_STAMP + Tamper and TimeStamp interrupts through the + EXTI line + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + PR19 + Pending bit 19 + 19 + 1 + + + PR20 + Pending bit 20 + 20 + 1 + + + PR21 + Pending bit 21 + 21 + 1 + + + PR22 + Pending bit 22 + 22 + 1 + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out global + interrupt + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In global + interrupt + 75 + + + OTG_HS_WKUP + USB On The Go HS Wakeup through EXTI + interrupt + 76 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA request signal + 30 + 1 + read-only + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_GNPTXFSIZ_Host + OTG_HS_GNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_TX0FSIZ_Peripheral + OTG_HS_TX0FSIZ_Peripheral + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_GNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + I2CPADEN + Enable I2C bus connection for the + external I2C PHY interface + 17 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + VBUS sensing disable + option + 21 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Peripheral + OTG_HS_GRXSTSR_Peripheral + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Peripheral + OTG_HS_GRXSTSP_Peripheral + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + RLDCTRL + Reload control + 16 + 1 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR11 + OTG_HS_HCCHAR11 + OTG_HS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR12 + OTG_HS_HCCHAR12 + OTG_HS host channel-12 characteristics + register + 0x280 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR13 + OTG_HS_HCCHAR13 + OTG_HS host channel-13 characteristics + register + 0x2A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR14 + OTG_HS_HCCHAR14 + OTG_HS host channel-14 characteristics + register + 0x2C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR15 + OTG_HS_HCCHAR15 + OTG_HS host channel-15 characteristics + register + 0x2E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 + OTG_HS_HCSPLT6 + OTG_HS host channel-6 split control + register + 0x1C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT7 + OTG_HS_HCSPLT7 + OTG_HS host channel-7 split control + register + 0x1E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT8 + OTG_HS_HCSPLT8 + OTG_HS host channel-8 split control + register + 0x204 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT9 + OTG_HS_HCSPLT9 + OTG_HS host channel-9 split control + register + 0x224 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT10 + OTG_HS_HCSPLT10 + OTG_HS host channel-10 split control + register + 0x244 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT11 + OTG_HS_HCSPLT11 + OTG_HS host channel-11 split control + register + 0x264 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT12 + OTG_HS_HCSPLT12 + OTG_HS host channel-12 split control + register + 0x284 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT13 + OTG_HS_HCSPLT13 + OTG_HS host channel-13 split control + register + 0x2A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT14 + OTG_HS_HCSPLT14 + OTG_HS host channel-14 split control + register + 0x2C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT15 + OTG_HS_HCSPLT15 + OTG_HS host channel-15 split control + register + 0x2E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT0 + OTG_HS_HCINT0 + OTG_HS host channel-11 interrupt + register + 0x108 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT1 + OTG_HS_HCINT1 + OTG_HS host channel-1 interrupt + register + 0x128 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT2 + OTG_HS_HCINT2 + OTG_HS host channel-2 interrupt + register + 0x148 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT3 + OTG_HS_HCINT3 + OTG_HS host channel-3 interrupt + register + 0x168 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT4 + OTG_HS_HCINT4 + OTG_HS host channel-4 interrupt + register + 0x188 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT5 + OTG_HS_HCINT5 + OTG_HS host channel-5 interrupt + register + 0x1A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT6 + OTG_HS_HCINT6 + OTG_HS host channel-6 interrupt + register + 0x1C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT7 + OTG_HS_HCINT7 + OTG_HS host channel-7 interrupt + register + 0x1E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT8 + OTG_HS_HCINT8 + OTG_HS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT9 + OTG_HS_HCINT9 + OTG_HS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT10 + OTG_HS_HCINT10 + OTG_HS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT11 + OTG_HS_HCINT11 + OTG_HS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT12 + OTG_HS_HCINT12 + OTG_HS host channel-12 interrupt + register + 0x288 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT13 + OTG_HS_HCINT13 + OTG_HS host channel-13 interrupt + register + 0x2A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT14 + OTG_HS_HCINT14 + OTG_HS host channel-14 interrupt + register + 0x2C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT15 + OTG_HS_HCINT15 + OTG_HS host channel-15 interrupt + register + 0x2E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK0 + OTG_HS_HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK2 + OTG_HS_HCINTMSK2 + OTG_HS host channel-2 interrupt mask + register + 0x14C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK12 + OTG_HS_HCINTMSK12 + OTG_HS host channel-12 interrupt mask + register + 0x28C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK13 + OTG_HS_HCINTMSK13 + OTG_HS host channel-13 interrupt mask + register + 0x2AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK14 + OTG_HS_HCINTMSK14 + OTG_HS host channel-14 interrupt mask + register + 0x2CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK15 + OTG_HS_HCINTMSK15 + OTG_HS host channel-15 interrupt mask + register + 0x2EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ12 + OTG_HS_HCTSIZ12 + OTG_HS host channel-12 transfer size + register + 0x290 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ13 + OTG_HS_HCTSIZ13 + OTG_HS host channel-13 transfer size + register + 0x2B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ14 + OTG_HS_HCTSIZ14 + OTG_HS host channel-14 transfer size + register + 0x2D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ15 + OTG_HS_HCTSIZ15 + OTG_HS host channel-15 transfer size + register + 0x2F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA12 + OTG_HS_HCDMA12 + OTG_HS host channel-12 DMA address + register + 0x294 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA13 + OTG_HS_HCDMA13 + OTG_HS host channel-13 DMA address + register + 0x2B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA14 + OTG_HS_HCDMA14 + OTG_HS host channel-14 DMA address + register + 0x2D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA15 + OTG_HS_HCDMA15 + OTG_HS host channel-15 DMA address + register + 0x2F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPEACHMSK1 + OTG_HS_DIEPEACHMSK1 + OTG_HS device each in endpoint-1 interrupt + register + 0x44 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + OTG_HS_DOEPEACHMSK1 + OTG_HS_DOEPEACHMSK1 + OTG_HS device each OUT endpoint-1 interrupt + register + 0x84 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + OUT packet error mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + BERRM + Bubble error interrupt + mask + 12 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + NYETM + NYET interrupt mask + 14 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-1 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-2 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-3 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-4 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-5 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + HASH + Hash processor + HASH + 0x50060400 + + 0x0 + 0x400 + registers + + + HASH_RNG + Hash and Rng global interrupt + 80 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + INIT + Initialize message digest + calculation + 2 + 1 + write-only + + + DMAE + DMA enable + 3 + 1 + read-write + + + DATATYPE + Data type selection + 4 + 2 + read-write + + + MODE + Mode selection + 6 + 1 + read-write + + + ALGO0 + Algorithm selection + 7 + 1 + read-write + + + NBW + Number of words already + pushed + 8 + 4 + read-only + + + DINNE + DIN not empty + 12 + 1 + read-only + + + MDMAT + Multiple DMA Transfers + 13 + 1 + read-write + + + LKEY + Long key selection + 16 + 1 + read-write + + + ALGO1 + ALGO + 18 + 1 + read-write + + + + + DIN + DIN + data input register + 0x4 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + STR + STR + start register + 0x8 + 0x20 + 0x00000000 + + + DCAL + Digest calculation + 8 + 1 + write-only + + + NBLW + Number of valid bits in the last word of + the message + 0 + 5 + read-write + + + + + HR0 + HR0 + digest registers + 0xC + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HR1 + HR1 + digest registers + 0x10 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HR2 + HR2 + digest registers + 0x14 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HR3 + HR3 + digest registers + 0x18 + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HR4 + HR4 + digest registers + 0x1C + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + IMR + IMR + interrupt enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + DCIE + Digest calculation completion interrupt + enable + 1 + 1 + + + DINIE + Data input interrupt + enable + 0 + 1 + + + + + SR + SR + status register + 0x24 + 0x20 + 0x00000001 + + + BUSY + Busy bit + 3 + 1 + read-only + + + DMAS + DMA Status + 2 + 1 + read-only + + + DCIS + Digest calculation completion interrupt + status + 1 + 1 + read-write + + + DINIS + Data input interrupt + status + 0 + 1 + read-write + + + + + CSR0 + CSR0 + context swap registers + 0xF8 + 0x20 + read-write + 0x00000000 + + + CSR0 + CSR0 + 0 + 32 + + + + + CSR1 + CSR1 + context swap registers + 0xFC + 0x20 + read-write + 0x00000000 + + + CSR1 + CSR1 + 0 + 32 + + + + + CSR2 + CSR2 + context swap registers + 0x100 + 0x20 + read-write + 0x00000000 + + + CSR2 + CSR2 + 0 + 32 + + + + + CSR3 + CSR3 + context swap registers + 0x104 + 0x20 + read-write + 0x00000000 + + + CSR3 + CSR3 + 0 + 32 + + + + + CSR4 + CSR4 + context swap registers + 0x108 + 0x20 + read-write + 0x00000000 + + + CSR4 + CSR4 + 0 + 32 + + + + + CSR5 + CSR5 + context swap registers + 0x10C + 0x20 + read-write + 0x00000000 + + + CSR5 + CSR5 + 0 + 32 + + + + + CSR6 + CSR6 + context swap registers + 0x110 + 0x20 + read-write + 0x00000000 + + + CSR6 + CSR6 + 0 + 32 + + + + + CSR7 + CSR7 + context swap registers + 0x114 + 0x20 + read-write + 0x00000000 + + + CSR7 + CSR7 + 0 + 32 + + + + + CSR8 + CSR8 + context swap registers + 0x118 + 0x20 + read-write + 0x00000000 + + + CSR8 + CSR8 + 0 + 32 + + + + + CSR9 + CSR9 + context swap registers + 0x11C + 0x20 + read-write + 0x00000000 + + + CSR9 + CSR9 + 0 + 32 + + + + + CSR10 + CSR10 + context swap registers + 0x120 + 0x20 + read-write + 0x00000000 + + + CSR10 + CSR10 + 0 + 32 + + + + + CSR11 + CSR11 + context swap registers + 0x124 + 0x20 + read-write + 0x00000000 + + + CSR11 + CSR11 + 0 + 32 + + + + + CSR12 + CSR12 + context swap registers + 0x128 + 0x20 + read-write + 0x00000000 + + + CSR12 + CSR12 + 0 + 32 + + + + + CSR13 + CSR13 + context swap registers + 0x12C + 0x20 + read-write + 0x00000000 + + + CSR13 + CSR13 + 0 + 32 + + + + + CSR14 + CSR14 + context swap registers + 0x130 + 0x20 + read-write + 0x00000000 + + + CSR14 + CSR14 + 0 + 32 + + + + + CSR15 + CSR15 + context swap registers + 0x134 + 0x20 + read-write + 0x00000000 + + + CSR15 + CSR15 + 0 + 32 + + + + + CSR16 + CSR16 + context swap registers + 0x138 + 0x20 + read-write + 0x00000000 + + + CSR16 + CSR16 + 0 + 32 + + + + + CSR17 + CSR17 + context swap registers + 0x13C + 0x20 + read-write + 0x00000000 + + + CSR17 + CSR17 + 0 + 32 + + + + + CSR18 + CSR18 + context swap registers + 0x140 + 0x20 + read-write + 0x00000000 + + + CSR18 + CSR18 + 0 + 32 + + + + + CSR19 + CSR19 + context swap registers + 0x144 + 0x20 + read-write + 0x00000000 + + + CSR19 + CSR19 + 0 + 32 + + + + + CSR20 + CSR20 + context swap registers + 0x148 + 0x20 + read-write + 0x00000000 + + + CSR20 + CSR20 + 0 + 32 + + + + + CSR21 + CSR21 + context swap registers + 0x14C + 0x20 + read-write + 0x00000000 + + + CSR21 + CSR21 + 0 + 32 + + + + + CSR22 + CSR22 + context swap registers + 0x150 + 0x20 + read-write + 0x00000000 + + + CSR22 + CSR22 + 0 + 32 + + + + + CSR23 + CSR23 + context swap registers + 0x154 + 0x20 + read-write + 0x00000000 + + + CSR23 + CSR23 + 0 + 32 + + + + + CSR24 + CSR24 + context swap registers + 0x158 + 0x20 + read-write + 0x00000000 + + + CSR24 + CSR24 + 0 + 32 + + + + + CSR25 + CSR25 + context swap registers + 0x15C + 0x20 + read-write + 0x00000000 + + + CSR25 + CSR25 + 0 + 32 + + + + + CSR26 + CSR26 + context swap registers + 0x160 + 0x20 + read-write + 0x00000000 + + + CSR26 + CSR26 + 0 + 32 + + + + + CSR27 + CSR27 + context swap registers + 0x164 + 0x20 + read-write + 0x00000000 + + + CSR27 + CSR27 + 0 + 32 + + + + + CSR28 + CSR28 + context swap registers + 0x168 + 0x20 + read-write + 0x00000000 + + + CSR28 + CSR28 + 0 + 32 + + + + + CSR29 + CSR29 + context swap registers + 0x16C + 0x20 + read-write + 0x00000000 + + + CSR29 + CSR29 + 0 + 32 + + + + + CSR30 + CSR30 + context swap registers + 0x170 + 0x20 + read-write + 0x00000000 + + + CSR30 + CSR30 + 0 + 32 + + + + + CSR31 + CSR31 + context swap registers + 0x174 + 0x20 + read-write + 0x00000000 + + + CSR31 + CSR31 + 0 + 32 + + + + + CSR32 + CSR32 + context swap registers + 0x178 + 0x20 + read-write + 0x00000000 + + + CSR32 + CSR32 + 0 + 32 + + + + + CSR33 + CSR33 + context swap registers + 0x17C + 0x20 + read-write + 0x00000000 + + + CSR33 + CSR33 + 0 + 32 + + + + + CSR34 + CSR34 + context swap registers + 0x180 + 0x20 + read-write + 0x00000000 + + + CSR34 + CSR34 + 0 + 32 + + + + + CSR35 + CSR35 + context swap registers + 0x184 + 0x20 + read-write + 0x00000000 + + + CSR35 + CSR35 + 0 + 32 + + + + + CSR36 + CSR36 + context swap registers + 0x188 + 0x20 + read-write + 0x00000000 + + + CSR36 + CSR36 + 0 + 32 + + + + + CSR37 + CSR37 + context swap registers + 0x18C + 0x20 + read-write + 0x00000000 + + + CSR37 + CSR37 + 0 + 32 + + + + + CSR38 + CSR38 + context swap registers + 0x190 + 0x20 + read-write + 0x00000000 + + + CSR38 + CSR38 + 0 + 32 + + + + + CSR39 + CSR39 + context swap registers + 0x194 + 0x20 + read-write + 0x00000000 + + + CSR39 + CSR39 + 0 + 32 + + + + + CSR40 + CSR40 + context swap registers + 0x198 + 0x20 + read-write + 0x00000000 + + + CSR40 + CSR40 + 0 + 32 + + + + + CSR41 + CSR41 + context swap registers + 0x19C + 0x20 + read-write + 0x00000000 + + + CSR41 + CSR41 + 0 + 32 + + + + + CSR42 + CSR42 + context swap registers + 0x1A0 + 0x20 + read-write + 0x00000000 + + + CSR42 + CSR42 + 0 + 32 + + + + + CSR43 + CSR43 + context swap registers + 0x1A4 + 0x20 + read-write + 0x00000000 + + + CSR43 + CSR43 + 0 + 32 + + + + + CSR44 + CSR44 + context swap registers + 0x1A8 + 0x20 + read-write + 0x00000000 + + + CSR44 + CSR44 + 0 + 32 + + + + + CSR45 + CSR45 + context swap registers + 0x1AC + 0x20 + read-write + 0x00000000 + + + CSR45 + CSR45 + 0 + 32 + + + + + CSR46 + CSR46 + context swap registers + 0x1B0 + 0x20 + read-write + 0x00000000 + + + CSR46 + CSR46 + 0 + 32 + + + + + CSR47 + CSR47 + context swap registers + 0x1B4 + 0x20 + read-write + 0x00000000 + + + CSR47 + CSR47 + 0 + 32 + + + + + CSR48 + CSR48 + context swap registers + 0x1B8 + 0x20 + read-write + 0x00000000 + + + CSR48 + CSR48 + 0 + 32 + + + + + CSR49 + CSR49 + context swap registers + 0x1BC + 0x20 + read-write + 0x00000000 + + + CSR49 + CSR49 + 0 + 32 + + + + + CSR50 + CSR50 + context swap registers + 0x1C0 + 0x20 + read-write + 0x00000000 + + + CSR50 + CSR50 + 0 + 32 + + + + + CSR51 + CSR51 + context swap registers + 0x1C4 + 0x20 + read-write + 0x00000000 + + + CSR51 + CSR51 + 0 + 32 + + + + + CSR52 + CSR52 + context swap registers + 0x1C8 + 0x20 + read-write + 0x00000000 + + + CSR52 + CSR52 + 0 + 32 + + + + + CSR53 + CSR53 + context swap registers + 0x1CC + 0x20 + read-write + 0x00000000 + + + CSR53 + CSR53 + 0 + 32 + + + + + HASH_HR0 + HASH_HR0 + HASH digest register + 0x310 + 0x20 + read-only + 0x00000000 + + + H0 + H0 + 0 + 32 + + + + + HASH_HR1 + HASH_HR1 + read-only + 0x314 + 0x20 + read-only + 0x00000000 + + + H1 + H1 + 0 + 32 + + + + + HASH_HR2 + HASH_HR2 + read-only + 0x318 + 0x20 + read-only + 0x00000000 + + + H2 + H2 + 0 + 32 + + + + + HASH_HR3 + HASH_HR3 + read-only + 0x31C + 0x20 + read-only + 0x00000000 + + + H3 + H3 + 0 + 32 + + + + + HASH_HR4 + HASH_HR4 + read-only + 0x320 + 0x20 + read-only + 0x00000000 + + + H4 + H4 + 0 + 32 + + + + + HASH_HR5 + HASH_HR5 + read-only + 0x324 + 0x20 + read-only + 0x00000000 + + + H5 + H5 + 0 + 32 + + + + + HASH_HR6 + HASH_HR6 + read-only + 0x328 + 0x20 + read-only + 0x00000000 + + + H6 + H6 + 0 + 32 + + + + + HASH_HR7 + HASH_HR7 + read-only + 0x32C + 0x20 + read-only + 0x00000000 + + + H7 + H7 + 0 + 32 + + + + + + + CRYP + Cryptographic processor + CRYP + 0x50060000 + + 0x0 + 0x400 + registers + + + CRYP + CRYP crypto global interrupt + 79 + + + + CR + CR + control register + 0x0 + 0x20 + 0x00000000 + + + ALGODIR + Algorithm direction + 2 + 1 + read-write + + + ALGOMODE0 + Algorithm mode + 3 + 3 + read-write + + + DATATYPE + Data type selection + 6 + 2 + read-write + + + KEYSIZE + Key size selection (AES mode + only) + 8 + 2 + read-write + + + FFLUSH + FIFO flush + 14 + 1 + write-only + + + CRYPEN + Cryptographic processor + enable + 15 + 1 + read-write + + + GCM_CCMPH + GCM_CCMPH + 16 + 2 + read-write + + + ALGOMODE3 + ALGOMODE + 19 + 1 + read-write + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000003 + + + BUSY + Busy bit + 4 + 1 + + + OFFU + Output FIFO full + 3 + 1 + + + OFNE + Output FIFO not empty + 2 + 1 + + + IFNF + Input FIFO not full + 1 + 1 + + + IFEM + Input FIFO empty + 0 + 1 + + + + + DIN + DIN + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + DATAIN + Data input + 0 + 32 + + + + + DOUT + DOUT + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + DATAOUT + Data output + 0 + 32 + + + + + DMACR + DMACR + DMA control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DOEN + DMA output enable + 1 + 1 + + + DIEN + DMA input enable + 0 + 1 + + + + + IMSCR + IMSCR + interrupt mask set/clear + register + 0x14 + 0x20 + read-write + 0x00000000 + + + OUTIM + Output FIFO service interrupt + mask + 1 + 1 + + + INIM + Input FIFO service interrupt + mask + 0 + 1 + + + + + RISR + RISR + raw interrupt status register + 0x18 + 0x20 + read-only + 0x00000001 + + + OUTRIS + Output FIFO service raw interrupt + status + 1 + 1 + + + INRIS + Input FIFO service raw interrupt + status + 0 + 1 + + + + + MISR + MISR + masked interrupt status + register + 0x1C + 0x20 + read-only + 0x00000000 + + + OUTMIS + Output FIFO service masked interrupt + status + 1 + 1 + + + INMIS + Input FIFO service masked interrupt + status + 0 + 1 + + + + + K0LR + K0LR + key registers + 0x20 + 0x20 + write-only + 0x00000000 + + + b224 + b224 + 0 + 1 + + + b225 + b225 + 1 + 1 + + + b226 + b226 + 2 + 1 + + + b227 + b227 + 3 + 1 + + + b228 + b228 + 4 + 1 + + + b229 + b229 + 5 + 1 + + + b230 + b230 + 6 + 1 + + + b231 + b231 + 7 + 1 + + + b232 + b232 + 8 + 1 + + + b233 + b233 + 9 + 1 + + + b234 + b234 + 10 + 1 + + + b235 + b235 + 11 + 1 + + + b236 + b236 + 12 + 1 + + + b237 + b237 + 13 + 1 + + + b238 + b238 + 14 + 1 + + + b239 + b239 + 15 + 1 + + + b240 + b240 + 16 + 1 + + + b241 + b241 + 17 + 1 + + + b242 + b242 + 18 + 1 + + + b243 + b243 + 19 + 1 + + + b244 + b244 + 20 + 1 + + + b245 + b245 + 21 + 1 + + + b246 + b246 + 22 + 1 + + + b247 + b247 + 23 + 1 + + + b248 + b248 + 24 + 1 + + + b249 + b249 + 25 + 1 + + + b250 + b250 + 26 + 1 + + + b251 + b251 + 27 + 1 + + + b252 + b252 + 28 + 1 + + + b253 + b253 + 29 + 1 + + + b254 + b254 + 30 + 1 + + + b255 + b255 + 31 + 1 + + + + + K0RR + K0RR + key registers + 0x24 + 0x20 + write-only + 0x00000000 + + + b192 + b192 + 0 + 1 + + + b193 + b193 + 1 + 1 + + + b194 + b194 + 2 + 1 + + + b195 + b195 + 3 + 1 + + + b196 + b196 + 4 + 1 + + + b197 + b197 + 5 + 1 + + + b198 + b198 + 6 + 1 + + + b199 + b199 + 7 + 1 + + + b200 + b200 + 8 + 1 + + + b201 + b201 + 9 + 1 + + + b202 + b202 + 10 + 1 + + + b203 + b203 + 11 + 1 + + + b204 + b204 + 12 + 1 + + + b205 + b205 + 13 + 1 + + + b206 + b206 + 14 + 1 + + + b207 + b207 + 15 + 1 + + + b208 + b208 + 16 + 1 + + + b209 + b209 + 17 + 1 + + + b210 + b210 + 18 + 1 + + + b211 + b211 + 19 + 1 + + + b212 + b212 + 20 + 1 + + + b213 + b213 + 21 + 1 + + + b214 + b214 + 22 + 1 + + + b215 + b215 + 23 + 1 + + + b216 + b216 + 24 + 1 + + + b217 + b217 + 25 + 1 + + + b218 + b218 + 26 + 1 + + + b219 + b219 + 27 + 1 + + + b220 + b220 + 28 + 1 + + + b221 + b221 + 29 + 1 + + + b222 + b222 + 30 + 1 + + + b223 + b223 + 31 + 1 + + + + + K1LR + K1LR + key registers + 0x28 + 0x20 + write-only + 0x00000000 + + + b160 + b160 + 0 + 1 + + + b161 + b161 + 1 + 1 + + + b162 + b162 + 2 + 1 + + + b163 + b163 + 3 + 1 + + + b164 + b164 + 4 + 1 + + + b165 + b165 + 5 + 1 + + + b166 + b166 + 6 + 1 + + + b167 + b167 + 7 + 1 + + + b168 + b168 + 8 + 1 + + + b169 + b169 + 9 + 1 + + + b170 + b170 + 10 + 1 + + + b171 + b171 + 11 + 1 + + + b172 + b172 + 12 + 1 + + + b173 + b173 + 13 + 1 + + + b174 + b174 + 14 + 1 + + + b175 + b175 + 15 + 1 + + + b176 + b176 + 16 + 1 + + + b177 + b177 + 17 + 1 + + + b178 + b178 + 18 + 1 + + + b179 + b179 + 19 + 1 + + + b180 + b180 + 20 + 1 + + + b181 + b181 + 21 + 1 + + + b182 + b182 + 22 + 1 + + + b183 + b183 + 23 + 1 + + + b184 + b184 + 24 + 1 + + + b185 + b185 + 25 + 1 + + + b186 + b186 + 26 + 1 + + + b187 + b187 + 27 + 1 + + + b188 + b188 + 28 + 1 + + + b189 + b189 + 29 + 1 + + + b190 + b190 + 30 + 1 + + + b191 + b191 + 31 + 1 + + + + + K1RR + K1RR + key registers + 0x2C + 0x20 + write-only + 0x00000000 + + + b128 + b128 + 0 + 1 + + + b129 + b129 + 1 + 1 + + + b130 + b130 + 2 + 1 + + + b131 + b131 + 3 + 1 + + + b132 + b132 + 4 + 1 + + + b133 + b133 + 5 + 1 + + + b134 + b134 + 6 + 1 + + + b135 + b135 + 7 + 1 + + + b136 + b136 + 8 + 1 + + + b137 + b137 + 9 + 1 + + + b138 + b138 + 10 + 1 + + + b139 + b139 + 11 + 1 + + + b140 + b140 + 12 + 1 + + + b141 + b141 + 13 + 1 + + + b142 + b142 + 14 + 1 + + + b143 + b143 + 15 + 1 + + + b144 + b144 + 16 + 1 + + + b145 + b145 + 17 + 1 + + + b146 + b146 + 18 + 1 + + + b147 + b147 + 19 + 1 + + + b148 + b148 + 20 + 1 + + + b149 + b149 + 21 + 1 + + + b150 + b150 + 22 + 1 + + + b151 + b151 + 23 + 1 + + + b152 + b152 + 24 + 1 + + + b153 + b153 + 25 + 1 + + + b154 + b154 + 26 + 1 + + + b155 + b155 + 27 + 1 + + + b156 + b156 + 28 + 1 + + + b157 + b157 + 29 + 1 + + + b158 + b158 + 30 + 1 + + + b159 + b159 + 31 + 1 + + + + + K2LR + K2LR + key registers + 0x30 + 0x20 + write-only + 0x00000000 + + + b96 + b96 + 0 + 1 + + + b97 + b97 + 1 + 1 + + + b98 + b98 + 2 + 1 + + + b99 + b99 + 3 + 1 + + + b100 + b100 + 4 + 1 + + + b101 + b101 + 5 + 1 + + + b102 + b102 + 6 + 1 + + + b103 + b103 + 7 + 1 + + + b104 + b104 + 8 + 1 + + + b105 + b105 + 9 + 1 + + + b106 + b106 + 10 + 1 + + + b107 + b107 + 11 + 1 + + + b108 + b108 + 12 + 1 + + + b109 + b109 + 13 + 1 + + + b110 + b110 + 14 + 1 + + + b111 + b111 + 15 + 1 + + + b112 + b112 + 16 + 1 + + + b113 + b113 + 17 + 1 + + + b114 + b114 + 18 + 1 + + + b115 + b115 + 19 + 1 + + + b116 + b116 + 20 + 1 + + + b117 + b117 + 21 + 1 + + + b118 + b118 + 22 + 1 + + + b119 + b119 + 23 + 1 + + + b120 + b120 + 24 + 1 + + + b121 + b121 + 25 + 1 + + + b122 + b122 + 26 + 1 + + + b123 + b123 + 27 + 1 + + + b124 + b124 + 28 + 1 + + + b125 + b125 + 29 + 1 + + + b126 + b126 + 30 + 1 + + + b127 + b127 + 31 + 1 + + + + + K2RR + K2RR + key registers + 0x34 + 0x20 + write-only + 0x00000000 + + + b64 + b64 + 0 + 1 + + + b65 + b65 + 1 + 1 + + + b66 + b66 + 2 + 1 + + + b67 + b67 + 3 + 1 + + + b68 + b68 + 4 + 1 + + + b69 + b69 + 5 + 1 + + + b70 + b70 + 6 + 1 + + + b71 + b71 + 7 + 1 + + + b72 + b72 + 8 + 1 + + + b73 + b73 + 9 + 1 + + + b74 + b74 + 10 + 1 + + + b75 + b75 + 11 + 1 + + + b76 + b76 + 12 + 1 + + + b77 + b77 + 13 + 1 + + + b78 + b78 + 14 + 1 + + + b79 + b79 + 15 + 1 + + + b80 + b80 + 16 + 1 + + + b81 + b81 + 17 + 1 + + + b82 + b82 + 18 + 1 + + + b83 + b83 + 19 + 1 + + + b84 + b84 + 20 + 1 + + + b85 + b85 + 21 + 1 + + + b86 + b86 + 22 + 1 + + + b87 + b87 + 23 + 1 + + + b88 + b88 + 24 + 1 + + + b89 + b89 + 25 + 1 + + + b90 + b90 + 26 + 1 + + + b91 + b91 + 27 + 1 + + + b92 + b92 + 28 + 1 + + + b93 + b93 + 29 + 1 + + + b94 + b94 + 30 + 1 + + + b95 + b95 + 31 + 1 + + + + + K3LR + K3LR + key registers + 0x38 + 0x20 + write-only + 0x00000000 + + + b32 + b32 + 0 + 1 + + + b33 + b33 + 1 + 1 + + + b34 + b34 + 2 + 1 + + + b35 + b35 + 3 + 1 + + + b36 + b36 + 4 + 1 + + + b37 + b37 + 5 + 1 + + + b38 + b38 + 6 + 1 + + + b39 + b39 + 7 + 1 + + + b40 + b40 + 8 + 1 + + + b41 + b41 + 9 + 1 + + + b42 + b42 + 10 + 1 + + + b43 + b43 + 11 + 1 + + + b44 + b44 + 12 + 1 + + + b45 + b45 + 13 + 1 + + + b46 + b46 + 14 + 1 + + + b47 + b47 + 15 + 1 + + + b48 + b48 + 16 + 1 + + + b49 + b49 + 17 + 1 + + + b50 + b50 + 18 + 1 + + + b51 + b51 + 19 + 1 + + + b52 + b52 + 20 + 1 + + + b53 + b53 + 21 + 1 + + + b54 + b54 + 22 + 1 + + + b55 + b55 + 23 + 1 + + + b56 + b56 + 24 + 1 + + + b57 + b57 + 25 + 1 + + + b58 + b58 + 26 + 1 + + + b59 + b59 + 27 + 1 + + + b60 + b60 + 28 + 1 + + + b61 + b61 + 29 + 1 + + + b62 + b62 + 30 + 1 + + + b63 + b63 + 31 + 1 + + + + + K3RR + K3RR + key registers + 0x3C + 0x20 + write-only + 0x00000000 + + + b0 + b0 + 0 + 1 + + + b1 + b1 + 1 + 1 + + + b2 + b2 + 2 + 1 + + + b3 + b3 + 3 + 1 + + + b4 + b4 + 4 + 1 + + + b5 + b5 + 5 + 1 + + + b6 + b6 + 6 + 1 + + + b7 + b7 + 7 + 1 + + + b8 + b8 + 8 + 1 + + + b9 + b9 + 9 + 1 + + + b10 + b10 + 10 + 1 + + + b11 + b11 + 11 + 1 + + + b12 + b12 + 12 + 1 + + + b13 + b13 + 13 + 1 + + + b14 + b14 + 14 + 1 + + + b15 + b15 + 15 + 1 + + + b16 + b16 + 16 + 1 + + + b17 + b17 + 17 + 1 + + + b18 + b18 + 18 + 1 + + + b19 + b19 + 19 + 1 + + + b20 + b20 + 20 + 1 + + + b21 + b21 + 21 + 1 + + + b22 + b22 + 22 + 1 + + + b23 + b23 + 23 + 1 + + + b24 + b24 + 24 + 1 + + + b25 + b25 + 25 + 1 + + + b26 + b26 + 26 + 1 + + + b27 + b27 + 27 + 1 + + + b28 + b28 + 28 + 1 + + + b29 + b29 + 29 + 1 + + + b30 + b30 + 30 + 1 + + + b31 + b31 + 31 + 1 + + + + + IV0LR + IV0LR + initialization vector + registers + 0x40 + 0x20 + read-write + 0x00000000 + + + IV31 + IV31 + 0 + 1 + + + IV30 + IV30 + 1 + 1 + + + IV29 + IV29 + 2 + 1 + + + IV28 + IV28 + 3 + 1 + + + IV27 + IV27 + 4 + 1 + + + IV26 + IV26 + 5 + 1 + + + IV25 + IV25 + 6 + 1 + + + IV24 + IV24 + 7 + 1 + + + IV23 + IV23 + 8 + 1 + + + IV22 + IV22 + 9 + 1 + + + IV21 + IV21 + 10 + 1 + + + IV20 + IV20 + 11 + 1 + + + IV19 + IV19 + 12 + 1 + + + IV18 + IV18 + 13 + 1 + + + IV17 + IV17 + 14 + 1 + + + IV16 + IV16 + 15 + 1 + + + IV15 + IV15 + 16 + 1 + + + IV14 + IV14 + 17 + 1 + + + IV13 + IV13 + 18 + 1 + + + IV12 + IV12 + 19 + 1 + + + IV11 + IV11 + 20 + 1 + + + IV10 + IV10 + 21 + 1 + + + IV9 + IV9 + 22 + 1 + + + IV8 + IV8 + 23 + 1 + + + IV7 + IV7 + 24 + 1 + + + IV6 + IV6 + 25 + 1 + + + IV5 + IV5 + 26 + 1 + + + IV4 + IV4 + 27 + 1 + + + IV3 + IV3 + 28 + 1 + + + IV2 + IV2 + 29 + 1 + + + IV1 + IV1 + 30 + 1 + + + IV0 + IV0 + 31 + 1 + + + + + IV0RR + IV0RR + initialization vector + registers + 0x44 + 0x20 + read-write + 0x00000000 + + + IV63 + IV63 + 0 + 1 + + + IV62 + IV62 + 1 + 1 + + + IV61 + IV61 + 2 + 1 + + + IV60 + IV60 + 3 + 1 + + + IV59 + IV59 + 4 + 1 + + + IV58 + IV58 + 5 + 1 + + + IV57 + IV57 + 6 + 1 + + + IV56 + IV56 + 7 + 1 + + + IV55 + IV55 + 8 + 1 + + + IV54 + IV54 + 9 + 1 + + + IV53 + IV53 + 10 + 1 + + + IV52 + IV52 + 11 + 1 + + + IV51 + IV51 + 12 + 1 + + + IV50 + IV50 + 13 + 1 + + + IV49 + IV49 + 14 + 1 + + + IV48 + IV48 + 15 + 1 + + + IV47 + IV47 + 16 + 1 + + + IV46 + IV46 + 17 + 1 + + + IV45 + IV45 + 18 + 1 + + + IV44 + IV44 + 19 + 1 + + + IV43 + IV43 + 20 + 1 + + + IV42 + IV42 + 21 + 1 + + + IV41 + IV41 + 22 + 1 + + + IV40 + IV40 + 23 + 1 + + + IV39 + IV39 + 24 + 1 + + + IV38 + IV38 + 25 + 1 + + + IV37 + IV37 + 26 + 1 + + + IV36 + IV36 + 27 + 1 + + + IV35 + IV35 + 28 + 1 + + + IV34 + IV34 + 29 + 1 + + + IV33 + IV33 + 30 + 1 + + + IV32 + IV32 + 31 + 1 + + + + + IV1LR + IV1LR + initialization vector + registers + 0x48 + 0x20 + read-write + 0x00000000 + + + IV95 + IV95 + 0 + 1 + + + IV94 + IV94 + 1 + 1 + + + IV93 + IV93 + 2 + 1 + + + IV92 + IV92 + 3 + 1 + + + IV91 + IV91 + 4 + 1 + + + IV90 + IV90 + 5 + 1 + + + IV89 + IV89 + 6 + 1 + + + IV88 + IV88 + 7 + 1 + + + IV87 + IV87 + 8 + 1 + + + IV86 + IV86 + 9 + 1 + + + IV85 + IV85 + 10 + 1 + + + IV84 + IV84 + 11 + 1 + + + IV83 + IV83 + 12 + 1 + + + IV82 + IV82 + 13 + 1 + + + IV81 + IV81 + 14 + 1 + + + IV80 + IV80 + 15 + 1 + + + IV79 + IV79 + 16 + 1 + + + IV78 + IV78 + 17 + 1 + + + IV77 + IV77 + 18 + 1 + + + IV76 + IV76 + 19 + 1 + + + IV75 + IV75 + 20 + 1 + + + IV74 + IV74 + 21 + 1 + + + IV73 + IV73 + 22 + 1 + + + IV72 + IV72 + 23 + 1 + + + IV71 + IV71 + 24 + 1 + + + IV70 + IV70 + 25 + 1 + + + IV69 + IV69 + 26 + 1 + + + IV68 + IV68 + 27 + 1 + + + IV67 + IV67 + 28 + 1 + + + IV66 + IV66 + 29 + 1 + + + IV65 + IV65 + 30 + 1 + + + IV64 + IV64 + 31 + 1 + + + + + IV1RR + IV1RR + initialization vector + registers + 0x4C + 0x20 + read-write + 0x00000000 + + + IV127 + IV127 + 0 + 1 + + + IV126 + IV126 + 1 + 1 + + + IV125 + IV125 + 2 + 1 + + + IV124 + IV124 + 3 + 1 + + + IV123 + IV123 + 4 + 1 + + + IV122 + IV122 + 5 + 1 + + + IV121 + IV121 + 6 + 1 + + + IV120 + IV120 + 7 + 1 + + + IV119 + IV119 + 8 + 1 + + + IV118 + IV118 + 9 + 1 + + + IV117 + IV117 + 10 + 1 + + + IV116 + IV116 + 11 + 1 + + + IV115 + IV115 + 12 + 1 + + + IV114 + IV114 + 13 + 1 + + + IV113 + IV113 + 14 + 1 + + + IV112 + IV112 + 15 + 1 + + + IV111 + IV111 + 16 + 1 + + + IV110 + IV110 + 17 + 1 + + + IV109 + IV109 + 18 + 1 + + + IV108 + IV108 + 19 + 1 + + + IV107 + IV107 + 20 + 1 + + + IV106 + IV106 + 21 + 1 + + + IV105 + IV105 + 22 + 1 + + + IV104 + IV104 + 23 + 1 + + + IV103 + IV103 + 24 + 1 + + + IV102 + IV102 + 25 + 1 + + + IV101 + IV101 + 26 + 1 + + + IV100 + IV100 + 27 + 1 + + + IV99 + IV99 + 28 + 1 + + + IV98 + IV98 + 29 + 1 + + + IV97 + IV97 + 30 + 1 + + + IV96 + IV96 + 31 + 1 + + + + + CSGCMCCM0R + CSGCMCCM0R + context swap register + 0x50 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM0R + CSGCMCCM0R + 0 + 32 + + + + + CSGCMCCM1R + CSGCMCCM1R + context swap register + 0x54 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM1R + CSGCMCCM1R + 0 + 32 + + + + + CSGCMCCM2R + CSGCMCCM2R + context swap register + 0x58 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM2R + CSGCMCCM2R + 0 + 32 + + + + + CSGCMCCM3R + CSGCMCCM3R + context swap register + 0x5C + 0x20 + read-write + 0x00000000 + + + CSGCMCCM3R + CSGCMCCM3R + 0 + 32 + + + + + CSGCMCCM4R + CSGCMCCM4R + context swap register + 0x60 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM4R + CSGCMCCM4R + 0 + 32 + + + + + CSGCMCCM5R + CSGCMCCM5R + context swap register + 0x64 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM5R + CSGCMCCM5R + 0 + 32 + + + + + CSGCMCCM6R + CSGCMCCM6R + context swap register + 0x68 + 0x20 + read-write + 0x00000000 + + + CSGCMCCM6R + CSGCMCCM6R + 0 + 32 + + + + + CSGCMCCM7R + CSGCMCCM7R + context swap register + 0x6C + 0x20 + read-write + 0x00000000 + + + CSGCMCCM7R + CSGCMCCM7R + 0 + 32 + + + + + CSGCM0R + CSGCM0R + context swap register + 0x70 + 0x20 + read-write + 0x00000000 + + + CSGCM0R + CSGCM0R + 0 + 32 + + + + + CSGCM1R + CSGCM1R + context swap register + 0x74 + 0x20 + read-write + 0x00000000 + + + CSGCM1R + CSGCM1R + 0 + 32 + + + + + CSGCM2R + CSGCM2R + context swap register + 0x78 + 0x20 + read-write + 0x00000000 + + + CSGCM2R + CSGCM2R + 0 + 32 + + + + + CSGCM3R + CSGCM3R + context swap register + 0x7C + 0x20 + read-write + 0x00000000 + + + CSGCM3R + CSGCM3R + 0 + 32 + + + + + CSGCM4R + CSGCM4R + context swap register + 0x80 + 0x20 + read-write + 0x00000000 + + + CSGCM4R + CSGCM4R + 0 + 32 + + + + + CSGCM5R + CSGCM5R + context swap register + 0x84 + 0x20 + read-write + 0x00000000 + + + CSGCM5R + CSGCM5R + 0 + 32 + + + + + CSGCM6R + CSGCM6R + context swap register + 0x88 + 0x20 + read-write + 0x00000000 + + + CSGCM6R + CSGCM6R + 0 + 32 + + + + + CSGCM7R + CSGCM7R + context swap register + 0x8C + 0x20 + read-write + 0x00000000 + + + CSGCM7R + CSGCM7R + 0 + 32 + + + + + + + diff --git a/neo/ui-stm32/build.rs b/neo/ui-stm32/build.rs new file mode 100644 index 0000000..ce79dd7 --- /dev/null +++ b/neo/ui-stm32/build.rs @@ -0,0 +1,20 @@ +use std::env; +use std::path::PathBuf; + +fn main() { + println!("cargo::rerun-if-changed=STM32F405.svd"); + + let bindings = svdgen::Builder::default() + .svd_file("STM32F405.svd") + .include("RCC") + .include("FLASH") + .include("GPIOA") + .include("GPIOC") + .build() + .expect("Unable to parse SVD file"); + + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap()); + bindings + .write_to_file(out_path.join("stm32f405.rs")) + .expect("Unable to translate SVD file"); +} diff --git a/neo/ui-stm32/src/board/button.rs b/neo/ui-stm32/src/board/button.rs new file mode 100644 index 0000000..7af2f93 --- /dev/null +++ b/neo/ui-stm32/src/board/button.rs @@ -0,0 +1,30 @@ +use crate::hal::gpio; + +pub struct Button

{ + pin: gpio::Input

, + last_state: bool, +} + +impl

Default for Button

+where + P: gpio::Fields, +{ + fn default() -> Self { + let pin = P::input(); + pin.pull_up(); + let last_state = pin.read(); + Self { pin, last_state } + } +} + +impl

Button

+where + P: gpio::Fields, +{ + pub fn read(&mut self) -> (bool, bool) { + let curr_state = self.pin.read(); + let changed = curr_state == self.last_state; + self.last_state = curr_state; + (curr_state, changed) + } +} diff --git a/neo/ui-stm32/src/board/led.rs b/neo/ui-stm32/src/board/led.rs new file mode 100644 index 0000000..4c9cdb8 --- /dev/null +++ b/neo/ui-stm32/src/board/led.rs @@ -0,0 +1,67 @@ +use crate::hal::gpio; + +#[derive(Copy, Clone)] +pub enum Color { + Black, + White, + Red, + Green, + Blue, + Teal, + Yellow, + Purple, +} + +impl Color { + fn rgb(&self) -> (bool, bool, bool) { + match self { + Self::Black => (false, false, false), + Self::Red => (true, false, false), + Self::Green => (false, true, false), + Self::Blue => (false, false, true), + Self::Teal => (false, true, true), + Self::Purple => (true, false, true), + Self::Yellow => (true, true, false), + Self::White => (true, true, true), + } + } +} + +pub struct Led { + r: gpio::Output, + g: gpio::Output, + b: gpio::Output, +} + +impl Default for Led +where + R: gpio::Fields, + G: gpio::Fields, + B: gpio::Fields, +{ + fn default() -> Self { + let r = R::output(); + let g = G::output(); + let b = B::output(); + + r.set_low(); + g.set_low(); + b.set_low(); + + Self { r, g, b } + } +} + +impl Led +where + R: gpio::Fields, + G: gpio::Fields, + B: gpio::Fields, +{ + fn set(&self, c: Color) { + let (r, g, b) = c.rgb(); + self.r.set(r); + self.g.set(g); + self.b.set(b); + } +} diff --git a/neo/ui-stm32/src/board/mod.rs b/neo/ui-stm32/src/board/mod.rs new file mode 100644 index 0000000..b1e014f --- /dev/null +++ b/neo/ui-stm32/src/board/mod.rs @@ -0,0 +1,18 @@ +mod button; +mod led; + +use crate::hal::gpio::{gpioa, gpioc}; +use button::Button; +use led::Led; + +type RedLedPin = gpioa::PA6; +type GreenLedPin = gpioc::PC5; +type BlueLedPin = gpioa::PA1; +type PttButtonPin = gpioc::PC0; +type AiButtonPin = gpioc::PC1; + +pub struct Board { + status_led: Led, + ptt_button: Button, + ai_button: Button, +} diff --git a/neo/ui-stm32/src/hal/clock.rs b/neo/ui-stm32/src/hal/clock.rs new file mode 100644 index 0000000..159e615 --- /dev/null +++ b/neo/ui-stm32/src/hal/clock.rs @@ -0,0 +1,160 @@ +//! # Clock Module +//! +//! This module provides functions to initialize and validate the clock configuration for the system. +//! It handles setting up the PLL (Phase-Locked Loop), external clock, and various clock dividers. +//! +//! ## Functions +//! +//! - `init`: Initializes the clock configuration based on the board-specific settings. +//! - `validate`: Validates the clock configuration to ensure it is set up correctly. +//! +//! ## Usage +//! +//! The `init` function should be called during system startup to configure the clock. The `validate` function +//! can be used to check if the clock configuration is correct. +//! + +use crate::svd::{Read, Write, FLASH, RCC}; + +fn write_pll_m(pll_m: u8) { + assert!(pll_m < (1 << 6)); + RCC::PLLCFGR::PLLM5::write((pll_m >> 5) & 0x1 == 1); + RCC::PLLCFGR::PLLM4::write((pll_m >> 4) & 0x1 == 1); + RCC::PLLCFGR::PLLM3::write((pll_m >> 3) & 0x1 == 1); + RCC::PLLCFGR::PLLM2::write((pll_m >> 2) & 0x1 == 1); + RCC::PLLCFGR::PLLM1::write((pll_m >> 1) & 0x1 == 1); + RCC::PLLCFGR::PLLM0::write((pll_m >> 0) & 0x1 == 1); +} + +fn write_pll_n(pll_n: u8) { + RCC::PLLCFGR::PLLN7::write((pll_n >> 7) & 0x1 == 1); + RCC::PLLCFGR::PLLN6::write((pll_n >> 6) & 0x1 == 1); + RCC::PLLCFGR::PLLN5::write((pll_n >> 5) & 0x1 == 1); + RCC::PLLCFGR::PLLN4::write((pll_n >> 4) & 0x1 == 1); + RCC::PLLCFGR::PLLN3::write((pll_n >> 3) & 0x1 == 1); + RCC::PLLCFGR::PLLN2::write((pll_n >> 2) & 0x1 == 1); + RCC::PLLCFGR::PLLN1::write((pll_n >> 1) & 0x1 == 1); + RCC::PLLCFGR::PLLN0::write((pll_n >> 0) & 0x1 == 1); +} + +fn write_pll_p(pll_p: u8) { + assert!(pll_p < (1 << 2)); + RCC::PLLCFGR::PLLP1::write((pll_p >> 1) & 0x1 == 1); + RCC::PLLCFGR::PLLP0::write((pll_p >> 0) & 0x1 == 1); +} + +fn write_pll_q(pll_q: u8) { + assert!(pll_q < (1 << 4)); + RCC::PLLCFGR::PLLQ3::write((pll_q >> 3) & 0x1 == 1); + RCC::PLLCFGR::PLLQ2::write((pll_q >> 2) & 0x1 == 1); + RCC::PLLCFGR::PLLQ1::write((pll_q >> 1) & 0x1 == 1); + RCC::PLLCFGR::PLLQ0::write((pll_q >> 0) & 0x1 == 1); +} + +fn read_pll_n() -> u8 { + (u8::from(RCC::PLLCFGR::PLLN7::read()) << 7) + | (u8::from(RCC::PLLCFGR::PLLN6::read()) << 6) + | (u8::from(RCC::PLLCFGR::PLLN5::read()) << 5) + | (u8::from(RCC::PLLCFGR::PLLN4::read()) << 4) + | (u8::from(RCC::PLLCFGR::PLLN3::read()) << 3) + | (u8::from(RCC::PLLCFGR::PLLN2::read()) << 2) + | (u8::from(RCC::PLLCFGR::PLLN1::read()) << 1) + | (u8::from(RCC::PLLCFGR::PLLN0::read()) << 0) +} + +fn read_pll_p() -> u8 { + (u8::from(RCC::PLLCFGR::PLLP1::read()) << 1) | (u8::from(RCC::PLLCFGR::PLLP0::read()) << 0) +} + +fn read_pll_q() -> u8 { + (u8::from(RCC::PLLCFGR::PLLQ3::read()) << 3) + | (u8::from(RCC::PLLCFGR::PLLQ2::read()) << 2) + | (u8::from(RCC::PLLCFGR::PLLQ1::read()) << 1) + | (u8::from(RCC::PLLCFGR::PLLQ0::read()) << 0) +} + +/// Initializes the clock configuration based on the board-specific settings. +pub fn init(hse_clk_freq: u32) { + let pll_m = match hse_clk_freq { + 16_000_000 => 8, + 24_000_000 => 12, + _ => unreachable!("Invalid HSE clock frequency {hse_clk_freq}"), + }; + + // Setup flash wait states and cache + // XXX(fluffy): If voltage is changed, need to change this + FLASH::ACR::LATENCY::write(5); + FLASH::ACR::PRFTEN::write(true); + FLASH::ACR::ICEN::write(true); + FLASH::ACR::DCEN::write(true); + + // Enable HSE + RCC::CR::HSEON::write(true); + while !RCC::CR::HSERDY::read() {} + + // Set up main PLL timing for external HSE + const PLL_N: u8 = 168; + const PLL_P: u8 = 2; + const PLL_Q: u8 = 4; + write_pll_m(pll_m); + write_pll_n(PLL_N); + write_pll_p(PLL_P); + write_pll_q(PLL_Q); + + // Select HSE + RCC::PLLCFGR::PLLSRC::write(true); + + // Enable PLL + RCC::CR::PLLON::write(true); + while !RCC::CR::PLLRDY::read() {} + + // Set up clock usage and dividers + RCC::CFGR::HPRE::write(0b0000); // sys clock div = 1 + RCC::CFGR::PPRE1::write(0b101); // APB1 clock div = 4 + RCC::CFGR::PPRE2::write(0b100); // APB2 clock div = 2 + + // Switch clock to PLL + RCC::CFGR::SW1::write(true); + RCC::CFGR::SW0::write(true); + while !RCC::CFGR::SWS1::read() || RCC::CFGR::SWS0::read() {} +} + +/// Validates the clock configuration to ensure it is set up correctly. +pub fn validate() { + // Check if HSE is ready + assert!(RCC::CR::HSERDY::read(), "HSE not ready"); + + // Check if PLL is ready + assert!(RCC::CR::PLLRDY::read(), "PLL not ready"); + + // Check if PLL source is HSE + assert!(RCC::PLLCFGR::PLLSRC::read(), "PLL source is not HSE"); + + // Check if the PLL parameters are set correctly + assert_eq!(read_pll_n(), 168, "PLL N not set to 168"); + assert_eq!(read_pll_p(), 2, "PLL P not set to 2"); + assert_eq!(read_pll_q(), 4, "PLL Q not set to 4"); + + // Check if system clock mux is set to PLL + assert!( + RCC::CFGR::SWS1::read() && !RCC::CFGR::SWS0::read(), + "System clock not set to PLL" + ); + + // Check AHB prescaler + assert_eq!( + RCC::CFGR::HPRE::read(), + 0b0000, + "AHB prescaler not set to 1" + ); + assert_eq!( + RCC::CFGR::PPRE1::read(), + 0b101, + "APB1 prescaler not set to 4" + ); + assert_eq!( + RCC::CFGR::PPRE2::read(), + 0b100, + "APB2 prescaler not set to 2" + ); +} diff --git a/neo/ui-stm32/src/hal/gpio.rs b/neo/ui-stm32/src/hal/gpio.rs new file mode 100644 index 0000000..02172d2 --- /dev/null +++ b/neo/ui-stm32/src/hal/gpio.rs @@ -0,0 +1,197 @@ +//! # GPIO Module +//! +//! This module provides functionality for initializing and controlling +//! General-Purpose Input/Output (GPIO) pins. +//! It includes methods for setting pins as input or output, configuring +//! pull-up or pull-down resistors, and reading or writing pin states. +//! +//! ## Structures +//! +//! - `Pin`: Represents a GPIO pin and provides methods to configure and control it. +//! +//! ## Functions +//! +//! - `init`: Initializes the GPIO peripheral by enabling the necessary clocks. +//! +//! ## Methods for `Pin` +//! +//! - `new`: Creates a new `Pin` instance. +//! - `output`: Configures the pin as an output. +//! - `input`: Configures the pin as an input with a pull-down resistor. +//! - `pulldown`: Configures the pin with a pull-down resistor. +//! - `pullup`: Configures the pin with a pull-up resistor. +//! - `low`: Sets the pin state to low. +//! - `high`: Sets the pin state to high. +//! - `read`: Reads the current state of the pin. +//! +//! ## Usage +//! +//! This module is intended for low-level hardware interaction and should be used with caution. +//! It provides direct access to hardware registers, +//! which can lead to undefined behavior if used incorrectly. +//! +//! ## Example +//! +//! ``` rust +//! use crate::hal::gpio::{self, Pin}; +//! use crate::hal::cpu; +//! use crate::hal::clock; +//! +//! fn main() { +//! cpu::init(); +//! clock::init( 16_000_000 ); +//! gpio::init(); +//! +//! let pin = gpio::gpioa::PA5::output(); +//! pin.set_high(); +//! +//! let pin = gpio::gpioa::PA4::input(); +//! println!("Pin state: {}", pin.read()); +//! } +//! ``` +#![allow(non_camel_case_types)] + +use crate::svd::{Read, Write, RCC}; + +pub fn init() { + RCC::AHB1ENR::GPIOAEN::write(true); +} + +pub trait Fields: Sized { + type IDR: Read; + type MODER: Write; + type ODR: Write; + type OTYPER: Write; + type PUPDR: Write; + type OSPEEDR: Write; + type BR: Write; + type BS: Write; + + fn output() -> Output { + Self::MODER::write(0b01); // mode = output + Self::ODR::write(false); // output = low + Self::OTYPER::write(false); // push-pull + Self::PUPDR::write(0b00); // no pull down or pull up + Self::OSPEEDR::write(0b00); // speed = slow + + Output::new() + } + + fn input() -> Input { + Self::MODER::write(0b00); // mode = input + Self::PUPDR::write(0b10); // pull down + + Input::new() + } +} + +pub struct Output { + _phantom: core::marker::PhantomData, +} + +impl Output +where + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } + + pub fn set(&self, high: bool) { + if high { + self.set_high() + } else { + self.set_low() + } + } + + pub fn set_low(&self) { + F::BR::write(true); + } + + pub fn set_high(&self) { + F::BS::write(true); + } +} + +pub struct Input { + _phantom: core::marker::PhantomData, +} + +impl Input +where + F: Fields, +{ + pub fn new() -> Self { + Self { + _phantom: core::marker::PhantomData, + } + } + + pub fn pull_up(&self) { + F::PUPDR::write(0b10); + } + + pub fn pull_down(&self) { + F::PUPDR::write(0b01); + } + + pub fn read(&self) -> bool { + F::IDR::read() + } +} + +use paste::paste; + +macro_rules! pin { + ($name:expr, $pin:literal) => { + paste! { + pub struct [

]; + + impl Fields for [

] { + type MODER = []::MODER::[]; + type OTYPER = []::OTYPER::[]; + type OSPEEDR = []::OSPEEDR::[]; + type PUPDR = []::PUPDR::[]; + type IDR = []::IDR::[]; + type ODR = []::ODR::[]; + type BR = []::BSRR::[
]; + type BS = []::BSRR::[]; + } + } + }; +} + +macro_rules! bus { + ($name:expr) => { + paste! { + pub mod [] { + use paste::paste; + use super::Fields; + use crate::svd::[]; + + pin! { $name, 0 } + pin! { $name, 1 } + pin! { $name, 2 } + pin! { $name, 3 } + pin! { $name, 4 } + pin! { $name, 5 } + pin! { $name, 6 } + pin! { $name, 7 } + pin! { $name, 8 } + pin! { $name, 9 } + pin! { $name, 10 } + pin! { $name, 11 } + pin! { $name, 12 } + pin! { $name, 13 } + pin! { $name, 14 } + pin! { $name, 15 } + } + } + }; +} + +bus! { A } +bus! { C } diff --git a/neo/ui-stm32/src/hal/mod.rs b/neo/ui-stm32/src/hal/mod.rs new file mode 100644 index 0000000..99a4797 --- /dev/null +++ b/neo/ui-stm32/src/hal/mod.rs @@ -0,0 +1,2 @@ +pub mod clock; +pub mod gpio; diff --git a/neo/ui-stm32/src/main.rs b/neo/ui-stm32/src/main.rs new file mode 100644 index 0000000..93ec495 --- /dev/null +++ b/neo/ui-stm32/src/main.rs @@ -0,0 +1,7 @@ +#![allow(dead_code)] // TODO(RLB) Remove once things are more complete + +mod board; +mod hal; +mod svd; + +fn main() {} diff --git a/neo/ui-stm32/src/svd.rs b/neo/ui-stm32/src/svd.rs new file mode 100644 index 0000000..d97d116 --- /dev/null +++ b/neo/ui-stm32/src/svd.rs @@ -0,0 +1,7 @@ +#![allow(dead_code)] +#![allow(non_snake_case)] +#![allow(non_camel_case_types)] +#![allow(clippy::identity_op)] +#![allow(unused_imports)] + +include!(concat!(env!("OUT_DIR"), "/stm32f405.rs"));