diff --git a/.gitmodules b/.gitmodules
index 492129f..f288192 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,42 +1,45 @@
 [submodule "FPGA/cores/aes"]
 	path = FPGA/cores/aes
-	url = ../aes.git
+	url = ../../Netnod/aes.git
 [submodule "FPGA/cores/aes-siv"]
 	path = FPGA/cores/aes-siv
-	url = ../aes-siv.git
+	url = ../../Netnod/aes-siv.git
 [submodule "FPGA/cores/cmac"]
 	path = FPGA/cores/cmac
-	url = ../cmac.git
+	url = ../../Netnod/cmac.git
 [submodule "FPGA/cores/md5"]
 	path = FPGA/cores/md5
-	url = ../md5.git
+	url = ../../Netnod/md5.git
 [submodule "FPGA/cores/sha1"]
 	path = FPGA/cores/sha1
-	url = ../sha1.git
+	url = ../../Netnod/sha1.git
 [submodule "FPGA/cores/siphash"]
 	path = FPGA/cores/siphash
-	url = ../siphash.git
+	url = ../../Netnod/siphash.git
 [submodule "FPGA/cores/api_extension"]
 	path = FPGA/network_path/api_extension
-	url = ../api_extension.git
+	url = ../../Netnod/api_extension.git
 [submodule "FPGA/cores/keymem"]
 	path = FPGA/network_path/keymem
-	url = ../keymem.git
+	url = ../../Netnod/keymem.git
 [submodule "FPGA/cores/nts"]
 	path = FPGA/network_path/nts
-	url = ../nts.git
+	url = ../../Netnod/nts.git
 [submodule "FPGA/cores/nts_noncegen"]
 	path = FPGA/network_path/nts_noncegen
-	url = ../nts_noncegen.git
+	url = ../../Netnod/nts_noncegen.git
 [submodule "FPGA/cores/rosc_entropy"]
 	path = FPGA/cores/rosc_entropy
-	url = ../rosc_entropy
+	url = ../../Netnod/rosc_entropy
 [submodule "FPGA/cores/verilog-ethernet"]
 	path = FPGA/cores/verilog-ethernet
-	url = ../verilog-ethernet
+	url = ../../Netnod/verilog-ethernet
 [submodule "FPGA/cores/verilog-i2c"]
 	path = FPGA/cores/verilog-i2c
-	url = ../verilog-i2c
+	url = ../../Netnod/verilog-i2c
 [submodule "FPGA/cores/neorv32"]
 	path = FPGA/cores/neorv32
-	url = ../neorv32
+	url = ../../Netnod/neorv32
+[submodule "FPGA/cores/openfdk"]
+	path = FPGA/cores/openfdk
+	url = https://github.com/aristanetworks/openfdk.git
diff --git a/FPGA/cores/aes-siv b/FPGA/cores/aes-siv
index 4ee1036..32b3076 160000
--- a/FPGA/cores/aes-siv
+++ b/FPGA/cores/aes-siv
@@ -1 +1 @@
-Subproject commit 4ee10361149837f1896ae0d2b4e3a13a0edb29c2
+Subproject commit 32b307626b772b94d6a23aaa95bc63e2a1ef601a
diff --git a/FPGA/cores/download-and-unpack.sh b/FPGA/cores/download-and-unpack.sh
index b2885d9..5e55fbc 100755
--- a/FPGA/cores/download-and-unpack.sh
+++ b/FPGA/cores/download-and-unpack.sh
@@ -5,7 +5,7 @@ DOWNLOADS=../../downloads
 
 if [ ! -f v7_xt_conn_trd/readme.txt ]; then
     mkdir -p $DOWNLOADS
-    wget -nc -P $DOWNLOADS https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_3/rdf0285-vc709-connectivity-trd-2014-3.zip
+    wget -nv -nc -P $DOWNLOADS https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_3/rdf0285-vc709-connectivity-trd-2014-3.zip
     rm -rf v7_xt_conn_trd
     unzip -q $DOWNLOADS/rdf0285-vc709-connectivity-trd-2014-3.zip
 fi
diff --git a/FPGA/cores/openfdk b/FPGA/cores/openfdk
new file mode 160000
index 0000000..7406ee1
--- /dev/null
+++ b/FPGA/cores/openfdk
@@ -0,0 +1 @@
+Subproject commit 7406ee1357921fdfb4eee467b6ac9cf832828edd
diff --git a/FPGA/cores/verilog-i2c b/FPGA/cores/verilog-i2c
index ad307a0..ca6688c 160000
--- a/FPGA/cores/verilog-i2c
+++ b/FPGA/cores/verilog-i2c
@@ -1 +1 @@
-Subproject commit ad307a052510ddefcb1dbc3b699453439cf1a5ce
+Subproject commit ca6688ccea2b16749254125f29871aa9f273d6a3
diff --git a/FPGA/network_path/keymem b/FPGA/network_path/keymem
index 5134732..1c841da 160000
--- a/FPGA/network_path/keymem
+++ b/FPGA/network_path/keymem
@@ -1 +1 @@
-Subproject commit 51347325c4f08921003bcb998568a4098c2910dc
+Subproject commit 1c841da7ebf090dc0556cc0804e78055cdcbaed8
diff --git a/FPGA/network_path/nts b/FPGA/network_path/nts
index 3d62112..6e3a43f 160000
--- a/FPGA/network_path/nts
+++ b/FPGA/network_path/nts
@@ -1 +1 @@
-Subproject commit 3d621125e6062b1a26f97782922d3b48977c6463
+Subproject commit 6e3a43f3b70031e39361a08c190966574a9643b4
diff --git a/FPGA/network_path/nts_noncegen b/FPGA/network_path/nts_noncegen
index fcb9566..02a1c93 160000
--- a/FPGA/network_path/nts_noncegen
+++ b/FPGA/network_path/nts_noncegen
@@ -1 +1 @@
-Subproject commit fcb95664186fa0637b04687b4f6a9d486c89bbfb
+Subproject commit 02a1c934baac1e7f795911f6918777b0a9ff7a12
diff --git a/FPGA/targets/ntps_arista/Makefile b/FPGA/targets/ntps_arista/Makefile
index 0ba6e5a..9f253c7 100644
--- a/FPGA/targets/ntps_arista/Makefile
+++ b/FPGA/targets/ntps_arista/Makefile
@@ -30,7 +30,7 @@ BUILD_ID   ?= 1
 
 PROJECT_DIR         = $(CURDIR)
 ARISTA_FDK_VERSION ?= 2.5.0
-ARISTA_FDK_DIR     ?= $(PROJECT_DIR)/../../../arista_fdk-$(ARISTA_FDK_VERSION)
+ARISTA_FDK_DIR     ?= $(PROJECT_DIR)/../../openfdk
 ARISTA_SRC_DIR      = $(ARISTA_FDK_DIR)/src
 
 SOURCE_FILES = $(PROJECT_DIR)/src_files.json
@@ -131,20 +131,25 @@ app::
 	/bin/time nice make BOARDSTD="$(BOARDSTD)" 2>&1 | tee log
 
 #-------------------------------------------------------------------------------
-# Include Arista Build Scripts
-#-------------------------------------------------------------------------------
-include $(ARISTA_FDK_DIR)/resources/app.mk
-include $(ARISTA_FDK_DIR)/resources/vivado.mk
-
-#-------------------------------------------------------------------------------
-# Rules to copy user files from the FDK. 
-# FIXME: These should be migrated to the IP core instead. 
+# Rules to copy user files from the FDK.
+# FIXME: These should be migrated to the IP core instead.
 #-------------------------------------------------------------------------------
 
-$(APP_STAGING_DIR)/clockappdaemon.py $(APP_STAGING_DIR)/format_docstring.py: $(ARISTA_FDK_DIR)/examples/tscore/src/$$(@F)
+$(APP_STAGING_DIR)/clockappdaemon.py $(APP_STAGING_DIR)/format_docstring.py: $(ARISTA_FDK_DIR)/examples/tscore_nomac/src/$$(@F)
 	mkdir -p $(@D) && cp $< $@
 	echo $(APP_STAGING_DIR)
 
-$(APP_STAGING_DIR)/daemon/%:$(ARISTA_FDK_DIR)/examples/tscore/src/daemon/%
+$(APP_STAGING_DIR)/daemon/%:$(ARISTA_FDK_DIR)/examples/tscore_nomac/src/daemon/%
 	mkdir -p $(@D) && cp $< $@
 	echo $(APP_STAGING_DIR)
+
+
+#-------------------------------------------------------------------------------
+# Download the Xilinx sources if they don't exist
+#-------------------------------------------------------------------------------
+
+$(PROJECT_DIR)/../../cores/v7_xt_conn_trd/%: |$(PROJECT_DIR)/../../cores/v7_xt_conn_trd
+	@
+
+$(PROJECT_DIR)/../../cores/v7_xt_conn_trd: $(PROJECT_DIR)/../../cores/download-and-unpack.sh
+	cd $(<D) && bash $(<F)
diff --git a/FPGA/targets/ntps_arista/build.sh b/FPGA/targets/ntps_arista/build.sh
index 5aef371..e5f6f57 100755
--- a/FPGA/targets/ntps_arista/build.sh
+++ b/FPGA/targets/ntps_arista/build.sh
@@ -1,7 +1,7 @@
 #! /bin/bash
 set -euxo pipefail
 
-ARISTA_FDK_DIR=${ARISTA_FDK_DIR:-$(pwd)/../../../arista_fdk-2.5.0}
+ARISTA_FDK_DIR=${ARISTA_FDK_DIR:-$(pwd)/../../cores/openfdk}
 echo "Building using Arista FDK in $ARISTA_FDK_DIR"
 
 # I can't figure out how to put vhdl files in a library using the
@@ -17,7 +17,7 @@ find build/neorv32 build/processor -type f | xargs sed -i 's/neorv32\./work./g'
 vivado -nojournal -nolog -notrace -mode batch -source create_buildinfo.tcl
 
 /bin/time nice make ARISTA_FDK_DIR=$ARISTA_FDK_DIR BOARDSTD=lb2 2>&1 | tee log
-if ! test -f ntps-4.0.0.x86_64.rpm; then
+if ! test -f ntps-4.0.0.swix; then
     echo "Build failed" 1>&2
     exit 1
 fi
diff --git a/FPGA/targets/ntps_arista/src/ntps-lb2-cfg.json b/FPGA/targets/ntps_arista/src/ntps-lb2-cfg.json
index 2eeba68..f2c91df 100644
--- a/FPGA/targets/ntps_arista/src/ntps-lb2-cfg.json
+++ b/FPGA/targets/ntps_arista/src/ntps-lb2-cfg.json
@@ -2,54 +2,53 @@
     "license": "bsd-3-clause",
     "sources_1": [
         "${ARISTA_FDK_DIR}/src/arista_sysctl/arista_sysctl_v2.vhd",
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_ctrl_wrapper.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_parser_core.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_base_slave.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_drp_bridge.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_eeprom_controller.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_master.vhd", 
-        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_reg_protocol.vhd", 
-        "${ARISTA_FDK_DIR}/src/axi/amba_pkg.vhd", 
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_ctrl_wrapper.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/eeprom_parser_core.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_base_slave.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_drp_bridge.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_eeprom_controller.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_master.vhd",
+        "${ARISTA_FDK_DIR}/src/arista_sysctl/i2c_reg_protocol.vhd",
+        "${ARISTA_FDK_DIR}/src/axi/amba_pkg.vhd",
         "${ARISTA_FDK_DIR}/src/board_common/board_common_pkg.vhd",
-        "${ARISTA_FDK_DIR}/src/boards/lb2/board_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/clock_modules/ocxo_freq_trim_spi.vhd", 
-        "${ARISTA_FDK_DIR}/src/crc/crc8_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/fpga_spec/fpga_spec_pkg.vhd", 
+        "${ARISTA_FDK_DIR}/src/boards/lb2/board_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/clock_modules/ocxo_freq_trim_spi.vhd",
+        "${ARISTA_FDK_DIR}/src/crc/crc8_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/fpga_spec/fpga_spec_pkg.vhd",
         "${ARISTA_FDK_DIR}/src/hermes/hermes_pkg.vhd",
-        "${ARISTA_FDK_DIR}/src/hphy_xilinx/phy_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_controller.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_counter_ts.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_fe_re.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_iddr.vhd", 
-        "${ARISTA_FDK_DIR}/src/metachron/metachron_trigger_holdoff.vhd", 
-        "${ARISTA_FDK_DIR}/src/metamako/edge_detect.vhd", 
-        "${ARISTA_FDK_DIR}/src/metamako/metamako_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/metamako/pcie_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_clr.vhd", 
-        "${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_preset.vhd", 
-        "${ARISTA_FDK_DIR}/src/primitive_xilinx/xil_pllbase.vhd", 
+        "${ARISTA_FDK_DIR}/src/hphy_xilinx/phy_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_controller.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_counter_ts.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_fe_re.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_synchroniser_iddr.vhd",
+        "${ARISTA_FDK_DIR}/src/metachron/metachron_trigger_holdoff.vhd",
+        "${ARISTA_FDK_DIR}/src/metamako/edge_detect.vhd",
+        "${ARISTA_FDK_DIR}/src/metamako/metamako_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/metamako/pcie_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_clr.vhd",
+        "${ARISTA_FDK_DIR}/src/primitive_xilinx/mako_dff_preset.vhd",
+        "${ARISTA_FDK_DIR}/src/primitive_xilinx/xil_pllbase.vhd",
         "${ARISTA_FDK_DIR}/src/regfile/i2c_slave_deglitch.vhd",
-        "${ARISTA_FDK_DIR}/src/regfile/reg_file_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/regfile/reg_flexi_pkg.vhd", 
-        "${ARISTA_FDK_DIR}/src/regfile/reg_hs_counter.vhd", 
-        "${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_100M/sem_mit_100M.xci", 
-        "${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_78M125/sem_mit_78M125.xci", 
+        "${ARISTA_FDK_DIR}/src/regfile/reg_file_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/regfile/reg_flexi_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/regfile/reg_hs_counter.vhd",
+        "${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_100M/sem_mit_100M.xci",
+        "${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_78M125/sem_mit_78M125.xci",
         "${ARISTA_FDK_DIR}/src/seu/ip/xcvu9p-flgb2104-3-e/sem_mit_test_100M/sem_mit_test_100M.xci",
-        "${ARISTA_FDK_DIR}/src/seu/xil_sem.vhd", 
-        "${ARISTA_FDK_DIR}/src/spi/spi_master.vhd", 
-        "${ARISTA_FDK_DIR}/src/synchroniser/sync_pulse.vhd", 
-        "${ARISTA_FDK_DIR}/src/synchroniser/sync_tgl_to_pulse.vhd", 
-        "${ARISTA_FDK_DIR}/src/synchroniser/sync_vec.vhd", 
-        "${ARISTA_FDK_DIR}/src/synchroniser/synchroniser.vhd", 
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/clk_gen.vhd", 
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/time_sync.vhd", 
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/timestamper.vhd", 
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/timing_controller.vhd", 
+        "${ARISTA_FDK_DIR}/src/seu/xil_sem.vhd",
+        "${ARISTA_FDK_DIR}/src/spi/spi_master.vhd",
+        "${ARISTA_FDK_DIR}/src/synchroniser/sync_pulse.vhd",
+        "${ARISTA_FDK_DIR}/src/synchroniser/sync_tgl_to_pulse.vhd",
+        "${ARISTA_FDK_DIR}/src/synchroniser/sync_vec.vhd",
+        "${ARISTA_FDK_DIR}/src/synchroniser/synchroniser.vhd",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/clk_gen.vhd",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/time_sync.vhd",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/timestamper.vhd",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/timing_controller.vhd",
         "${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.vhd",
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/tscore_wrapper.vhd", 
-        "${ARISTA_FDK_DIR}/src/yart/drp_pkg.vhd",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/tscore_wrapper.vhd",
         "${ARISTA_FDK_DIR}/src/yart/yart_i2c.vhd",
         "${ARISTA_FDK_DIR}/src/yart/yart_leaf_decode_v2.vhd",
         "${ARISTA_FDK_DIR}/src/yart/yart_pkg.vhd",
@@ -188,8 +187,8 @@
     ],
     "constrs_1": [
         "${PROJECT_DIR}/../../cores/verilog-ethernet/lib/axis/syn/sync_reset.tcl",
-        "${ARISTA_FDK_DIR}/src/boards/lb2/board_constraints.xdc", 
-        "${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.xdc", 
+        "${ARISTA_FDK_DIR}/src/boards/lb2/board_constraints.xdc",
+        "${ARISTA_FDK_DIR}/src/ts_ipcore/tscore.xdc",
         "${PROJECT_DIR}/src/ntps-lb2-top.xdc"
-    ] 
+    ]
 }