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MostlyKIGuessMostlyKIGuess
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assembler for visualization and script
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3 files changed

+136
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‎pipelined/pipeline_visualization.sh‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
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# visualize_pipeline.sh
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#!/bin/bash
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mkdir -p test_results
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mkdir -p visualization
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# Check for test file argument
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if [ $# -eq 0 ]; then
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echo "Usage: $0 <test_file>"
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exit 1
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fi
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TEST_FILE=$1
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# Assemble the test file
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echo "Assembling test file..."
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python3 testcases/assembler.py "$TEST_FILE"
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# Compile Verilog files
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echo "Compiling Verilog files..."
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iverilog -o test_results/cpu_test \
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verilog/cpu_pipelined.v \
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verilog/testbench_pipelined.v \
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-I modules/
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if [ $? -eq 0 ]; then
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echo "Compilation successful!"
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# Run simulation and capture output
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echo "Running simulation..."
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vvp test_results/cpu_test | tee test_results/simulation_output.txt
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# Generate visualization data
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echo "Generating visualization data..."
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python3 visualization/parse-pipeline.py test_results/simulation_output.txt
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# Open visualization in browser
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echo "Opening visualization in browser..."
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xdg-open visualization/index.html 2>/dev/null || \
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open visualization/index.html 2>/dev/null || \
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echo "Please open visualization/index.html in your browser manually"
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echo "Visualization complete!"
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else
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echo "Compilation failed."
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exit 1
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fi

‎pipelined/testcases/assembler.py‎

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -329,7 +329,7 @@ def generate_testbench(instructions):
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$display("ID Stage: rs1=x%0d (%0d), rs2=x%0d (%0d), rd=x%0d",
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cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.reg_rd);
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332-
// Show EX stage activity (removed alu_control as it doesn't exist)
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// Show EX stage activity
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$display("EX Stage: ALU Result=%0h", cpu.alu_result);
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// Show MEM stage activity
@@ -349,6 +349,49 @@ def generate_testbench(instructions):
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$display("Control signals: branch=%b, mem_read=%b, mem_to_reg=%b, mem_write=%b, alu_src=%b, reg_write=%b",
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cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
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// Add pipeline register contents - MORE DETAILED INFO
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$display("Pipeline Registers:");
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$display("IF/ID: PC=%h, Instruction=%h", cpu.if_id_pc, cpu.if_id_instruction);
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$display("ID/EX: PC=%h, Instruction=%h, rs1=x%0d, rs2=x%0d, rd=x%0d, RegWrite=%b, MemWrite=%b",
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cpu.id_ex_pc, cpu.id_ex_instruction, cpu.id_ex_rs1, cpu.id_ex_rs2,
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cpu.id_ex_rd, cpu.id_ex_reg_write, cpu.id_ex_mem_write);
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$display("EX/MEM: Instruction=%h, rd=x%0d, RegWrite=%b, MemWrite=%b, ALUResult=%h",
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cpu.ex_mem_instruction, cpu.ex_mem_rd, cpu.ex_mem_reg_write,
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cpu.ex_mem_mem_write, cpu.ex_mem_alu_result);
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$display("MEM/WB: Instruction=%h, rd=x%0d, RegWrite=%b, MemToReg=%b",
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cpu.mem_wb_instruction, cpu.mem_wb_rd, cpu.mem_wb_reg_write,
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cpu.mem_wb_mem_to_reg);
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// Hazard detection information
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if (cpu.stall) begin // Use cpu.stall directly instead of cpu.hazard_detection_unit.stall_pipeline
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$display("HAZARD DETECTED: Stalling pipeline");
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$display("Load-use hazard between instructions at PC=%h and PC=%h",
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cpu.if_id_pc - 4, cpu.if_id_pc);
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end
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// Forwarding information
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if (cpu.forwardA != 0 || cpu.forwardB != 0) begin // Use cpu.forwardA/B directly
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$display("Forwarding active:");
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if (cpu.forwardA == 2'b10)
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$display("EX → EX Forwarding to rs1 (x%0d)", cpu.id_ex_rs1);
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if (cpu.forwardA == 2'b01)
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$display("MEM → EX Forwarding to rs1 (x%0d)", cpu.id_ex_rs1);
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if (cpu.forwardB == 2'b10)
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$display("EX → EX Forwarding to rs2 (x%0d)", cpu.id_ex_rs2);
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if (cpu.forwardB == 2'b01)
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$display("MEM → EX Forwarding to rs2 (x%0d)", cpu.id_ex_rs2);
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end
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// Branch information
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if (cpu.branch && cpu.zero) begin // Use cpu.zero instead of cpu.alu_zero
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$display("Branch at PC=%h: Taking branch", cpu.pc_current);
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if (cpu.branch_mispredicted) // Use cpu.branch_mispredicted directly
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$display("Branch mispredicted: Pipeline flush required");
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end
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// Pipeline stall/flush status
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if (cpu.flush) // Use cpu.flush instead of cpu.if_id_flush
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$display("Pipeline flushed");
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end
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end
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@@ -365,6 +408,7 @@ def generate_testbench(instructions):
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print(f"Generated testbench file: {output_file}")
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368412
def get_instruction_type(instruction):
369413
if instruction in ["add", "sub", "or", "and"]:
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return 'R'

‎pipelined/verilog/testbench_pipelined.v‎

Lines changed: 44 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ module testbench_pipelined();
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$display("ID Stage: rs1=x%0d (%0d), rs2=x%0d (%0d), rd=x%0d",
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cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.reg_rd);
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128-
// Show EX stage activity (removed alu_control as it doesn't exist)
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// Show EX stage activity
129129
$display("EX Stage: ALU Result=%0h", cpu.alu_result);
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131131
// Show MEM stage activity
@@ -145,6 +145,49 @@ module testbench_pipelined();
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$display("Control signals: branch=%b, mem_read=%b, mem_to_reg=%b, mem_write=%b, alu_src=%b, reg_write=%b",
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cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
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148+
// Add pipeline register contents - MORE DETAILED INFO
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$display("Pipeline Registers:");
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$display("IF/ID: PC=%h, Instruction=%h", cpu.if_id_pc, cpu.if_id_instruction);
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$display("ID/EX: PC=%h, Instruction=%h, rs1=x%0d, rs2=x%0d, rd=x%0d, RegWrite=%b, MemWrite=%b",
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cpu.id_ex_pc, cpu.id_ex_instruction, cpu.id_ex_rs1, cpu.id_ex_rs2,
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cpu.id_ex_rd, cpu.id_ex_reg_write, cpu.id_ex_mem_write);
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$display("EX/MEM: Instruction=%h, rd=x%0d, RegWrite=%b, MemWrite=%b, ALUResult=%h",
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cpu.ex_mem_instruction, cpu.ex_mem_rd, cpu.ex_mem_reg_write,
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cpu.ex_mem_mem_write, cpu.ex_mem_alu_result);
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$display("MEM/WB: Instruction=%h, rd=x%0d, RegWrite=%b, MemToReg=%b",
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cpu.mem_wb_instruction, cpu.mem_wb_rd, cpu.mem_wb_reg_write,
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cpu.mem_wb_mem_to_reg);
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161+
// Hazard detection information
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if (cpu.stall) begin // Use cpu.stall directly instead of cpu.hazard_detection_unit.stall_pipeline
163+
$display("HAZARD DETECTED: Stalling pipeline");
164+
$display("Load-use hazard between instructions at PC=%h and PC=%h",
165+
cpu.if_id_pc - 4, cpu.if_id_pc);
166+
end
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168+
// Forwarding information
169+
if (cpu.forwardA != 0 || cpu.forwardB != 0) begin // Use cpu.forwardA/B directly
170+
$display("Forwarding active:");
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if (cpu.forwardA == 2'b10)
172+
$display("EX → EX Forwarding to rs1 (x%0d)", cpu.id_ex_rs1);
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if (cpu.forwardA == 2'b01)
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$display("MEM → EX Forwarding to rs1 (x%0d)", cpu.id_ex_rs1);
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if (cpu.forwardB == 2'b10)
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$display("EX → EX Forwarding to rs2 (x%0d)", cpu.id_ex_rs2);
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if (cpu.forwardB == 2'b01)
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$display("MEM → EX Forwarding to rs2 (x%0d)", cpu.id_ex_rs2);
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end
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// Branch information
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if (cpu.branch && cpu.zero) begin // Use cpu.zero instead of cpu.alu_zero
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$display("Branch at PC=%h: Taking branch", cpu.pc_current);
184+
if (cpu.branch_mispredicted) // Use cpu.branch_mispredicted directly
185+
$display("Branch mispredicted: Pipeline flush required");
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end
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188+
// Pipeline stall/flush status
189+
if (cpu.flush) // Use cpu.flush instead of cpu.if_id_flush
190+
$display("Pipeline flushed");
148191
end
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end
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