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Commit 2932b25

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Merge branch 'working-hikey960-upstream-coresight' into working-hikey960-upstream-rebase-v4.14-rc7-2017-11-03-18-10-36
* working-hikey960-upstream-coresight: coresight: Fix disabling of CoreSight TPIU coresight: ETM: Add support for ARM Cortex-A73
2 parents 11c8ab0 + c4f8eaf commit 2932b25

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2 files changed

+24
-11
lines changed

2 files changed

+24
-11
lines changed

drivers/hwtracing/coresight/coresight-etm4x.c

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1034,7 +1034,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
10341034
}
10351035

10361036
pm_runtime_put(&adev->dev);
1037-
dev_info(dev, "%s initialized\n", (char *)id->data);
1037+
dev_info(dev, "CPU%d: %s initialized\n",
1038+
drvdata->cpu, (char *)id->data);
10381039

10391040
if (boot_enable) {
10401041
coresight_enable(drvdata->csdev);
@@ -1052,21 +1053,26 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
10521053
return ret;
10531054
}
10541055

1055-
static const struct amba_id etm4_ids[] = {
1056-
{ /* ETM 4.0 - Cortex-A53 */
1056+
static struct amba_id etm4_ids[] = {
1057+
{
10571058
.id = 0x000bb95d,
10581059
.mask = 0x000fffff,
1059-
.data = "ETM 4.0",
1060+
.data = "Cortex-A53 ETM v4.0",
10601061
},
1061-
{ /* ETM 4.0 - Cortex-A57 */
1062+
{
10621063
.id = 0x000bb95e,
10631064
.mask = 0x000fffff,
1064-
.data = "ETM 4.0",
1065+
.data = "Cortex-A57 ETM v4.0",
10651066
},
1066-
{ /* ETM 4.0 - A72, Maia, HiSilicon */
1067+
{
10671068
.id = 0x000bb95a,
10681069
.mask = 0x000fffff,
1069-
.data = "ETM 4.0",
1070+
.data = "Cortex-A72 ETM v4.0",
1071+
},
1072+
{
1073+
.id = 0x000bb959,
1074+
.mask = 0x000fffff,
1075+
.data = "Cortex-A73 ETM v4.0",
10701076
},
10711077
{ 0, 0},
10721078
};

drivers/hwtracing/coresight/coresight-tpiu.c

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,11 @@
4646
#define TPIU_ITATBCTR0 0xef8
4747

4848
/** register definition **/
49+
/* FFSR - 0x300 */
50+
#define FFSR_FT_STOPPED BIT(1)
4951
/* FFCR - 0x304 */
5052
#define FFCR_FON_MAN BIT(6)
53+
#define FFCR_STOP_FI BIT(12)
5154

5255
/**
5356
* @base: memory mapped base address for this component.
@@ -85,10 +88,14 @@ static void tpiu_disable_hw(struct tpiu_drvdata *drvdata)
8588
{
8689
CS_UNLOCK(drvdata->base);
8790

88-
/* Clear formatter controle reg. */
89-
writel_relaxed(0x0, drvdata->base + TPIU_FFCR);
91+
/* Clear formatter and stop on flush */
92+
writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR);
9093
/* Generate manual flush */
91-
writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
94+
writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
95+
/* Wait for flush to complete */
96+
coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN, 0);
97+
/* Wait for formatter to stop */
98+
coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED, 1);
9299

93100
CS_LOCK(drvdata->base);
94101
}

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