feat: example 1-3 and cocotb for example 1

Author: pineylilly

.gitignore

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+*.vcd
+*.vvp
+*.out
+__pycache__
+sim_build
+results.xml

ex01_and_gate/and_gate.v

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+module and_gate(a, b, out);
+    input a, b;
+    output out;
+
+    assign out = a & b;
+
+endmodule

ex01_and_gate/and_gate_tb.v

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+`timescale 1ns/1ns
+
+module and_gate_tb();
+    reg a, b;
+    wire out;
+
+    and_gate uut(a, b, out);
+
+    initial begin
+        $dumpfile("and_gate_tb.vcd");
+        $dumpvars(0, and_gate_tb);
+
+        a = 0;
+        b = 0;
+        #10 a = 1;
+        #10 b = 1;
+        #10 a = 0;
+        #10 b = 0;
+        #10 a = 1;
+        #10 b = 0;
+        #10 a = 0;
+        #10 b = 1;
+        #10 $finish;
+    end
+    
+endmodule

ex01_and_gate/test/Makefile

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+# Simulator
+SIM ?= icarus
+
+# Top level language
+TOPLEVEL_LANG ?= verilog
+
+# Files
+VERILOG_SOURCES = $(shell pwd)/../and_gate.v
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = and_gate
+
+# MODULE is the basename of the Python test file
+MODULE = and_gate_test
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim

ex01_and_gate/test/and_gate_test.py

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+import cocotb
+from cocotb.triggers import Timer
+
+@cocotb.test()
+async def and_gate_test(dut):
+    a = (0, 0, 1, 1)
+    b = (0, 1, 0, 1)
+    out = (0, 0, 0, 1)
+    
+    for i in range(4):
+        dut.a.value = a[i]
+        dut.b.value = b[i]
+        await Timer(1, units='ns')
+        assert dut.out.value == out[i], f"[Iteration {i}] output is {dut.out.value}, expected {out[i]}"

ex02_1_bit_full_adder/full_adder.v

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+module full_adder (a, b, cin, s, cout);
+    input a;
+    input b;
+    input cin;
+    output s;
+    output cout;
+    
+    assign {cout, s} = a + b + cin;
+
+endmodule

ex02_1_bit_full_adder/full_adder_tb.v

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+`timescale 1ns/1ns
+
+module full_adder_tb();
+    reg a, b, cin;
+    wire s, cout;
+
+    full_adder fa1 (a, b, cin, s, cout);
+
+    initial begin
+        $dumpfile("full_adder_tb.vcd");
+        $dumpvars(0, full_adder_tb);
+
+        a = 0;
+        b = 0;
+        cin = 0;
+        #10
+        a = 1;
+        #10
+        a = 0; 
+        b = 1;
+        #10
+        a = 1;
+        #10
+        a = 0;
+        b = 0;
+        cin = 1;
+        #10
+        a = 1;
+        #10
+        a = 0;
+        b = 1;
+        #10
+        a = 1;
+        #10
+        $finish;
+    end
+
+    always begin
+        #1 $display("a=%b, b=%b, cin=%b, s=%b, cout=%b", a, b, cin, s, cout);
+    end
+endmodule

ex03_4_bit_half_adder/half_adder_4.v

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+module half_adder_4(a, b, s, cout);
+    input [3:0] a;
+    input [3:0] b;
+    output [3:0] s;
+    output cout;
+    
+    assign {cout, s} = a + b;
+    
+endmodule

ex03_4_bit_half_adder/half_adder_4_tb.v

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+`timescale 1ns/1ns
+
+module half_adder_4_tb();
+    reg [3:0] a, b;
+    wire [3:0] s;
+    wire cout;
+
+    half_adder_4 ha1 (a, b, s, cout);
+
+    initial begin
+        $dumpfile("half_adder_4_tb.vcd");
+        $dumpvars(0, half_adder_4_tb);
+
+        a = 4'b0000;
+        b = 4'b0000;
+        #10
+        a = 4'b0001;
+        #10
+        a = 4'b0000; 
+        b = 4'b0001;
+        #10
+        a = 4'b0001;
+        #10
+        a = 4'b0010;
+        b = 4'b0000;
+        #10
+        a = 4'b0011;
+        #10
+        a = 4'b0100;
+        b = 4'b0001;
+        #10
+        a = 4'b0111;
+        b = 4'b0011;
+        #10
+        a = 4'b1111;
+        b = 4'b0001;
+        #10
+        a = 4'b1111;
+        b = 4'b0010;
+        #10
+        a = 4'b0001;
+        b = 4'b1111;
+        #10
+        a = 4'b0110;
+        b = 4'b1111;
+        #10
+        a = 4'b1111;
+        b = 4'b1111;
+        #10
+        $finish;
+    end
+
+    always begin
+        #1 $display("a=%b, b=%b, s=%b, cout=%b", a, b, s, cout);
+    end
+endmodule