feat: build and simulate all for better

Author: yokeTH

Makefile

@@ -32,11 +32,31 @@ build-all:
 	@for subdir in $(SUBDIRS); do \
 		$(MAKE) -C $$subdir build; \
 	done
+		@for source in $(BETTER_SOURCES); do \
+		dir="$$(dirname $$source)/test"; \
+		module_name="$$(basename $$source .v)"; \
+		echo "Processing $$source in $$dir"; \
+		if [ ! -f "$$source" ]; then \
+			echo "Error: Verilog source file $$source not found" >&2; \
+			continue; \
+		fi; \
+		$(MAKE) -C $$dir TOPLEVEL=$$module_name VERILOG_SOURCES=$$source build; \
+	done
 
 simulate-all:
 	@for subdir in $(SUBDIRS); do \
 		$(MAKE) -C $$subdir simulate; \
 	done
+		@for source in $(BETTER_SOURCES); do \
+		dir="$$(dirname $$source)/test"; \
+		module_name="$$(basename $$source .v)"; \
+		echo "Processing $$source in $$dir"; \
+		if [ ! -f "$$source" ]; then \
+			echo "Error: Verilog source file $$source not found" >&2; \
+			continue; \
+		fi; \
+		$(MAKE) -C $$dir TOPLEVEL=$$module_name VERILOG_SOURCES=$$source simulate; \
+	done
 
 build-simulate-all:
 	$(MAKE) build-all;